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Yatharth Kocharb1c2fe02015-10-14 15:27:24 +01001/*
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +01005 */
6
7#include <platform_def.h>
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +00008#include <xlat_tables_defs.h>
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +01009
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(bl2u_entrypoint)
13
14MEMORY {
15 RAM (rwx): ORIGIN = BL2U_BASE, LENGTH = BL2U_LIMIT - BL2U_BASE
16}
17
18
19SECTIONS
20{
21 . = BL2U_BASE;
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000022 ASSERT(. == ALIGN(PAGE_SIZE),
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010023 "BL2U_BASE address is not aligned on a page boundary.")
24
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010025#if SEPARATE_CODE_AND_RODATA
26 .text . : {
27 __TEXT_START__ = .;
28 *bl2u_entrypoint.o(.text*)
29 *(.text*)
30 *(.vectors)
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000031 . = NEXT(PAGE_SIZE);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010032 __TEXT_END__ = .;
33 } >RAM
34
35 .rodata . : {
36 __RODATA_START__ = .;
37 *(.rodata*)
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000038 . = NEXT(PAGE_SIZE);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010039 __RODATA_END__ = .;
40 } >RAM
41#else
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010042 ro . : {
43 __RO_START__ = .;
44 *bl2u_entrypoint.o(.text*)
45 *(.text*)
46 *(.rodata*)
47
48 *(.vectors)
49 __RO_END_UNALIGNED__ = .;
50 /*
51 * Memory page(s) mapped to this section will be marked as
52 * read-only, executable. No RW data from the next section must
53 * creep in. Ensure the rest of the current memory page is unused.
54 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000055 . = NEXT(PAGE_SIZE);
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010056 __RO_END__ = .;
57 } >RAM
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010058#endif
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010059
60 /*
61 * Define a linker symbol to mark start of the RW memory area for this
62 * image.
63 */
64 __RW_START__ = . ;
65
Douglas Raillard306593d2017-02-24 18:14:15 +000066 /*
67 * .data must be placed at a lower address than the stacks if the stack
68 * protector is enabled. Alternatively, the .data.stack_protector_canary
69 * section can be placed independently of the main .data section.
70 */
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010071 .data . : {
72 __DATA_START__ = .;
73 *(.data*)
74 __DATA_END__ = .;
75 } >RAM
76
77 stacks (NOLOAD) : {
78 __STACKS_START__ = .;
79 *(tzfw_normal_stacks)
80 __STACKS_END__ = .;
81 } >RAM
82
83 /*
84 * The .bss section gets initialised to 0 at runtime.
Douglas Raillard21362a92016-12-02 13:51:54 +000085 * Its base address should be 16-byte aligned for better performance of the
86 * zero-initialization code.
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +010087 */
88 .bss : ALIGN(16) {
89 __BSS_START__ = .;
90 *(SORT_BY_ALIGNMENT(.bss*))
91 *(COMMON)
92 __BSS_END__ = .;
93 } >RAM
94
95 /*
96 * The xlat_table section is for full, aligned page tables (4K).
97 * Removing them from .bss avoids forcing 4K alignment on
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +000098 * the .bss section. The tables are initialized to zero by the translation
99 * tables library.
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +0100100 */
101 xlat_table (NOLOAD) : {
102 *(xlat_table)
103 } >RAM
104
105#if USE_COHERENT_MEM
106 /*
107 * The base address of the coherent memory section must be page-aligned (4K)
108 * to guarantee that the coherent data are stored on their own pages and
109 * are not mixed with normal data. This is required to set up the correct
110 * memory attributes for the coherent data page tables.
111 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000112 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +0100113 __COHERENT_RAM_START__ = .;
114 *(tzfw_coherent_mem)
115 __COHERENT_RAM_END_UNALIGNED__ = .;
116 /*
117 * Memory page(s) mapped to this section will be marked
118 * as device memory. No other unexpected data must creep in.
119 * Ensure the rest of the current memory page is unused.
120 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000121 . = NEXT(PAGE_SIZE);
Yatharth Kocharb1c2fe02015-10-14 15:27:24 +0100122 __COHERENT_RAM_END__ = .;
123 } >RAM
124#endif
125
126 /*
127 * Define a linker symbol to mark end of the RW memory area for this
128 * image.
129 */
130 __RW_END__ = .;
131 __BL2U_END__ = .;
132
133 __BSS_SIZE__ = SIZEOF(.bss);
134
135 ASSERT(. <= BL2U_LIMIT, "BL2U image has exceeded its limit.")
136}