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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <asm_macros.S>
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010033#include <el3_common_macros.S>
Dan Handley2bd4ef22014-04-09 13:14:54 +010034#include <psci.h>
Achin Guptae1aa5162014-06-26 09:58:52 +010035#include <xlat_tables.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010036
Soby Mathew981487a2015-07-13 14:10:57 +010037 .globl psci_entrypoint
Achin Gupta42c52802014-05-09 19:32:25 +010038 .globl psci_power_down_wfi
Achin Gupta4f6ad662013-10-25 09:08:21 +010039
Soby Mathew981487a2015-07-13 14:10:57 +010040 /* --------------------------------------------------------------------
41 * This CPU has been physically powered up. It is either resuming from
42 * suspend or has simply been turned on. In both cases, call the power
43 * on finisher.
44 * --------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +010045 */
Soby Mathew981487a2015-07-13 14:10:57 +010046func psci_entrypoint
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010047 /*
48 * On the warm boot path, most of the EL3 initialisations performed by
49 * 'el3_entrypoint_common' must be skipped:
50 *
Juan Castillo7d199412015-12-14 09:35:25 +000051 * - Only when the platform bypasses the BL1/BL31 entrypoint by
Sandrine Bailleux449dbd52015-06-02 17:19:43 +010052 * programming the reset address do we need to set the CPU endianness.
53 * In other cases, we assume this has been taken care by the
54 * entrypoint code.
55 *
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010056 * - No need to determine the type of boot, we know it is a warm boot.
57 *
58 * - Do not try to distinguish between primary and secondary CPUs, this
59 * notion only exists for a cold boot.
60 *
61 * - No need to initialise the memory or the C runtime environment,
62 * it has been done once and for all on the cold boot path.
Achin Guptae1aa5162014-06-26 09:58:52 +010063 */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010064 el3_entrypoint_common \
Sandrine Bailleux449dbd52015-06-02 17:19:43 +010065 _set_endian=PROGRAMMABLE_RESET_ADDRESS \
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010066 _warm_boot_mailbox=0 \
67 _secondary_cold_boot=0 \
68 _init_memory=0 \
69 _init_c_runtime=0 \
70 _exception_vectors=runtime_exceptions
Achin Guptae1aa5162014-06-26 09:58:52 +010071
72 /* --------------------------------------------
73 * Enable the MMU with the DCache disabled. It
74 * is safe to use stacks allocated in normal
75 * memory as a result. All memory accesses are
76 * marked nGnRnE when the MMU is disabled. So
77 * all the stack writes will make it to memory.
78 * All memory accesses are marked Non-cacheable
79 * when the MMU is enabled but D$ is disabled.
80 * So used stack memory is guaranteed to be
81 * visible immediately after the MMU is enabled
82 * Enabling the DCache at the same time as the
83 * MMU can lead to speculatively fetched and
84 * possibly stale stack memory being read from
85 * other caches. This can lead to coherency
86 * issues.
87 * --------------------------------------------
88 */
89 mov x0, #DISABLE_DCACHE
90 bl bl31_plat_enable_mmu
Achin Gupta4f6ad662013-10-25 09:08:21 +010091
Soby Mathew981487a2015-07-13 14:10:57 +010092 bl psci_power_up_finish
Achin Gupta4f6ad662013-10-25 09:08:21 +010093
Jeenu Viswambharancaa84932014-02-06 10:36:15 +000094 b el3_exit
Soby Mathew981487a2015-07-13 14:10:57 +010095endfunc psci_entrypoint
Achin Gupta4f6ad662013-10-25 09:08:21 +010096
Achin Gupta42c52802014-05-09 19:32:25 +010097 /* --------------------------------------------
98 * This function is called to indicate to the
99 * power controller that it is safe to power
100 * down this cpu. It should not exit the wfi
101 * and will be released from reset upon power
102 * up. 'wfi_spill' is used to catch erroneous
103 * exits from wfi.
104 * --------------------------------------------
105 */
106func psci_power_down_wfi
Andrew Thoelke42e75a72014-04-28 12:28:39 +0100107 dsb sy // ensure write buffer empty
Achin Gupta4f6ad662013-10-25 09:08:21 +0100108 wfi
109wfi_spill:
110 b wfi_spill
Kévin Petita877c252015-03-24 14:03:57 +0000111endfunc psci_power_down_wfi
Achin Gupta4f6ad662013-10-25 09:08:21 +0100112