Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1 | /* |
Marek Vasut | 2dd95b8 | 2019-06-14 01:41:10 +0200 | [diff] [blame] | 2 | * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <stdint.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | |
| 9 | #include <common/debug.h> |
| 10 | |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 11 | #include "../qos_common.h" |
Marek Vasut | 2dd95b8 | 2019-06-14 01:41:10 +0200 | [diff] [blame] | 12 | #include "../qos_reg.h" |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 13 | #include "qos_init_m3_v10.h" |
| 14 | |
| 15 | #define RCAR_QOS_VERSION "rev.0.19" |
| 16 | |
Marek Vasut | 92c7efc | 2019-06-14 01:44:43 +0200 | [diff] [blame] | 17 | #include "qos_init_m3_v10_mstat.h" |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 18 | |
| 19 | static void dbsc_setting(void) |
| 20 | { |
| 21 | uint32_t md = 0; |
| 22 | |
| 23 | /* BUFCAM settings */ |
| 24 | /* DBSC_DBCAM0CNF0 not set */ |
| 25 | io_write_32(DBSC_DBCAM0CNF1, 0x00043218); /* dbcam0cnf1 */ |
| 26 | io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); /* dbcam0cnf2 */ |
| 27 | io_write_32(DBSC_DBCAM0CNF3, 0x00000000); /* dbcam0cnf3 */ |
| 28 | io_write_32(DBSC_DBSCHCNT0, 0x080F0037); /* dbschcnt0 */ |
| 29 | /* DBSC_DBSCHCNT1 not set */ |
| 30 | io_write_32(DBSC_DBSCHSZ0, 0x00000001); /* dbschsz0 */ |
| 31 | io_write_32(DBSC_DBSCHRW0, 0x22421111); /* dbschrw0 */ |
| 32 | |
| 33 | md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17; |
| 34 | |
| 35 | switch (md) { |
| 36 | case 0x0: |
| 37 | /* DDR3200 */ |
| 38 | io_write_32(DBSC_SCFCTST2, 0x012F1123); |
| 39 | break; |
| 40 | case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */ |
| 41 | /* DDR2800 */ |
| 42 | io_write_32(DBSC_SCFCTST2, 0x012F1123); |
| 43 | break; |
| 44 | case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */ |
| 45 | /* DDR2400 */ |
| 46 | io_write_32(DBSC_SCFCTST2, 0x012F1123); |
| 47 | break; |
| 48 | default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */ |
| 49 | /* DDR1600 */ |
| 50 | io_write_32(DBSC_SCFCTST2, 0x012F1123); |
| 51 | break; |
| 52 | } |
| 53 | |
| 54 | /* QoS Settings */ |
Marek Vasut | 2dd95b8 | 2019-06-14 01:41:10 +0200 | [diff] [blame] | 55 | io_write_32(DBSC_DBSCHQOS00, 0x00000F00); |
| 56 | io_write_32(DBSC_DBSCHQOS01, 0x00000B00); |
| 57 | io_write_32(DBSC_DBSCHQOS02, 0x00000000); |
| 58 | io_write_32(DBSC_DBSCHQOS03, 0x00000000); |
| 59 | /* DBSC_DBSCHQOS10 not set */ |
| 60 | /* DBSC_DBSCHQOS11 not set */ |
| 61 | /* DBSC_DBSCHQOS12 not set */ |
| 62 | /* DBSC_DBSCHQOS13 not set */ |
| 63 | /* DBSC_DBSCHQOS20 not set */ |
| 64 | /* DBSC_DBSCHQOS21 not set */ |
| 65 | /* DBSC_DBSCHQOS22 not set */ |
| 66 | /* DBSC_DBSCHQOS23 not set */ |
| 67 | /* DBSC_DBSCHQOS30 not set */ |
| 68 | /* DBSC_DBSCHQOS31 not set */ |
| 69 | /* DBSC_DBSCHQOS32 not set */ |
| 70 | /* DBSC_DBSCHQOS33 not set */ |
| 71 | io_write_32(DBSC_DBSCHQOS40, 0x00000300); |
| 72 | io_write_32(DBSC_DBSCHQOS41, 0x000002F0); |
| 73 | io_write_32(DBSC_DBSCHQOS42, 0x00000200); |
| 74 | io_write_32(DBSC_DBSCHQOS43, 0x00000100); |
| 75 | /* DBSC_DBSCHQOS50 not set */ |
| 76 | /* DBSC_DBSCHQOS51 not set */ |
| 77 | /* DBSC_DBSCHQOS52 not set */ |
| 78 | /* DBSC_DBSCHQOS53 not set */ |
| 79 | /* DBSC_DBSCHQOS60 not set */ |
| 80 | /* DBSC_DBSCHQOS61 not set */ |
| 81 | /* DBSC_DBSCHQOS62 not set */ |
| 82 | /* DBSC_DBSCHQOS63 not set */ |
| 83 | /* DBSC_DBSCHQOS70 not set */ |
| 84 | /* DBSC_DBSCHQOS71 not set */ |
| 85 | /* DBSC_DBSCHQOS72 not set */ |
| 86 | /* DBSC_DBSCHQOS73 not set */ |
| 87 | /* DBSC_DBSCHQOS80 not set */ |
| 88 | /* DBSC_DBSCHQOS81 not set */ |
| 89 | /* DBSC_DBSCHQOS82 not set */ |
| 90 | /* DBSC_DBSCHQOS83 not set */ |
| 91 | io_write_32(DBSC_DBSCHQOS90, 0x00000300); |
| 92 | io_write_32(DBSC_DBSCHQOS91, 0x000002F0); |
| 93 | io_write_32(DBSC_DBSCHQOS92, 0x00000200); |
| 94 | io_write_32(DBSC_DBSCHQOS93, 0x00000100); |
| 95 | /* DBSC_DBSCHQOS100 not set */ |
| 96 | /* DBSC_DBSCHQOS101 not set */ |
| 97 | /* DBSC_DBSCHQOS102 not set */ |
| 98 | /* DBSC_DBSCHQOS103 not set */ |
| 99 | /* DBSC_DBSCHQOS110 not set */ |
| 100 | /* DBSC_DBSCHQOS111 not set */ |
| 101 | /* DBSC_DBSCHQOS112 not set */ |
| 102 | /* DBSC_DBSCHQOS113 not set */ |
| 103 | /* DBSC_DBSCHQOS120 not set */ |
| 104 | /* DBSC_DBSCHQOS121 not set */ |
| 105 | /* DBSC_DBSCHQOS122 not set */ |
| 106 | /* DBSC_DBSCHQOS123 not set */ |
| 107 | io_write_32(DBSC_DBSCHQOS130, 0x00000100); |
| 108 | io_write_32(DBSC_DBSCHQOS131, 0x000000F0); |
| 109 | io_write_32(DBSC_DBSCHQOS132, 0x000000A0); |
| 110 | io_write_32(DBSC_DBSCHQOS133, 0x00000040); |
| 111 | io_write_32(DBSC_DBSCHQOS140, 0x000000C0); |
| 112 | io_write_32(DBSC_DBSCHQOS141, 0x000000B0); |
| 113 | io_write_32(DBSC_DBSCHQOS142, 0x00000080); |
| 114 | io_write_32(DBSC_DBSCHQOS143, 0x00000040); |
| 115 | io_write_32(DBSC_DBSCHQOS150, 0x00000040); |
| 116 | io_write_32(DBSC_DBSCHQOS151, 0x00000030); |
| 117 | io_write_32(DBSC_DBSCHQOS152, 0x00000020); |
| 118 | io_write_32(DBSC_DBSCHQOS153, 0x00000010); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | void qos_init_m3_v10(void) |
| 122 | { |
| 123 | dbsc_setting(); |
| 124 | |
| 125 | /* DRAM Split Address mapping */ |
| 126 | #if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH |
| 127 | #if RCAR_LSI == RCAR_M3 |
| 128 | #error "Don't set DRAM Split 4ch(M3)" |
| 129 | #else |
| 130 | ERROR("DRAM Split 4ch not supported.(M3)"); |
| 131 | panic(); |
| 132 | #endif |
| 133 | #elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \ |
| 134 | (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO) |
| 135 | NOTICE("BL2: DRAM Split is 2ch\n"); |
| 136 | io_write_32(AXI_ADSPLCR0, 0x00000000U); |
| 137 | io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT |
| 138 | | ADSPLCR0_SPLITSEL(0xFFU) |
| 139 | | ADSPLCR0_AREA(0x1CU) |
| 140 | | ADSPLCR0_SWP); |
| 141 | io_write_32(AXI_ADSPLCR2, 0x089A0000U); |
| 142 | io_write_32(AXI_ADSPLCR3, 0x00000000U); |
| 143 | #else |
| 144 | NOTICE("BL2: DRAM Split is OFF\n"); |
| 145 | #endif |
| 146 | |
| 147 | #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) |
| 148 | #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT |
| 149 | NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); |
| 150 | #endif |
| 151 | |
| 152 | /* Resource Alloc setting */ |
Marek Vasut | 2dd95b8 | 2019-06-14 01:41:10 +0200 | [diff] [blame] | 153 | io_write_32(QOSCTRL_RAS, 0x00000028U); |
| 154 | io_write_32(QOSCTRL_FIXTH, 0x000F0005U); |
| 155 | io_write_32(QOSCTRL_REGGD, 0x00000000U); |
| 156 | io_write_64(QOSCTRL_DANN, 0x0101010102020201UL); |
| 157 | io_write_32(QOSCTRL_DANT, 0x00100804U); |
| 158 | io_write_32(QOSCTRL_EC, 0x00000000U); |
| 159 | io_write_64(QOSCTRL_EMS, 0x0000000000000000UL); |
| 160 | io_write_32(QOSCTRL_FSS, 0x000003e8U); |
| 161 | io_write_32(QOSCTRL_INSFC, 0xC7840001U); |
| 162 | io_write_32(QOSCTRL_BERR, 0x00000000U); |
| 163 | io_write_32(QOSCTRL_RACNT0, 0x00000000U); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 164 | |
Marek Vasut | 2dd95b8 | 2019-06-14 01:41:10 +0200 | [diff] [blame] | 165 | /* QOSBW setting */ |
| 166 | io_write_32(QOSCTRL_SL_INIT, |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 167 | SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK); |
Marek Vasut | 2dd95b8 | 2019-06-14 01:41:10 +0200 | [diff] [blame] | 168 | io_write_32(QOSCTRL_REF_ARS, 0x00330000U); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 169 | |
Marek Vasut | 2dd95b8 | 2019-06-14 01:41:10 +0200 | [diff] [blame] | 170 | /* QOSBW SRAM setting */ |
Marek Vasut | 5753df4 | 2019-06-14 01:39:27 +0200 | [diff] [blame^] | 171 | uint32_t i; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 172 | |
Marek Vasut | 5753df4 | 2019-06-14 01:39:27 +0200 | [diff] [blame^] | 173 | for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { |
| 174 | io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); |
| 175 | io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); |
| 176 | } |
| 177 | for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { |
| 178 | io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); |
| 179 | io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 180 | } |
| 181 | |
| 182 | /* 3DG bus Leaf setting */ |
| 183 | io_write_32(0xFD820808U, 0x00001234U); |
| 184 | io_write_32(0xFD820800U, 0x00000006U); |
| 185 | io_write_32(0xFD821800U, 0x00000006U); |
| 186 | io_write_32(0xFD822800U, 0x00000006U); |
| 187 | io_write_32(0xFD823800U, 0x00000006U); |
| 188 | io_write_32(0xFD824800U, 0x00000006U); |
| 189 | io_write_32(0xFD825800U, 0x00000006U); |
| 190 | io_write_32(0xFD826800U, 0x00000006U); |
| 191 | io_write_32(0xFD827800U, 0x00000006U); |
| 192 | |
| 193 | /* RT bus Leaf setting */ |
| 194 | io_write_32(0xFFC50800U, 0x00000000U); |
| 195 | io_write_32(0xFFC51800U, 0x00000000U); |
| 196 | |
| 197 | /* Resource Alloc start */ |
Marek Vasut | 2dd95b8 | 2019-06-14 01:41:10 +0200 | [diff] [blame] | 198 | io_write_32(QOSCTRL_RAEN, 0x00000001U); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 199 | |
Marek Vasut | 2dd95b8 | 2019-06-14 01:41:10 +0200 | [diff] [blame] | 200 | /* QOSBW start */ |
| 201 | io_write_32(QOSCTRL_STATQC, 0x00000001U); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 202 | #else |
| 203 | NOTICE("BL2: QoS is None\n"); |
| 204 | |
| 205 | /* Resource Alloc setting */ |
Marek Vasut | 2dd95b8 | 2019-06-14 01:41:10 +0200 | [diff] [blame] | 206 | io_write_32(QOSCTRL_EC, 0x00000000U); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 207 | /* Resource Alloc start */ |
Marek Vasut | 2dd95b8 | 2019-06-14 01:41:10 +0200 | [diff] [blame] | 208 | io_write_32(QOSCTRL_RAEN, 0x00000001U); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 209 | #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ |
| 210 | } |