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Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001Build Options
2=============
3
4The TF-A build system supports the following build options. Unless mentioned
5otherwise, these options are expected to be specified at the build command
6line and are not to be modified in any component makefiles. Note that the
7build system doesn't track dependency for build options. Therefore, if any of
8the build options are changed from a previous build, a clean build must be
9performed.
10
11.. _build_options_common:
12
13Common build options
14--------------------
15
16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the
17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to
18 code having a smaller resulting size.
19
20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
22 directory containing the SP source, relative to the ``bl32/``; the directory
23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
24
johpow01fa59c6f2020-10-02 13:41:11 -050025- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return
26 zero at all but the highest implemented exception level. Reads from the
27 memory mapped view are unaffected by this control.
28
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010029- ``ARCH`` : Choose the target build architecture for TF-A. It can take either
30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
31 ``aarch64``.
32
Alexei Fedorov132e6652020-12-07 16:38:53 +000033- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies
34 one or more feature modifiers. This option has the form ``[no]feature+...``
35 and defaults to ``none``. It translates into compiler option
36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the
37 list of supported feature modifiers.
38
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010039- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
42 :ref:`Firmware Design`.
43
44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`.
47
Manish V Badarkheb59efca2023-06-27 11:40:21 +010048- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded
49 SP nodes in tb_fw_config.
50
51- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the
52 SPMC Core manifest. Valid when ``SPD=spmd`` is selected.
53
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010054- ``BL2``: This is an optional build option which specifies the path to BL2
55 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
56 built.
57
58- ``BL2U``: This is an optional build option which specifies the path to
59 BL2U image. In this case, the BL2U in TF-A will not be built.
60
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -060061- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset
62 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
63 entrypoint) or 1 (CPU reset to BL2 entrypoint).
64 The default value is 0.
65
66- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3.
67 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be
68 true in a 4-world system where RESET_TO_BL2 is 0.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010069
Balint Dobszay719ba9c2021-03-26 16:23:18 +010070- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the
71 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided.
72
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010073- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
74 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
75 the RW sections in RAM, while leaving the RO sections in place. This option
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -060076 enable this use-case. For now, this option is only supported
77 when RESET_TO_BL2 is set to '1'.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010078
79- ``BL31``: This is an optional build option which specifies the path to
80 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
81 be built.
82
83- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
84 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
85 this file name will be used to save the key.
86
87- ``BL32``: This is an optional build option which specifies the path to
88 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
89 be built.
90
91- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
92 Trusted OS Extra1 image for the ``fip`` target.
93
94- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
95 Trusted OS Extra2 image for the ``fip`` target.
96
97- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
98 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
99 this file name will be used to save the key.
100
101- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
102 ``fip`` target in case TF-A BL2 is used.
103
104- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
105 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
106 this file name will be used to save the key.
107
108- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication
109 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves.
110 If enabled, it is needed to use a compiler that supports the option
111 ``-mbranch-protection``. Selects the branch protection features to use:
112- 0: Default value turns off all types of branch protection
113- 1: Enables all types of branch protection features
114- 2: Return address signing to its standard level
115- 3: Extend the signing to include leaf functions
Alexei Fedorove039e482020-06-19 14:33:49 +0100116- 4: Turn on branch target identification mechanism
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100117
118 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options
119 and resulting PAuth/BTI features.
120
121 +-------+--------------+-------+-----+
122 | Value | GCC option | PAuth | BTI |
123 +=======+==============+=======+=====+
124 | 0 | none | N | N |
125 +-------+--------------+-------+-----+
126 | 1 | standard | Y | Y |
127 +-------+--------------+-------+-----+
128 | 2 | pac-ret | Y | N |
129 +-------+--------------+-------+-----+
130 | 3 | pac-ret+leaf | Y | N |
131 +-------+--------------+-------+-----+
Alexei Fedorove039e482020-06-19 14:33:49 +0100132 | 4 | bti | N | Y |
133 +-------+--------------+-------+-----+
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100134
Manish Pandey34a305e2021-10-21 21:53:49 +0100135 This option defaults to 0.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100136 Note that Pointer Authentication is enabled for Non-secure world
137 irrespective of the value of this option if the CPU supports it.
138
139- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
140 compilation of each build. It must be set to a C string (including quotes
141 where applicable). Defaults to a string that contains the time and date of
142 the compilation.
143
144- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A
145 build to be uniquely identified. Defaults to the current git commit id.
146
Grant Likely388248a2020-07-30 08:50:10 +0100147- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build``
148
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100149- ``CFLAGS``: Extra user options appended on the compiler's command line in
150 addition to the options set by the build system.
151
152- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
153 release several CPUs out of reset. It can take either 0 (several CPUs may be
154 brought up) or 1 (only one CPU will ever be brought up during cold reset).
155 Default is 0. If the platform always brings up a single CPU, there is no
156 need to distinguish between primary and secondary CPUs and the boot path can
157 be optimised. The ``plat_is_my_cpu_primary()`` and
158 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
159 to be implemented in this case.
160
Sandrine Bailleuxd4c1d442020-01-15 10:23:25 +0100161- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust.
162 Defaults to ``tbbr``.
163
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100164- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
165 register state when an unexpected exception occurs during execution of
166 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
167 this is only enabled for a debug build of the firmware.
168
169- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
170 certificate generation tool to create new keys in case no valid keys are
171 present or specified. Allowed options are '0' or '1'. Default is '1'.
172
173- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
174 the AArch32 system registers to be included when saving and restoring the
175 CPU context. The option must be set to 0 for AArch64-only platforms (that
176 is on hardware that does not implement AArch32, or at least not at EL1 and
177 higher ELs). Default value is 1.
178
179- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
180 registers to be included when saving and restoring the CPU context. Default
181 is 0.
182
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000183- ``CTX_INCLUDE_MTE_REGS``: Numeric value to include Memory Tagging Extension
184 registers in cpu context. This must be enabled, if the platform wants to use
185 this feature in the Secure world and MTE is enabled at ELX. This flag can
186 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism.
187 Default value is 0.
Arunachalam Ganapathydd3ec7e2020-05-28 11:57:09 +0100188
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000189- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV
190 registers to be saved/restored when entering/exiting an EL2 execution
191 context. This flag can take values 0 to 2, to align with the
192 ``FEATURE_DETECTION`` mechanism. Default value is 0.
193
194- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer
195 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers
196 to be included when saving and restoring the CPU context as part of world
197 switch. This flag can take values 0 to 2, to align with ``FEATURE_DETECTION``
198 mechanism. Default value is 0.
199
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100200 Note that Pointer Authentication is enabled for Non-secure world irrespective
201 of the value of this flag if the CPU supports it.
202
203- ``DEBUG``: Chooses between a debug and release build. It can take either 0
204 (release) or 1 (debug) as values. 0 is the default.
205
Sumit Garg392e4df2019-11-15 10:43:00 +0530206- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the
207 authenticated decryption algorithm to be used to decrypt firmware/s during
208 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of
209 this flag is ``none`` to disable firmware decryption which is an optional
Manish Pandey34a305e2021-10-21 21:53:49 +0100210 feature as per TBBR.
Sumit Garg392e4df2019-11-15 10:43:00 +0530211
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100212- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation
213 of the binary image. If set to 1, then only the ELF image is built.
214 0 is the default.
215
Boyan Karatotev677ed8a2023-02-16 09:45:29 +0000216- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded
217 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards.
218 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION``
219 mechanism. Default is ``0``.
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000220
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100221- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
222 Board Boot authentication at runtime. This option is meant to be enabled only
223 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
224 flag has to be enabled. 0 is the default.
225
226- ``E``: Boolean option to make warnings into errors. Default is 1.
227
Boyan Karatoteve9e7e8a2022-12-07 10:26:48 +0000228 When specifying higher warnings levels (``W=1`` and higher), this option
229 defaults to 0. This is done to encourage contributors to use them, as they
230 are expected to produce warnings that would otherwise fail the build. New
231 contributions are still expected to build with ``W=0`` and ``E=1`` (the
232 default).
233
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100234- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
235 the normal boot flow. It must specify the entry point address of the EL3
236 payload. Please refer to the "Booting an EL3 payload" section for more
237 details.
238
Chris Kay925fda42021-05-25 10:42:56 +0100239- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters
240 (also known as group 1 counters). These are implementation-defined counters,
241 and as such require additional platform configuration. Default is 0.
242
Chris Kayf11909f2021-08-19 11:21:52 +0100243- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which
244 allows platforms with auxiliary counters to describe them via the
245 ``HW_CONFIG`` device tree blob. Default is 0.
246
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100247- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
248 are compiled out. For debug builds, this option defaults to 1, and calls to
249 ``assert()`` are left in place. For release builds, this option defaults to 0
250 and calls to ``assert()`` function are compiled out. This option can be set
251 independently of ``DEBUG``. It can also be used to hide any auxiliary code
252 that is only required for the assertion and does not fit in the assertion
253 itself.
254
Alexei Fedorovb8f26e92020-02-06 17:11:03 +0000255- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100256 dumps or not. It is supported in both AArch64 and AArch32. However, in
257 AArch32 the format of the frame records are not defined in the AAPCS and they
258 are defined by the implementation. This implementation of backtrace only
259 supports the format used by GCC when T32 interworking is disabled. For this
260 reason enabling this option in AArch32 will force the compiler to only
261 generate A32 code. This option is enabled by default only in AArch64 debug
262 builds, but this behaviour can be overridden in each platform's Makefile or
263 in the build command line.
264
Andre Przywara0b7f1b02023-03-21 13:53:19 +0000265- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit
266 extensions. This flag can take the values 0 to 2, to align with the
267 ``FEATURE_DETECTION`` mechanism. This is an optional architectural feature
268 available on v8.4 onwards. Some v8.2 implementations also implement an AMU
269 and this option can be used to enable this feature on those systems as well.
270 This flag can take the values 0 to 2, the default is 0.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000271
272- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1``
273 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6
274 onwards. This flag can take the values 0 to 2, to align with the
275 ``FEATURE_DETECTION`` mechanism. Default value is ``0``.
276
277- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2``
278 extension. It allows access to the SCXTNUM_EL2 (Software Context Number)
279 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an
280 optional feature available on Arm v8.0 onwards. This flag can take values
281 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism.
282 Default value is ``0``.
283
284- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent
285 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3.
286 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4
287 and upwards. This flag can take the values 0 to 2, to align with the
288 ``FEATURE_DETECTION`` mechanism. Default value is ``0``.
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000289
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000290- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000291 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer
292 Physical Offset register) during EL2 to EL3 context save/restore operations.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000293 Its a mandatory architectural feature and is enabled from v8.6 and upwards.
294 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
295 mechanism. Default value is ``0``.
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000296
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000297- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps)
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000298 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000299 Read Trap Register) during EL2 to EL3 context save/restore operations.
300 Its a mandatory architectural feature and is enabled from v8.6 and upwards.
301 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
302 mechanism. Default value is ``0``.
303
304- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to
305 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as
306 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a
307 mandatory architectural feature and is enabled from v8.7 and upwards. This
308 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
309 mechanism. Default value is ``0``.
310
Maksims Svecovsdf4ad842023-03-24 13:05:09 +0000311- ``ENABLE_FEAT_MTE_PERM``: Numeric value to enable support for
312 ``FEAT_MTE_PERM``, which introduces Allocation tag access permission to
313 memory region attributes. ``FEAT_MTE_PERM`` is a optional architectural
314 feature available from v8.9 and upwards. This flag can take the values 0 to
315 2, to align with the ``FEATURE_DETECTION`` mechanism. Default value is
316 ``0``.
317
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000318- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged
319 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a
320 permission fault for any privileged data access from EL1/EL2 to virtual
321 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a
322 mandatory architectural feature and is enabled from v8.1 and upwards. This
323 flag can take values 0 to 2, to align with the ``FEATURE_DETECTION``
324 mechanism. Default value is ``0``.
325
326- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension.
327 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This
328 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400329 mechanism. Default value is ``0``.
330
331- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP``
332 extension. This feature is only supported in AArch64 state. This flag can
333 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism.
334 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from
335 Armv8.5 onwards.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000336
Andre Przywara46880dc2022-11-17 16:42:09 +0000337- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB``
338 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and
339 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or
340 later CPUs. It is enabled from v8.5 and upwards and if needed can be
341 overidden from platforms explicitly.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000342
343- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2)
344 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4.
345 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION``
346 mechanism. Default is ``0``.
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000347
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +0100348- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed
349 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature
350 available on Arm v8.6. This flag can take values 0 to 2, to align with the
351 ``FEATURE_DETECTION`` mechanism. Default is ``0``.
352
353 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets
354 delayed by the amount of value in ``TWED_DELAY``.
355
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000356- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization
357 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register
358 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory
359 architectural feature and is enabled from v8.1 and upwards. It can take
360 values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism.
361 Default value is ``0``.
johpow01f91e59f2021-08-04 19:38:18 -0500362
Mark Brownc37eee72023-03-14 20:13:03 +0000363- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to
364 allow access to TCR2_EL2 (extended translation control) from EL2 as
365 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a
366 mandatory architectural feature and is enabled from v8.9 and upwards. This
367 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
368 mechanism. Default value is ``0``.
369
Mark Brown293a6612023-03-14 20:48:43 +0000370- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE
371 at EL2 and below, and context switch relevant registers. This flag
372 can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
373 mechanism. Default value is ``0``.
374
375- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE
376 at EL2 and below, and context switch relevant registers. This flag
377 can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
378 mechanism. Default value is ``0``.
379
380- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE
381 at EL2 and below, and context switch relevant registers. This flag
382 can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
383 mechanism. Default value is ``0``.
384
385- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE
386 at EL2 and below, and context switch relevant registers. This flag
387 can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
388 mechanism. Default value is ``0``.
389
Mark Brown326f2952023-03-14 21:33:04 +0000390- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to
391 allow use of Guarded Control Stack from EL2 as well as adding the GCS
392 registers to the EL2 context save/restore operations. This flag can take
393 the values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism.
394 Default value is ``0``.
395
Sandrine Bailleux11427302019-12-17 09:38:08 +0100396- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO)
zelalem-aweked5f45272019-11-12 16:20:17 -0600397 support in GCC for TF-A. This option is currently only supported for
398 AArch64. Default is 0.
399
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000400- ``ENABLE_MPAM_FOR_LOWER_ELS``: Numeric value to enable lower ELs to use MPAM
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100401 feature. MPAM is an optional Armv8.4 extension that enables various memory
402 system components and resources to define partitions; software running at
403 various ELs can assign themselves to desired partition to control their
404 performance aspects.
405
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000406 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION``
407 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to
408 access their own MPAM registers without trapping into EL3. This option
409 doesn't make use of partitioning in EL3, however. Platform initialisation
410 code should configure and use partitions in EL3 as required. This option
411 defaults to ``0``.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100412
Chris Kay03be39d2021-05-05 13:38:30 +0100413- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power
414 Mitigation Mechanism supported by certain Arm cores, which allows the SoC
415 firmware to detect and limit high activity events to assist in SoC processor
416 power domain dynamic power budgeting and limit the triggering of whole-rail
417 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``.
418
419- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which
420 allows platforms with cores supporting MPMM to describe them via the
421 ``HW_CONFIG`` device tree blob. Default is 0.
422
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100423- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
424 support within generic code in TF-A. This option is currently only supported
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600425 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and
426 in BL32 (SP_min) for AARCH32. Default is 0.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100427
428- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
429 Measurement Framework(PMF). Default is 0.
430
431- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
432 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
433 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
434 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
435 software.
436
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000437- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm
438 Management Extension. This flag can take the values 0 to 2, to align with
439 the ``FEATURE_DETECTION`` mechanism. Default value is 0. This is currently
440 an experimental feature.
Zelalem Aweke4d37db82021-07-11 18:33:20 -0500441
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100442- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
443 instrumentation which injects timestamp collection points into TF-A to
444 allow runtime performance to be measured. Currently, only PSCI is
445 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
446 as well. Default is 0.
447
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000448- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension
johpow019baade32021-07-08 14:14:00 -0500449 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share
450 registers so are enabled together. Using this option without
451 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure
Boyan Karatotev7f5dcc72023-03-08 16:29:26 +0000452 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a
453 superset of SVE. SME is an optional architectural feature for AArch64
johpow019baade32021-07-08 14:14:00 -0500454 and TF-A support is experimental. At this time, this build option cannot be
Manish Pandey247e5c32021-11-15 15:29:08 +0000455 used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000456 build with these options will fail. This flag can take the values 0 to 2, to
457 align with the ``FEATURE_DETECTION`` mechanism. Default is 0.
johpow019baade32021-07-08 14:14:00 -0500458
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +0000459- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension
460 version 2 (SME2) for the non-secure world only. SME2 is an optional
461 architectural feature for AArch64 and TF-A support is experimental.
462 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME
463 accesses will still be trapped. This flag can take the values 0 to 2, to
464 align with the ``FEATURE_DETECTION`` mechanism. Default is 0.
465
johpow019baade32021-07-08 14:14:00 -0500466- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix
Boyan Karatotev7f5dcc72023-03-08 16:29:26 +0000467 Extension for secure world. Used along with SVE and FPU/SIMD.
468 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this.
469 This is experimental. Default is 0.
johpow019baade32021-07-08 14:14:00 -0500470
Andre Przywaraf3e8cfc2022-11-17 16:42:09 +0000471- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100472 extensions. This is an optional architectural feature for AArch64.
Andre Przywaraf3e8cfc2022-11-17 16:42:09 +0000473 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
474 mechanism. The default is 2 but is automatically disabled when the target
475 architecture is AArch32.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100476
Jayanth Dodderi Chidanandd62c6812023-03-07 10:43:19 +0000477- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100478 (SVE) for the Non-secure world only. SVE is an optional architectural feature
479 for AArch64. Note that when SVE is enabled for the Non-secure world, access
Max Shvetsovc4502772021-03-22 11:59:37 +0000480 to SIMD and floating-point functionality from the Secure world is disabled by
481 default and controlled with ENABLE_SVE_FOR_SWD.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100482 This is to avoid corruption of the Non-secure world data in the Z-registers
483 which are aliased by the SIMD and FP registers. The build option is not
484 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
Boyan Karatotev7f5dcc72023-03-08 16:29:26 +0000485 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS``
486 enabled. This flag can take the values 0 to 2, to align with the
487 ``FEATURE_DETECTION`` mechanism. At this time, this build option cannot be
488 used on systems that have SPM_MM enabled. The default is 1.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100489
Max Shvetsovc4502772021-03-22 11:59:37 +0000490- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world.
491 SVE is an optional architectural feature for AArch64. Note that this option
Boyan Karatotev7f5dcc72023-03-08 16:29:26 +0000492 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is
493 automatically disabled when the target architecture is AArch32.
Max Shvetsovc4502772021-03-22 11:59:37 +0000494
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100495- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
496 checks in GCC. Allowed values are "all", "strong", "default" and "none". The
497 default value is set to "none". "strong" is the recommended stack protection
498 level if this feature is desired. "none" disables the stack protection. For
499 all values other than "none", the ``plat_get_stack_protector_canary()``
500 platform hook needs to be implemented. The value is passed as the last
501 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
502
Sumit Gargc0c369c2019-11-15 18:47:53 +0530503- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This
Manish Pandey34a305e2021-10-21 21:53:49 +0100504 flag depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530505
506- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload.
Manish Pandey34a305e2021-10-21 21:53:49 +0100507 This flag depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530508
509- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could
510 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends
Manish Pandey34a305e2021-10-21 21:53:49 +0100511 on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530512
513- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector
514 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT``
Manish Pandey34a305e2021-10-21 21:53:49 +0100515 build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530516
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100517- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
518 deprecated platform APIs, helper functions or drivers within Trusted
519 Firmware as error. It can take the value 1 (flag the use of deprecated
520 APIs as error) or 0. The default is 0.
521
522- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
523 targeted at EL3. When set ``0`` (default), no exceptions are expected or
Raghu Krishnamurthy669bf402022-07-25 14:44:33 -0700524 handled at EL3, and a panic will result. The exception to this rule is when
525 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions
526 occuring during normal world execution, are trapped to EL3. Any exception
527 trapped during secure world execution are trapped to the SPMC. This is
528 supported only for AArch64 builds.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100529
Javier Almansa Sobrino0d1f6b12020-09-18 16:47:07 +0100530- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when
531 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``.
532 Default value is 40 (LOG_LEVEL_INFO).
533
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100534- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault
535 injection from lower ELs, and this build option enables lower ELs to use
536 Error Records accessed via System Registers to inject faults. This is
537 applicable only to AArch64 builds.
538
539 This feature is intended for testing purposes only, and is advisable to keep
540 disabled for production images.
541
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000542- ``FEATURE_DETECTION``: Boolean option to enable the architectural features
543 detection mechanism. It detects whether the Architectural features enabled
544 through feature specific build flags are supported by the PE or not by
545 validating them either at boot phase or at runtime based on the value
546 possessed by the feature flag (0 to 2) and report error messages at an early
Boyan Karatoteva3e1b072023-06-09 13:22:16 +0100547 stage. This flag will also enable errata ordering checking for ``DEBUG``
548 builds.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000549
550 This prevents and benefits us from EL3 runtime exceptions during context save
551 and restore routines guarded by these build flags. Henceforth validating them
552 before their usage provides more control on the actions taken under them.
553
554 The mechanism permits the build flags to take values 0, 1 or 2 and
555 evaluates them accordingly.
556
557 Lets consider ``ENABLE_FEAT_HCX``, build flag for ``FEAT_HCX`` as an example:
558
559 ::
560
561 ENABLE_FEAT_HCX = 0: Feature disabled statically at compile time.
562 ENABLE_FEAT_HCX = 1: Feature Enabled and the flag is validated at boottime.
563 ENABLE_FEAT_HCX = 2: Feature Enabled and the flag is validated at runtime.
564
565 In the above example, if the feature build flag, ``ENABLE_FEAT_HCX`` set to
566 0, feature is disabled statically during compilation. If it is defined as 1,
567 feature is validated, wherein FEAT_HCX is detected at boot time. In case not
568 implemented by the PE, a hard panic is generated. Finally, if the flag is set
569 to 2, feature is validated at runtime.
570
571 Note that the entire implementation is divided into two phases, wherein as
572 as part of phase-1 we are supporting the values 0,1. Value 2 is currently not
573 supported and is planned to be handled explicilty in phase-2 implementation.
574
575 FEATURE_DETECTION macro is disabled by default, and is currently an
576 experimental procedure. Platforms can explicitly make use of this by
577 mechanism, by enabling it to validate whether they have set their build flags
578 properly at an early phase.
579
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100580- ``FIP_NAME``: This is an optional build option which specifies the FIP
581 filename for the ``fip`` target. Default is ``fip.bin``.
582
583- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
584 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
585
Sumit Gargc0c369c2019-11-15 18:47:53 +0530586- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values:
587
588 ::
589
590 0: Encryption is done with Secret Symmetric Key (SSK) which is common
591 for a class of devices.
592 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is
593 unique per device.
594
Manish Pandey34a305e2021-10-21 21:53:49 +0100595 This flag depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530596
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100597- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
598 tool to create certificates as per the Chain of Trust described in
599 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to
600 include the certificates in the FIP and FWU_FIP. Default value is '0'.
601
602 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
603 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
604 the corresponding certificates, and to include those certificates in the
605 FIP and FWU_FIP.
606
607 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
608 images will not include support for Trusted Board Boot. The FIP will still
609 include the corresponding certificates. This FIP can be used to verify the
610 Chain of Trust on the host machine through other mechanisms.
611
612 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
613 images will include support for Trusted Board Boot, but the FIP and FWU_FIP
614 will not include the corresponding certificates, causing a boot failure.
615
616- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
617 inherent support for specific EL3 type interrupts. Setting this build option
618 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -0500619 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and
620 :ref:`Interrupt Management Framework<Interrupt Management Framework>`.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100621 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
622 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
623 the Secure Payload interrupts needs to be synchronously handed over to Secure
624 EL1 for handling. The default value of this option is ``0``, which means the
625 Group 0 interrupts are assumed to be handled by Secure EL1.
626
Manish Pandey0e3379d2022-10-10 11:43:08 +0100627- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError
628 Interrupts, resulting from errors in NS world, will be always trapped in
629 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions
630 will be trapped in the current exception level (or in EL1 if the current
631 exception level is EL0).
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100632
633- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
634 software operations are required for CPUs to enter and exit coherency.
635 However, newer systems exist where CPUs' entry to and exit from coherency
636 is managed in hardware. Such systems require software to only initiate these
637 operations, and the rest is managed in hardware, minimizing active software
638 management. In such systems, this boolean option enables TF-A to carry out
639 build and run-time optimizations during boot and power management operations.
640 This option defaults to 0 and if it is enabled, then it implies
641 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
642
643 If this flag is disabled while the platform which TF-A is compiled for
644 includes cores that manage coherency in hardware, then a compilation error is
645 generated. This is based on the fact that a system cannot have, at the same
646 time, cores that manage coherency in hardware and cores that don't. In other
647 words, a platform cannot have, at the same time, cores that require
648 ``HW_ASSISTED_COHERENCY=1`` and cores that require
649 ``HW_ASSISTED_COHERENCY=0``.
650
651 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
652 translation library (xlat tables v2) must be used; version 1 of translation
653 library is not supported.
654
Varun Wadekar0a46eb12023-04-13 21:06:18 +0100655- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for
656 implementation defined system register accesses from lower ELs. Default
657 value is ``0``.
658
Louis Mayencourtc1c2bf72020-02-13 08:21:34 +0000659- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the
David Horstmannb2cc35f2021-01-21 12:29:59 +0000660 bottom, higher addresses at the top. This build flag can be set to '1' to
Louis Mayencourtc1c2bf72020-02-13 08:21:34 +0000661 invert this behavior. Lower addresses will be printed at the top and higher
662 addresses at the bottom.
663
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100664- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
665 used for generating the PKCS keys and subsequent signing of the certificate.
Lionel Debievefefeffb2022-11-14 11:03:42 +0100666 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular``
667 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1
668 RSA 1.5 algorithm which is not TBBR compliant and is retained only for
669 compatibility. The default value of this flag is ``rsa`` which is the TBBR
670 compliant PKCS#1 RSA 2.1 scheme.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100671
Gilad Ben-Yossefa6e53422019-09-15 13:29:29 +0300672- ``KEY_SIZE``: This build flag enables the user to select the key size for
673 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE``
674 depend on the chosen algorithm and the cryptographic module.
675
Lionel Debievefefeffb2022-11-14 11:03:42 +0100676 +---------------------------+------------------------------------+
677 | KEY_ALG | Possible key sizes |
678 +===========================+====================================+
679 | rsa | 1024 , 2048 (default), 3072, 4096* |
680 +---------------------------+------------------------------------+
681 | ecdsa | unavailable |
682 +---------------------------+------------------------------------+
683 | ecdsa-brainpool-regular | unavailable |
684 +---------------------------+------------------------------------+
685 | ecdsa-brainpool-twisted | unavailable |
686 +---------------------------+------------------------------------+
687
Gilad Ben-Yossefa6e53422019-09-15 13:29:29 +0300688
689 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1.
690 Only 3072 bits size is available with CryptoCell 712 SBROM release 2.
691
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100692- ``HASH_ALG``: This build flag enables the user to select the secure hash
693 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``.
694 The default value of this flag is ``sha256``.
695
696- ``LDFLAGS``: Extra user options appended to the linkers' command line in
697 addition to the one set by the build system.
698
699- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
700 output compiled into the build. This should be one of the following:
701
702 ::
703
704 0 (LOG_LEVEL_NONE)
705 10 (LOG_LEVEL_ERROR)
706 20 (LOG_LEVEL_NOTICE)
707 30 (LOG_LEVEL_WARNING)
708 40 (LOG_LEVEL_INFO)
709 50 (LOG_LEVEL_VERBOSE)
710
711 All log output up to and including the selected log level is compiled into
712 the build. The default value is 40 in debug builds and 20 in release builds.
713
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000714- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot
Manish V Badarkhe92de80a2021-12-16 10:41:47 +0000715 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to
716 provide trust that the code taking the measurements and recording them has
717 not been tampered with.
Sandrine Bailleux533d8b32021-06-10 11:18:04 +0200718
Manish Pandey34a305e2021-10-21 21:53:49 +0100719 This option defaults to 0.
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000720
Manish V Badarkhe8564f772022-02-14 18:31:16 +0000721- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust
722 for Measurement (DRTM). This feature has trust dependency on BL31 for taking
723 the measurements and recording them as per `PSA DRTM specification`_. For
724 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can
725 be used and for the platforms which use ``RESET_TO_BL31`` platform owners
Manish V Badarkhebbe1e422023-02-20 22:44:03 +0000726 should have mechanism to authenticate BL31. This is an experimental feature.
Manish V Badarkhe8564f772022-02-14 18:31:16 +0000727
728 This option defaults to 0.
729
Govindraj Raja81525652023-07-18 13:55:33 -0500730- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build
731 options to the compiler. An example usage:
732
733 .. code:: make
734
735 MARCH_DIRECTIVE := -march=armv8.5-a
736
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100737- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
738 specifies the file that contains the Non-Trusted World private key in PEM
739 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
740
741- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is
742 optional. It is only needed if the platform makefile specifies that it
743 is required in order to build the ``fwu_fip`` target.
744
745- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
746 contents upon world switch. It can take either 0 (don't save and restore) or
747 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
748 wants the timer registers to be saved and restored.
749
Manish V Badarkheb59efca2023-06-27 11:40:21 +0100750- ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in
751 tb_fw_config device tree. This flag is defined only when
752 ``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern optee_sp.
753
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100754- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
755 for the BL image. It can be either 0 (include) or 1 (remove). The default
756 value is 0.
757
758- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
759 the underlying hardware is not a full PL011 UART but a minimally compliant
760 generic UART, which is a subset of the PL011. The driver will not access
761 any register that is not part of the SBSA generic UART specification.
762 Default value is 0 (a full PL011 compliant UART is present).
763
764- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
765 must be subdirectory of any depth under ``plat/``, and must contain a
766 platform makefile named ``platform.mk``. For example, to build TF-A for the
767 Arm Juno board, select PLAT=juno.
768
769- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
770 instead of the normal boot flow. When defined, it must specify the entry
771 point address for the preloaded BL33 image. This option is incompatible with
772 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
773 over ``PRELOADED_BL33_BASE``.
774
775- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
776 vector address can be programmed or is fixed on the platform. It can take
777 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
778 programmable reset address, it is expected that a CPU will start executing
779 code directly at the right address, both on a cold and warm reset. In this
780 case, there is no need to identify the entrypoint on boot and the boot path
781 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
782 does not need to be implemented in this case.
783
784- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
785 possible for the PSCI power-state parameter: original and extended State-ID
786 formats. This flag if set to 1, configures the generic PSCI layer to use the
787 extended format. The default value of this flag is 0, which means by default
788 the original power-state format is used by the PSCI implementation. This flag
789 should be specified by the platform makefile and it governs the return value
790 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is
791 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be
792 set to 1 as well.
793
Wing Li1e9b68a2023-01-26 18:33:36 -0800794- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI
795 OS-initiated mode. This option defaults to 0.
796
Manish Pandeyd419e222023-02-13 12:39:17 +0000797- ``ENABLE_FEAT_RAS``: Numeric value to enable Armv8.2 RAS features. RAS features
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100798 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000799 or later CPUs. This flag can take the values 0 to 2, to align with the
800 ``FEATURE_DETECTION`` mechanism.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100801
Manish Pandeyd419e222023-02-13 12:39:17 +0000802- ``RAS_FFH_SUPPORT``: Support to enable Firmware first handling of RAS errors
803 originating from NS world. When ``RAS_FFH_SUPPORT`` is set to ``1``,
804 ``HANDLE_EA_EL3_FIRST_NS`` and ``ENABLE_FEAT_RAS`` must also be set to ``1``.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100805
806- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
807 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
808 entrypoint) or 1 (CPU reset to BL31 entrypoint).
809 The default value is 0.
810
811- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided
812 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector
813 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
814 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
815
816- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
Max Shvetsov06dba292019-12-06 11:50:12 +0000817 file that contains the ROT private key in PEM format and enforces public key
818 hash generation. If ``SAVE_KEYS=1``, this
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100819 file name will be used to save the key.
820
821- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
822 certificate generation tool to save the keys used to establish the Chain of
823 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
824
825- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional.
826 If a SCP_BL2 image is present then this option must be passed for the ``fip``
827 target.
828
829- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
830 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
831 this file name will be used to save the key.
832
833- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is
834 optional. It is only needed if the platform makefile specifies that it
835 is required in order to build the ``fwu_fip`` target.
836
837- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
838 Delegated Exception Interface to BL31 image. This defaults to ``0``.
839
840 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
841 set to ``1``.
842
843- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
844 isolated on separate memory pages. This is a trade-off between security and
845 memory usage. See "Isolating code and read-only data on separate memory
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100846 pages" section in :ref:`Firmware Design`. This flag is disabled by default
847 and affects all BL images.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100848
Samuel Holland31a14e12018-10-17 21:40:18 -0500849- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS
850 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be
851 allocated in RAM discontiguous from the loaded firmware image. When set, the
David Horstmannb2cc35f2021-01-21 12:29:59 +0000852 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and
Samuel Holland31a14e12018-10-17 21:40:18 -0500853 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS
854 sections are placed in RAM immediately following the loaded firmware image.
855
Jiafei Pan0824b452022-02-24 10:47:33 +0800856- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the
857 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM
858 discontiguous from loaded firmware images. When set, the platform need to
859 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This
860 flag is disabled by default and NOLOAD sections are placed in RAM immediately
861 following the loaded firmware image.
862
Jeremy Linton684a0792021-01-26 22:42:03 -0600863- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration
864 access requests via a standard SMCCC defined in `DEN0115`_. When combined with
865 UEFI+ACPI this can provide a certain amount of OS forward compatibility
866 with newer platforms that aren't ECAM compliant.
867
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100868- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
869 This build option is only valid if ``ARCH=aarch64``. The value should be
870 the path to the directory containing the SPD source, relative to
871 ``services/spd/``; the directory is expected to contain a makefile called
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100872 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in
873 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher
874 cannot be enabled when the ``SPM_MM`` option is enabled.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100875
876- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
877 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
878 execution in BL1 just before handing over to BL31. At this point, all
879 firmware images have been loaded in memory, and the MMU and caches are
880 turned off. Refer to the "Debugging options" section for more details.
881
Marc Bonniciabaac162021-12-01 18:00:40 +0000882- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM
883 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC
884 component runs at the EL3 exception level. The default value is ``0`` (
885 disabled). This configuration supports pre-Armv8.4 platforms (aka not
886 implementing the ``FEAT_SEL2`` extension). This is an experimental feature.
887
Jens Wiklanderba0ed3e2022-12-14 17:02:16 +0100888- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM
889 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to
890 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading
891 mechanism should be used.
892
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000893- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100894 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC
Marc Bonniciabaac162021-12-01 18:00:40 +0000895 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2``
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100896 extension. This is the default when enabling the SPM Dispatcher. When
897 disabled (0) it indicates the SPMC component runs at the S-EL1 execution
Marc Bonniciabaac162021-12-01 18:00:40 +0000898 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations
899 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2``
900 extension).
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100901
Paul Beesleyfe975b42019-09-16 11:29:03 +0000902- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100903 Partition Manager (SPM) implementation. The default value is ``0``
904 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is
905 enabled (``SPD=spmd``).
Paul Beesleyfe975b42019-09-16 11:29:03 +0000906
Manish Pandey3f90ad72020-01-14 11:52:05 +0000907- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100908 description of secure partitions. The build system will parse this file and
909 package all secure partition blobs into the FIP. This file is not
910 necessarily part of TF-A tree. Only available when ``SPD=spmd``.
Manish Pandey3f90ad72020-01-14 11:52:05 +0000911
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100912- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
913 secure interrupts (caught through the FIQ line). Platforms can enable
914 this directive if they need to handle such interruption. When enabled,
915 the FIQ are handled in monitor mode and non secure world is not allowed
916 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
917 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
918
Mark Brown64869972022-04-20 18:14:32 +0100919- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3.
920 Platforms can configure this if they need to lower the hardware
921 limit, for example due to asymmetric configuration or limitations of
922 software run at lower ELs. The default is the architectural maximum
923 of 2048 which should be suitable for most configurations, the
924 hardware will limit the effective VL to the maximum physically supported
925 VL.
926
Jayanth Dodderi Chidanand7c7faff2022-10-11 17:16:07 +0100927- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True
928 Random Number Generator Interface to BL31 image. This defaults to ``0``.
929
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100930- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
931 Boot feature. When set to '1', BL1 and BL2 images include support to load
932 and verify the certificates and images in a FIP, and BL1 includes support
933 for the Firmware Update. The default value is '0'. Generation and inclusion
934 of certificates in the FIP and FWU_FIP depends upon the value of the
935 ``GENERATE_COT`` option.
936
937 .. warning::
938 This option depends on ``CREATE_KEYS`` to be enabled. If the keys
939 already exist in disk, they will be overwritten without further notice.
940
941- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
942 specifies the file that contains the Trusted World private key in PEM
943 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
944
945- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
946 synchronous, (see "Initializing a BL32 Image" section in
947 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using
948 synchronous method) or 1 (BL32 is initialized using asynchronous method).
949 Default is 0.
950
951- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
952 routing model which routes non-secure interrupts asynchronously from TSP
953 to EL3 causing immediate preemption of TSP. The EL3 is responsible
954 for saving and restoring the TSP context in this routing model. The
955 default routing model (when the value is 0) is to route non-secure
956 interrupts to TSP allowing it to save its context and hand over
957 synchronously to EL3 via an SMC.
958
959 .. note::
960 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
961 must also be set to ``1``.
962
Manish V Badarkheb59efca2023-06-27 11:40:21 +0100963- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and
964 internal-trusted-storage) as SP in tb_fw_config device tree.
965
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +0100966- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of
967 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set
968 this delay. It can take values in the range (0-15). Default value is ``0``
969 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed.
970 Platforms need to explicitly update this value based on their requirements.
971
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100972- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM
973 linker. When the ``LINKER`` build variable points to the armlink linker,
974 this flag is enabled automatically. To enable support for armlink, platforms
975 will have to provide a scatter file for the BL image. Currently, Tegra
976 platforms use the armlink support to compile BL3-1 images.
977
978- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
979 memory region in the BL memory map or not (see "Use of Coherent memory in
980 TF-A" section in :ref:`Firmware Design`). It can take the value 1
981 (Coherent memory region is included) or 0 (Coherent memory region is
982 excluded). Default is 1.
983
Ambroise Vincent9660dc12019-07-12 13:47:03 +0100984- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature
985 exposing a virtual filesystem interface through BL31 as a SiP SMC function.
986 Default is 0.
987
Louis Mayencourt6b232d92020-02-28 16:57:30 +0000988- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the
989 firmware configuration framework. This will move the io_policies into a
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100990 configuration device tree, instead of static structure in the code base.
991
Manish V Badarkhead339892020-06-29 10:32:53 +0100992- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors
993 at runtime using fconf. If this flag is enabled, COT descriptors are
994 statically captured in tb_fw_config file in the form of device tree nodes
995 and properties. Currently, COT descriptors used by BL2 are moved to the
996 device tree and COT descriptors used by BL1 are retained in the code
Manish Pandey34a305e2021-10-21 21:53:49 +0100997 base statically.
Manish V Badarkhead339892020-06-29 10:32:53 +0100998
Balint Dobszayd0dbd5e2019-12-18 15:28:00 +0100999- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in
1000 runtime using firmware configuration framework. The platform specific SDEI
1001 shared and private events configuration is retrieved from device tree rather
Manish Pandey34a305e2021-10-21 21:53:49 +01001002 than static C structures at compile time. This is only supported if
1003 SDEI_SUPPORT build flag is enabled.
Louis Mayencourtbadcac82019-10-24 15:18:46 +01001004
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -05001005- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0
1006 and Group1 secure interrupts using the firmware configuration framework. The
1007 platform specific secure interrupt property descriptor is retrieved from
1008 device tree in runtime rather than depending on static C structure at compile
Manish Pandey34a305e2021-10-21 21:53:49 +01001009 time.
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -05001010
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001011- ``USE_ROMLIB``: This flag determines whether library at ROM will be used.
1012 This feature creates a library of functions to be placed in ROM and thus
1013 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default
1014 is 0.
1015
1016- ``V``: Verbose build. If assigned anything other than 0, the build commands
1017 are printed. Default is 0.
1018
1019- ``VERSION_STRING``: String used in the log output for each TF-A image.
1020 Defaults to a string formed by concatenating the version number, build type
1021 and build string.
1022
1023- ``W``: Warning level. Some compiler warning options of interest have been
1024 regrouped and put in the root Makefile. This flag can take the values 0 to 3,
1025 each level enabling more warning options. Default is 0.
1026
Boyan Karatoteve9e7e8a2022-12-07 10:26:48 +00001027 This option is closely related to the ``E`` option, which enables
1028 ``-Werror``.
1029
1030 - ``W=0`` (default)
1031
1032 Enables a wide assortment of warnings, most notably ``-Wall`` and
1033 ``-Wextra``, as well as various bad practices and things that are likely to
1034 result in errors. Includes some compiler specific flags. No warnings are
1035 expected at this level for any build.
1036
1037 - ``W=1``
1038
1039 Enables warnings we want the generic build to include but are too time
1040 consuming to fix at the moment. It re-enables warnings taken out for
1041 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected
1042 to eventually be merged into ``W=0``. Some warnings are expected on some
1043 builds, but new contributions should not introduce new ones.
1044
1045 - ``W=2`` (recommended)
1046
1047 Enables warnings we want the generic build to include but cannot be enabled
1048 due to external libraries. This level is expected to eventually be merged
1049 into ``W=0``. Lots of warnings are expected, primarily from external
1050 libraries like zlib and compiler-rt, but new controbutions should not
1051 introduce new ones.
1052
1053 - ``W=3``
1054
1055 Enables warnings that are informative but not necessary and generally too
1056 verbose and frequently ignored. A very large number of warnings are
1057 expected.
1058
1059 The exact set of warning flags depends on the compiler and TF-A warning
1060 level, however they are all succinctly set in the top-level Makefile. Please
1061 refer to the `GCC`_ or `Clang`_ documentation for more information on the
1062 individual flags.
1063
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001064- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
1065 the CPU after warm boot. This is applicable for platforms which do not
1066 require interconnect programming to enable cache coherency (eg: single
1067 cluster platforms). If this option is enabled, then warm boot path
1068 enables D-caches immediately after enabling MMU. This option defaults to 0.
1069
Manish V Badarkhe75c972a2020-03-22 05:06:38 +00001070- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory
1071 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The
1072 default value of this flag is ``no``. Note this option must be enabled only
1073 for ARM architecture greater than Armv8.5-A.
1074
Manish V Badarkhea59fa012020-07-31 08:38:49 +01001075- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT``
1076 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``.
1077 The default value of this flag is ``0``.
1078
1079 ``AT`` speculative errata workaround disables stage1 page table walk for
1080 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point
1081 produces either the correct result or failure without TLB allocation.
Manish V Badarkhe2801ed42020-04-28 04:53:32 +01001082
1083 This boolean option enables errata for all below CPUs.
1084
Manish V Badarkhea59fa012020-07-31 08:38:49 +01001085 +---------+--------------+-------------------------+
1086 | Errata | CPU | Workaround Define |
1087 +=========+==============+=========================+
1088 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` |
1089 +---------+--------------+-------------------------+
1090 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` |
1091 +---------+--------------+-------------------------+
1092 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` |
1093 +---------+--------------+-------------------------+
1094 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` |
1095 +---------+--------------+-------------------------+
1096 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` |
1097 +---------+--------------+-------------------------+
1098
1099 .. note::
1100 This option is enabled by build only if platform sets any of above defines
1101 mentioned in ’Workaround Define' column in the table.
1102 If this option is enabled for the EL3 software then EL2 software also must
1103 implement this workaround due to the behaviour of the errata mentioned
1104 in new SDEN document which will get published soon.
Manish V Badarkhe2801ed42020-04-28 04:53:32 +01001105
Manish Pandey7c6fcb42022-09-27 14:30:34 +01001106- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR
Varun Wadekar92234852020-06-12 10:11:28 -07001107 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs.
1108 This flag is disabled by default.
1109
Juan Pablo Conde52865522022-06-28 16:56:32 -04001110- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the
1111 host machine where a custom installation of OpenSSL is located, which is used
1112 to build the certificate generation, firmware encryption and FIP tools. If
1113 this option is not set, the default OS installation will be used.
Manish V Badarkhe3589b702020-07-29 10:58:44 +01001114
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -05001115- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for
1116 functions that wait for an arbitrary time length (udelay and mdelay). The
1117 default value is 0.
1118
Jayanth Dodderi Chidanand69316752022-05-09 12:33:03 +01001119- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record
1120 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an
1121 optional architectural feature for AArch64. This flag can take the values
1122 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0
1123 and it is automatically disabled when the target architecture is AArch32.
johpow0181865962022-01-28 17:06:20 -06001124
Jayanth Dodderi Chidananda793ccc2022-05-19 14:08:28 +01001125- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer
Manish V Badarkhe20df29c2021-07-02 09:10:56 +01001126 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented
1127 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural
Jayanth Dodderi Chidananda793ccc2022-05-19 14:08:28 +01001128 feature for AArch64. This flag can take the values 0 to 2, to align with the
1129 ``FEATURE_DETECTION`` mechanism. The default is 0 and it is automatically
1130 disabled when the target architecture is AArch32.
Manish V Badarkhe20df29c2021-07-02 09:10:56 +01001131
Andre Przywara44e33e02022-11-17 16:42:09 +00001132- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system
Manish V Badarkhef356f7e2021-06-29 11:44:20 +01001133 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented
1134 but unused). This feature is available if trace unit such as ETMv4.x, and
Andre Przywara44e33e02022-11-17 16:42:09 +00001135 ETE(extending ETM feature) is implemented. This flag can take the values
1136 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0.
Manish V Badarkhef356f7e2021-06-29 11:44:20 +01001137
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +00001138- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers
Manish V Badarkhe51a97112021-07-08 09:33:18 +01001139 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused),
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +00001140 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align
1141 with the ``FEATURE_DETECTION`` mechanism. This flag is disabled by default.
Manish V Badarkhe51a97112021-07-08 09:33:18 +01001142
Tamas Banc9ccc272022-01-18 16:20:47 +01001143- ``PLAT_RSS_NOT_SUPPORTED``: Boolean option to enable the usage of the PSA
1144 APIs on platforms that doesn't support RSS (providing Arm CCA HES
1145 functionalities). When enabled (``1``), a mocked version of the APIs are used.
1146 The default value is 0.
1147
Okash Khawaja037b56e2022-11-04 12:38:01 +00001148- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine
1149 ``plat_can_cmo`` which will return zero if cache management operations should
1150 be skipped and non-zero otherwise. By default, this option is disabled which
1151 means platform hook won't be checked and CMOs will always be performed when
1152 related functions are called.
1153
Sona Mathew6315c582023-03-15 09:40:36 -05001154- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management
1155 firmware interface for the BL31 image. By default its disabled (``0``).
1156
1157- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the
1158 errata mitigation for platforms with a non-arm interconnect using the errata
1159 ABI. By default its disabled (``0``).
1160
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +00001161GICv3 driver options
1162--------------------
1163
1164GICv3 driver files are included using directive:
1165
1166``include drivers/arm/gic/v3/gicv3.mk``
1167
1168The driver can be configured with the following options set in the platform
1169makefile:
1170
Andre Przywarae1cc1302020-03-25 15:50:38 +00001171- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3.
1172 Enabling this option will add runtime detection support for the
1173 GIC-600, so is safe to select even for a GIC500 implementation.
1174 This option defaults to 0.
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +00001175
Varun Wadekareea6dc12021-05-04 16:14:09 -07001176- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit
1177 for GIC-600 AE. Enabling this option will introduce support to initialize
1178 the FMU. Platforms should call the init function during boot to enable the
1179 FMU and its safety mechanisms. This option defaults to 0.
1180
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +00001181- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip
1182 functionality. This option defaults to 0
1183
1184- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation
1185 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore``
1186 functions. This is required for FVP platform which need to simulate GIC save
1187 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0.
1188
Alexei Fedorov19705932020-04-06 19:00:35 +01001189- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver.
1190 This option defaults to 0.
1191
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001192- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended
1193 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0.
1194
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001195Debugging options
1196-----------------
1197
1198To compile a debug version and make the build more verbose use
1199
1200.. code:: shell
1201
1202 make PLAT=<platform> DEBUG=1 V=1 all
1203
Daniel Boulbydf83a832022-05-03 16:46:16 +01001204AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools
1205(for example Arm-DS) might not support this and may need an older version of
1206DWARF symbols to be emitted by GCC. This can be achieved by using the
1207``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting
1208the version to 4 is recommended for Arm-DS.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001209
1210When debugging logic problems it might also be useful to disable all compiler
1211optimizations by using ``-O0``.
1212
1213.. warning::
1214 Using ``-O0`` could cause output images to be larger and base addresses
1215 might need to be recalculated (see the **Memory layout on Arm development
1216 platforms** section in the :ref:`Firmware Design`).
1217
1218Extra debug options can be passed to the build system by setting ``CFLAGS`` or
1219``LDFLAGS``:
1220
1221.. code:: shell
1222
1223 CFLAGS='-O0 -gdwarf-2' \
1224 make PLAT=<platform> DEBUG=1 V=1 all
1225
1226Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
1227ignored as the linker is called directly.
1228
1229It is also possible to introduce an infinite loop to help in debugging the
1230post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
1231``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common`
1232section. In this case, the developer may take control of the target using a
Daniel Boulbydf83a832022-05-03 16:46:16 +01001233debugger when indicated by the console output. When using Arm-DS, the following
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001234commands can be used:
1235
1236::
1237
1238 # Stop target execution
1239 interrupt
1240
1241 #
1242 # Prepare your debugging environment, e.g. set breakpoints
1243 #
1244
1245 # Jump over the debug loop
1246 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
1247
1248 # Resume execution
1249 continue
1250
Manish V Badarkhe5c101ae2021-03-16 11:14:19 +00001251Firmware update options
1252-----------------------
1253
1254- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used
1255 in defining the firmware update metadata structure. This flag is by default
1256 set to '2'.
1257
1258- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each
1259 firmware bank. Each firmware bank must have the same number of images as per
1260 the `PSA FW update specification`_.
1261 This flag is used in defining the firmware update metadata structure. This
1262 flag is by default set to '1'.
1263
Manish V Badarkheda87af12021-06-20 21:14:46 +01001264- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the
1265 `PSA FW update specification`_. The default value is 0, and this is an
1266 experimental feature.
1267 PSA firmware update implementation has some limitations, such as BL2 is
1268 not part of the protocol-updatable images, if BL2 needs to be updated, then
1269 it should be done through another platform-defined mechanism, and it assumes
1270 that the platform's hardware supports CRC32 instructions.
1271
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001272--------------
1273
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -06001274*Copyright (c) 2019-2023, Arm Limited. All rights reserved.*
Jeremy Linton684a0792021-01-26 22:42:03 -06001275
1276.. _DEN0115: https://developer.arm.com/docs/den0115/latest
Manish V Badarkhe5c101ae2021-03-16 11:14:19 +00001277.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/
Manish V Badarkhe8564f772022-02-14 18:31:16 +00001278.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a
Boyan Karatoteve9e7e8a2022-12-07 10:26:48 +00001279.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html
1280.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html