blob: 0001ffdde973f89eb48dbc36746d8023ee056de4 [file] [log] [blame]
Sughosh Ganu18f513d2018-05-16 17:22:35 +05301/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Sughosh Ganu18f513d2018-05-16 17:22:35 +05307#include <assert.h>
Sughosh Ganu18f513d2018-05-16 17:22:35 +05308#include <string.h>
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <bl31/interrupt_mgmt.h>
11#include <lib/el3_runtime/context_mgmt.h>
12#include <lib/extensions/ras.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000013#include <plat/arm/common/arm_spm_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <plat/common/platform.h>
15#include <services/mm_svc.h>
16#include <services/sdei.h>
17#include <services/spm_svc.h>
18
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000019#include <sgi_ras.h>
20
Sughosh Ganu18f513d2018-05-16 17:22:35 +053021static int sgi_ras_intr_handler(const struct err_record_info *err_rec,
22 int probe_data,
23 const struct err_handler_data *const data);
24struct efi_guid {
25 uint32_t data1;
26 uint16_t data2;
27 uint16_t data3;
28 uint8_t data4[8];
29};
30
31typedef struct mm_communicate_header {
32 struct efi_guid header_guid;
33 size_t message_len;
34 uint8_t data[8];
35} mm_communicate_header_t;
36
Sughosh Ganu70661cf2018-05-16 17:26:40 +053037struct sgi_ras_ev_map sgi575_ras_map[] = {
38
39 /* DMC620 error overflow interrupt*/
40 {SP_DMC_ERROR_OVERFLOW_EVENT_AARCH64, SGI_SDEI_DS_EVENT_1, 33},
41
42 /* DMC620 error ECC error interrupt*/
43 {SP_DMC_ERROR_ECC_EVENT_AARCH64, SGI_SDEI_DS_EVENT_0, 35},
44};
45
46#define SGI575_RAS_MAP_SIZE ARRAY_SIZE(sgi575_ras_map)
47
48struct err_record_info sgi_err_records[] = {
49 {
50 .handler = &sgi_ras_intr_handler,
51 },
52};
53
54struct ras_interrupt sgi_ras_interrupts[] = {
55 {
56 .intr_number = 33,
57 .err_record = &sgi_err_records[0],
58 },
59 {
60 .intr_number = 35,
61 .err_record = &sgi_err_records[0],
62 }
63};
64
65REGISTER_ERR_RECORD_INFO(sgi_err_records);
66REGISTER_RAS_INTERRUPTS(sgi_ras_interrupts);
67
68static struct sgi_ras_ev_map *plat_sgi_get_ras_ev_map(void)
69{
70 return sgi575_ras_map;
71}
72
73static int plat_sgi_get_ras_ev_map_size(void)
74{
75 return SGI575_RAS_MAP_SIZE;
76}
77
Sughosh Ganu18f513d2018-05-16 17:22:35 +053078/*
79 * Find event mapping for a given interrupt number: On success, returns pointer
80 * to the event mapping. On error, returns NULL.
81 */
82static struct sgi_ras_ev_map *find_ras_event_map_by_intr(uint32_t intr_num)
83{
84 struct sgi_ras_ev_map *map = plat_sgi_get_ras_ev_map();
85 int i;
86 int size = plat_sgi_get_ras_ev_map_size();
87
88 for (i = 0; i < size; i++) {
89 if (map->intr == intr_num)
90 return map;
91
92 map++;
93 }
94
95 return NULL;
96}
97
98static void sgi_ras_intr_configure(int intr)
99{
100 plat_ic_set_interrupt_type(intr, INTR_TYPE_EL3);
101 plat_ic_set_interrupt_priority(intr, PLAT_RAS_PRI);
102 plat_ic_clear_interrupt_pending(intr);
103 plat_ic_set_spi_routing(intr, INTR_ROUTING_MODE_ANY,
104 (u_register_t)read_mpidr_el1());
105 plat_ic_enable_interrupt(intr);
106}
107
108static int sgi_ras_intr_handler(const struct err_record_info *err_rec,
109 int probe_data,
110 const struct err_handler_data *const data)
111{
112 struct sgi_ras_ev_map *ras_map;
113 mm_communicate_header_t *header;
114 uint32_t intr;
115
116 cm_el1_sysregs_context_save(NON_SECURE);
117 intr = data->interrupt;
118
119 /*
120 * Find if this is a RAS interrupt. There must be an event against
121 * this interrupt
122 */
123 ras_map = find_ras_event_map_by_intr(intr);
124 assert(ras_map);
125
126 /*
127 * Populate the MM_COMMUNICATE payload to share the
128 * event info with StandaloneMM code. This allows us to use
129 * MM_COMMUNICATE as a common entry mechanism into S-EL0. The
130 * header data will be parsed in StandaloneMM to process the
131 * corresponding event.
132 *
133 * TBD - Currently, the buffer allocated by SPM for communication
134 * between EL3 and S-EL0 is being used(PLAT_SPM_BUF_BASE). But this
135 * should happen via a dynamic mem allocation, which should be
136 * managed by SPM -- the individual platforms then call the mem
137 * alloc api to get memory for the payload.
138 */
139 header = (void *) PLAT_SPM_BUF_BASE;
140 memset(header, 0, sizeof(*header));
141 memcpy(&header->data, &ras_map->ras_ev_num,
142 sizeof(ras_map->ras_ev_num));
143 header->message_len = 4;
144
145 spm_sp_call(MM_COMMUNICATE_AARCH64, (uint64_t)header, 0,
146 plat_my_core_pos());
147
148 /*
149 * Do an EOI of the RAS interuupt. This allows the
150 * sdei event to be dispatched at the SDEI event's
151 * priority.
152 */
153 plat_ic_end_of_interrupt(intr);
154
155 /* Dispatch the event to the SDEI client */
156 sdei_dispatch_event(ras_map->sdei_ev_num);
157
158 return 0;
159}
160
161int sgi_ras_intr_handler_setup(void)
162{
163 int i;
164 struct sgi_ras_ev_map *map = plat_sgi_get_ras_ev_map();
165 int size = plat_sgi_get_ras_ev_map_size();
166
167 for (i = 0; i < size; i++) {
168 sgi_ras_intr_configure(map->intr);
169 map++;
170 }
171
172 INFO("SGI: RAS Interrupt Handler successfully registered\n");
173
174 return 0;
175}