| Valentine Barshak | f218414 | 2018-10-30 02:06:17 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2017, Renesas Electronics Corporation |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #include <stdint.h> /* for uint32_t */ |
| Ambroise Vincent | ffbf32a | 2019-03-28 09:01:18 +0000 | [diff] [blame] | 9 | #include <lib/mmio.h> |
| Valentine Barshak | f218414 | 2018-10-30 02:06:17 +0300 | [diff] [blame] | 10 | #include "pfc_init_v3m.h" |
| 11 | #include "include/rcar_def.h" |
| 12 | #include "rcar_private.h" |
| 13 | |
| 14 | #define RST_MODEMR 0xE6160060 // Mode Monitor Register |
| 15 | |
| 16 | /* GPIO base address */ |
| 17 | #define GPIO_BASE (0xE6050000U) |
| 18 | |
| 19 | /* GPIO registers */ |
| 20 | #define GPIO_IOINTSEL0 (GPIO_BASE + 0x0000U) |
| 21 | #define GPIO_INOUTSEL0 (GPIO_BASE + 0x0004U) |
| 22 | #define GPIO_OUTDT0 (GPIO_BASE + 0x0008U) |
| 23 | #define GPIO_INDT0 (GPIO_BASE + 0x000CU) |
| 24 | #define GPIO_INTDT0 (GPIO_BASE + 0x0010U) |
| 25 | #define GPIO_INTCLR0 (GPIO_BASE + 0x0014U) |
| 26 | #define GPIO_INTMSK0 (GPIO_BASE + 0x0018U) |
| 27 | #define GPIO_MSKCLR0 (GPIO_BASE + 0x001CU) |
| 28 | #define GPIO_POSNEG0 (GPIO_BASE + 0x0020U) |
| 29 | #define GPIO_EDGLEVEL0 (GPIO_BASE + 0x0024U) |
| 30 | #define GPIO_FILONOFF0 (GPIO_BASE + 0x0028U) |
| 31 | #define GPIO_INTMSKS0 (GPIO_BASE + 0x0038U) |
| 32 | #define GPIO_MSKCLRS0 (GPIO_BASE + 0x003CU) |
| 33 | #define GPIO_OUTDTSEL0 (GPIO_BASE + 0x0040U) |
| 34 | #define GPIO_OUTDTH0 (GPIO_BASE + 0x0044U) |
| 35 | #define GPIO_OUTDTL0 (GPIO_BASE + 0x0048U) |
| 36 | #define GPIO_BOTHEDGE0 (GPIO_BASE + 0x004CU) |
| 37 | #define GPIO_IOINTSEL1 (GPIO_BASE + 0x1000U) |
| 38 | #define GPIO_INOUTSEL1 (GPIO_BASE + 0x1004U) |
| 39 | #define GPIO_OUTDT1 (GPIO_BASE + 0x1008U) |
| 40 | #define GPIO_INDT1 (GPIO_BASE + 0x100CU) |
| 41 | #define GPIO_INTDT1 (GPIO_BASE + 0x1010U) |
| 42 | #define GPIO_INTCLR1 (GPIO_BASE + 0x1014U) |
| 43 | #define GPIO_INTMSK1 (GPIO_BASE + 0x1018U) |
| 44 | #define GPIO_MSKCLR1 (GPIO_BASE + 0x101CU) |
| 45 | #define GPIO_POSNEG1 (GPIO_BASE + 0x1020U) |
| 46 | #define GPIO_EDGLEVEL1 (GPIO_BASE + 0x1024U) |
| 47 | #define GPIO_FILONOFF1 (GPIO_BASE + 0x1028U) |
| 48 | #define GPIO_INTMSKS1 (GPIO_BASE + 0x1038U) |
| 49 | #define GPIO_MSKCLRS1 (GPIO_BASE + 0x103CU) |
| 50 | #define GPIO_OUTDTSEL1 (GPIO_BASE + 0x1040U) |
| 51 | #define GPIO_OUTDTH1 (GPIO_BASE + 0x1044U) |
| 52 | #define GPIO_OUTDTL1 (GPIO_BASE + 0x1048U) |
| 53 | #define GPIO_BOTHEDGE1 (GPIO_BASE + 0x104CU) |
| 54 | #define GPIO_IOINTSEL2 (GPIO_BASE + 0x2000U) |
| 55 | #define GPIO_INOUTSEL2 (GPIO_BASE + 0x2004U) |
| 56 | #define GPIO_OUTDT2 (GPIO_BASE + 0x2008U) |
| 57 | #define GPIO_INDT2 (GPIO_BASE + 0x200CU) |
| 58 | #define GPIO_INTDT2 (GPIO_BASE + 0x2010U) |
| 59 | #define GPIO_INTCLR2 (GPIO_BASE + 0x2014U) |
| 60 | #define GPIO_INTMSK2 (GPIO_BASE + 0x2018U) |
| 61 | #define GPIO_MSKCLR2 (GPIO_BASE + 0x201CU) |
| 62 | #define GPIO_POSNEG2 (GPIO_BASE + 0x2020U) |
| 63 | #define GPIO_EDGLEVEL2 (GPIO_BASE + 0x2024U) |
| 64 | #define GPIO_FILONOFF2 (GPIO_BASE + 0x2028U) |
| 65 | #define GPIO_INTMSKS2 (GPIO_BASE + 0x2038U) |
| 66 | #define GPIO_MSKCLRS2 (GPIO_BASE + 0x203CU) |
| 67 | #define GPIO_OUTDTSEL2 (GPIO_BASE + 0x2040U) |
| 68 | #define GPIO_OUTDTH2 (GPIO_BASE + 0x2044U) |
| 69 | #define GPIO_OUTDTL2 (GPIO_BASE + 0x2048U) |
| 70 | #define GPIO_BOTHEDGE2 (GPIO_BASE + 0x204CU) |
| 71 | #define GPIO_IOINTSEL3 (GPIO_BASE + 0x3000U) |
| 72 | #define GPIO_INOUTSEL3 (GPIO_BASE + 0x3004U) |
| 73 | #define GPIO_OUTDT3 (GPIO_BASE + 0x3008U) |
| 74 | #define GPIO_INDT3 (GPIO_BASE + 0x300CU) |
| 75 | #define GPIO_INTDT3 (GPIO_BASE + 0x3010U) |
| 76 | #define GPIO_INTCLR3 (GPIO_BASE + 0x3014U) |
| 77 | #define GPIO_INTMSK3 (GPIO_BASE + 0x3018U) |
| 78 | #define GPIO_MSKCLR3 (GPIO_BASE + 0x301CU) |
| 79 | #define GPIO_POSNEG3 (GPIO_BASE + 0x3020U) |
| 80 | #define GPIO_EDGLEVEL3 (GPIO_BASE + 0x3024U) |
| 81 | #define GPIO_FILONOFF3 (GPIO_BASE + 0x3028U) |
| 82 | #define GPIO_INTMSKS3 (GPIO_BASE + 0x3038U) |
| 83 | #define GPIO_MSKCLRS3 (GPIO_BASE + 0x303CU) |
| 84 | #define GPIO_OUTDTSEL3 (GPIO_BASE + 0x3040U) |
| 85 | #define GPIO_OUTDTH3 (GPIO_BASE + 0x3044U) |
| 86 | #define GPIO_OUTDTL3 (GPIO_BASE + 0x3048U) |
| 87 | #define GPIO_BOTHEDGE3 (GPIO_BASE + 0x304CU) |
| 88 | #define GPIO_IOINTSEL4 (GPIO_BASE + 0x4000U) |
| 89 | #define GPIO_INOUTSEL4 (GPIO_BASE + 0x4004U) |
| 90 | #define GPIO_OUTDT4 (GPIO_BASE + 0x4008U) |
| 91 | #define GPIO_INDT4 (GPIO_BASE + 0x400CU) |
| 92 | #define GPIO_INTDT4 (GPIO_BASE + 0x4010U) |
| 93 | #define GPIO_INTCLR4 (GPIO_BASE + 0x4014U) |
| 94 | #define GPIO_INTMSK4 (GPIO_BASE + 0x4018U) |
| 95 | #define GPIO_MSKCLR4 (GPIO_BASE + 0x401CU) |
| 96 | #define GPIO_POSNEG4 (GPIO_BASE + 0x4020U) |
| 97 | #define GPIO_EDGLEVEL4 (GPIO_BASE + 0x4024U) |
| 98 | #define GPIO_FILONOFF4 (GPIO_BASE + 0x4028U) |
| 99 | #define GPIO_INTMSKS4 (GPIO_BASE + 0x4038U) |
| 100 | #define GPIO_MSKCLRS4 (GPIO_BASE + 0x403CU) |
| 101 | #define GPIO_OUTDTSEL4 (GPIO_BASE + 0x4040U) |
| 102 | #define GPIO_OUTDTH4 (GPIO_BASE + 0x4044U) |
| 103 | #define GPIO_OUTDTL4 (GPIO_BASE + 0x4048U) |
| 104 | #define GPIO_BOTHEDGE4 (GPIO_BASE + 0x404CU) |
| 105 | #define GPIO_IOINTSEL5 (GPIO_BASE + 0x5000U) |
| 106 | #define GPIO_INOUTSEL5 (GPIO_BASE + 0x5004U) |
| 107 | #define GPIO_OUTDT5 (GPIO_BASE + 0x5008U) |
| 108 | #define GPIO_INDT5 (GPIO_BASE + 0x500CU) |
| 109 | #define GPIO_INTDT5 (GPIO_BASE + 0x5010U) |
| 110 | #define GPIO_INTCLR5 (GPIO_BASE + 0x5014U) |
| 111 | #define GPIO_INTMSK5 (GPIO_BASE + 0x5018U) |
| 112 | #define GPIO_MSKCLR5 (GPIO_BASE + 0x501CU) |
| 113 | #define GPIO_POSNEG5 (GPIO_BASE + 0x5020U) |
| 114 | #define GPIO_EDGLEVEL5 (GPIO_BASE + 0x5024U) |
| 115 | #define GPIO_FILONOFF5 (GPIO_BASE + 0x5028U) |
| 116 | #define GPIO_INTMSKS5 (GPIO_BASE + 0x5038U) |
| 117 | #define GPIO_MSKCLRS5 (GPIO_BASE + 0x503CU) |
| 118 | #define GPIO_OUTDTSEL5 (GPIO_BASE + 0x5040U) |
| 119 | #define GPIO_OUTDTH5 (GPIO_BASE + 0x5044U) |
| 120 | #define GPIO_OUTDTL5 (GPIO_BASE + 0x5048U) |
| 121 | #define GPIO_BOTHEDGE5 (GPIO_BASE + 0x504CU) |
| 122 | |
| 123 | /* Pin functon base address */ |
| 124 | #define PFC_BASE (0xE6060000U) |
| 125 | |
| 126 | /* Pin functon registers */ |
| 127 | #define PFC_PMMR (PFC_BASE + 0x0000U) |
| 128 | #define PFC_GPSR0 (PFC_BASE + 0x0100U) |
| 129 | #define PFC_GPSR1 (PFC_BASE + 0x0104U) |
| 130 | #define PFC_GPSR2 (PFC_BASE + 0x0108U) |
| 131 | #define PFC_GPSR3 (PFC_BASE + 0x010CU) |
| 132 | #define PFC_GPSR4 (PFC_BASE + 0x0110U) |
| 133 | #define PFC_GPSR5 (PFC_BASE + 0x0114U) |
| 134 | #define PFC_IPSR0 (PFC_BASE + 0x0200U) |
| 135 | #define PFC_IPSR1 (PFC_BASE + 0x0204U) |
| 136 | #define PFC_IPSR2 (PFC_BASE + 0x0208U) |
| 137 | #define PFC_IPSR3 (PFC_BASE + 0x020CU) |
| 138 | #define PFC_IPSR4 (PFC_BASE + 0x0210U) |
| 139 | #define PFC_IPSR5 (PFC_BASE + 0x0214U) |
| 140 | #define PFC_IPSR6 (PFC_BASE + 0x0218U) |
| 141 | #define PFC_IPSR7 (PFC_BASE + 0x021CU) |
| 142 | #define PFC_IPSR8 (PFC_BASE + 0x0220U) |
| 143 | #define PFC_IOCTRL30 (PFC_BASE + 0x0380U) |
| 144 | #define PFC_IOCTRL31 (PFC_BASE + 0x0384U) |
| 145 | #define PFC_IOCTRL32 (PFC_BASE + 0x0388U) |
| 146 | #define PFC_IOCTRL40 (PFC_BASE + 0x03C0U) |
| 147 | #define PFC_PUEN0 (PFC_BASE + 0x0400U) |
| 148 | #define PFC_PUEN1 (PFC_BASE + 0x0404U) |
| 149 | #define PFC_PUEN2 (PFC_BASE + 0x0408U) |
| 150 | #define PFC_PUEN3 (PFC_BASE + 0x040CU) |
| 151 | #define PFC_PUD0 (PFC_BASE + 0x0440U) |
| 152 | #define PFC_PUD1 (PFC_BASE + 0x0444U) |
| 153 | #define PFC_PUD2 (PFC_BASE + 0x0448U) |
| 154 | #define PFC_PUD3 (PFC_BASE + 0x044CU) |
| 155 | #define PFC_MOD_SEL0 (PFC_BASE + 0x0500U) |
| 156 | |
| 157 | /* Pin functon bit */ |
| 158 | #define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U) |
| 159 | #define GPSR0_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U) |
| 160 | #define GPSR0_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U) |
| 161 | #define GPSR0_DU_DOTCLKOUT ((uint32_t)1U << 18U) |
| 162 | #define GPSR0_DU_DB7 ((uint32_t)1U << 17U) |
| 163 | #define GPSR0_DU_DB6 ((uint32_t)1U << 16U) |
| 164 | #define GPSR0_DU_DB5 ((uint32_t)1U << 15U) |
| 165 | #define GPSR0_DU_DB4 ((uint32_t)1U << 14U) |
| 166 | #define GPSR0_DU_DB3 ((uint32_t)1U << 13U) |
| 167 | #define GPSR0_DU_DB2 ((uint32_t)1U << 12U) |
| 168 | #define GPSR0_DU_DG7 ((uint32_t)1U << 11U) |
| 169 | #define GPSR0_DU_DG6 ((uint32_t)1U << 10U) |
| 170 | #define GPSR0_DU_DG5 ((uint32_t)1U << 9U) |
| 171 | #define GPSR0_DU_DG4 ((uint32_t)1U << 8U) |
| 172 | #define GPSR0_DU_DG3 ((uint32_t)1U << 7U) |
| 173 | #define GPSR0_DU_DG2 ((uint32_t)1U << 6U) |
| 174 | #define GPSR0_DU_DR7 ((uint32_t)1U << 5U) |
| 175 | #define GPSR0_DU_DR6 ((uint32_t)1U << 4U) |
| 176 | #define GPSR0_DU_DR5 ((uint32_t)1U << 3U) |
| 177 | #define GPSR0_DU_DR4 ((uint32_t)1U << 2U) |
| 178 | #define GPSR0_DU_DR3 ((uint32_t)1U << 1U) |
| 179 | #define GPSR0_DU_DR2 ((uint32_t)1U << 0U) |
| 180 | |
| 181 | #define GPSR1_DIGRF_CLKOUT ((uint32_t)1U << 27U) |
| 182 | #define GPSR1_DIGRF_CLKIN ((uint32_t)1U << 26U) |
| 183 | #define GPSR1_CANFD_CLK ((uint32_t)1U << 25U) |
| 184 | #define GPSR1_CANFD1_RX ((uint32_t)1U << 24U) |
| 185 | #define GPSR1_CANFD1_TX ((uint32_t)1U << 23U) |
| 186 | #define GPSR1_CANFD0_RX ((uint32_t)1U << 22U) |
| 187 | #define GPSR1_CANFD0_TX ((uint32_t)1U << 21U) |
| 188 | #define GPSR1_AVB0_AVTP_CAPTURE ((uint32_t)1U << 20U) |
| 189 | #define GPSR1_AVB0_AVTP_MATCH ((uint32_t)1U << 19U) |
| 190 | #define GPSR1_AVB0_LINK ((uint32_t)1U << 18U) |
| 191 | #define GPSR1_AVB0_PHY_INT ((uint32_t)1U << 17U) |
| 192 | #define GPSR1_AVB0_MAGIC ((uint32_t)1U << 16U) |
| 193 | #define GPSR1_AVB0_MDC ((uint32_t)1U << 15U) |
| 194 | #define GPSR1_AVB0_MDIO ((uint32_t)1U << 14U) |
| 195 | #define GPSR1_AVB0_TXCREFCLK ((uint32_t)1U << 13U) |
| 196 | #define GPSR1_AVB0_TD3 ((uint32_t)1U << 12U) |
| 197 | #define GPSR1_AVB0_TD2 ((uint32_t)1U << 11U) |
| 198 | #define GPSR1_AVB0_TD1 ((uint32_t)1U << 10U) |
| 199 | #define GPSR1_AVB0_TD0 ((uint32_t)1U << 9U) |
| 200 | #define GPSR1_AVB0_TXC ((uint32_t)1U << 8U) |
| 201 | #define GPSR1_AVB0_TX_CTL ((uint32_t)1U << 7U) |
| 202 | #define GPSR1_AVB0_RD3 ((uint32_t)1U << 6U) |
| 203 | #define GPSR1_AVB0_RD2 ((uint32_t)1U << 5U) |
| 204 | #define GPSR1_AVB0_RD1 ((uint32_t)1U << 4U) |
| 205 | #define GPSR1_AVB0_RD0 ((uint32_t)1U << 3U) |
| 206 | #define GPSR1_AVB0_RXC ((uint32_t)1U << 2U) |
| 207 | #define GPSR1_AVB0_RX_CTL ((uint32_t)1U << 1U) |
| 208 | #define GPSR1_IRQ0 ((uint32_t)1U << 0U) |
| 209 | |
| 210 | #define GPSR2_VI0_FIELD ((uint32_t)1U << 16U) |
| 211 | #define GPSR2_VI0_DATA11 ((uint32_t)1U << 15U) |
| 212 | #define GPSR2_VI0_DATA10 ((uint32_t)1U << 14U) |
| 213 | #define GPSR2_VI0_DATA9 ((uint32_t)1U << 13U) |
| 214 | #define GPSR2_VI0_DATA8 ((uint32_t)1U << 12U) |
| 215 | #define GPSR2_VI0_DATA7 ((uint32_t)1U << 11U) |
| 216 | #define GPSR2_VI0_DATA6 ((uint32_t)1U << 10U) |
| 217 | #define GPSR2_VI0_DATA5 ((uint32_t)1U << 9U) |
| 218 | #define GPSR2_VI0_DATA4 ((uint32_t)1U << 8U) |
| 219 | #define GPSR2_VI0_DATA3 ((uint32_t)1U << 7U) |
| 220 | #define GPSR2_VI0_DATA2 ((uint32_t)1U << 6U) |
| 221 | #define GPSR2_VI0_DATA1 ((uint32_t)1U << 5U) |
| 222 | #define GPSR2_VI0_DATA0 ((uint32_t)1U << 4U) |
| 223 | #define GPSR2_VI0_VSYNC_N ((uint32_t)1U << 3U) |
| 224 | #define GPSR2_VI0_HSYNC_N ((uint32_t)1U << 2U) |
| 225 | #define GPSR2_VI0_CLKENB ((uint32_t)1U << 1U) |
| 226 | #define GPSR2_VI0_CLK ((uint32_t)1U << 0U) |
| 227 | |
| 228 | #define GPSR3_VI1_FIELD ((uint32_t)1U << 16U) |
| 229 | #define GPSR3_VI1_DATA11 ((uint32_t)1U << 15U) |
| 230 | #define GPSR3_VI1_DATA10 ((uint32_t)1U << 14U) |
| 231 | #define GPSR3_VI1_DATA9 ((uint32_t)1U << 13U) |
| 232 | #define GPSR3_VI1_DATA8 ((uint32_t)1U << 12U) |
| 233 | #define GPSR3_VI1_DATA7 ((uint32_t)1U << 11U) |
| 234 | #define GPSR3_VI1_DATA6 ((uint32_t)1U << 10U) |
| 235 | #define GPSR3_VI1_DATA5 ((uint32_t)1U << 9U) |
| 236 | #define GPSR3_VI1_DATA4 ((uint32_t)1U << 8U) |
| 237 | #define GPSR3_VI1_DATA3 ((uint32_t)1U << 7U) |
| 238 | #define GPSR3_VI1_DATA2 ((uint32_t)1U << 6U) |
| 239 | #define GPSR3_VI1_DATA1 ((uint32_t)1U << 5U) |
| 240 | #define GPSR3_VI1_DATA0 ((uint32_t)1U << 4U) |
| 241 | #define GPSR3_VI1_VSYNC_N ((uint32_t)1U << 3U) |
| 242 | #define GPSR3_VI1_HSYNC_N ((uint32_t)1U << 2U) |
| 243 | #define GPSR3_VI1_CLKENB ((uint32_t)1U << 1U) |
| 244 | #define GPSR3_VI1_CLK ((uint32_t)1U << 0U) |
| 245 | |
| 246 | #define GPSR4_SDA2 ((uint32_t)1U << 5U) |
| 247 | #define GPSR4_SCL2 ((uint32_t)1U << 4U) |
| 248 | #define GPSR4_SDA1 ((uint32_t)1U << 3U) |
| 249 | #define GPSR4_SCL1 ((uint32_t)1U << 2U) |
| 250 | #define GPSR4_SDA0 ((uint32_t)1U << 1U) |
| 251 | #define GPSR4_SCL0 ((uint32_t)1U << 0U) |
| 252 | |
| 253 | #define GPSR5_RPC_INT_N ((uint32_t)1U << 14U) |
| 254 | #define GPSR5_RPC_WP_N ((uint32_t)1U << 13U) |
| 255 | #define GPSR5_RPC_RESET_N ((uint32_t)1U << 12U) |
| 256 | #define GPSR5_QSPI1_SSL ((uint32_t)1U << 11U) |
| 257 | #define GPSR5_QSPI1_IO3 ((uint32_t)1U << 10U) |
| 258 | #define GPSR5_QSPI1_IO2 ((uint32_t)1U << 9U) |
| 259 | #define GPSR5_QSPI1_MISO_IO1 ((uint32_t)1U << 8U) |
| 260 | #define GPSR5_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U) |
| 261 | #define GPSR5_QSPI1_SPCLK ((uint32_t)1U << 6U) |
| 262 | #define GPSR5_QSPI0_SSL ((uint32_t)1U << 5U) |
| 263 | #define GPSR5_QSPI0_IO3 ((uint32_t)1U << 4U) |
| 264 | #define GPSR5_QSPI0_IO2 ((uint32_t)1U << 3U) |
| 265 | #define GPSR5_QSPI0_MISO_IO1 ((uint32_t)1U << 2U) |
| 266 | #define GPSR5_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U) |
| 267 | #define GPSR5_QSPI0_SPCLK ((uint32_t)1U << 0U) |
| 268 | |
| 269 | #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) |
| 270 | #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) |
| 271 | #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) |
| 272 | #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) |
| 273 | #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) |
| 274 | #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) |
| 275 | #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) |
| 276 | #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) |
| 277 | |
| 278 | #define IOCTRL30_POC_VI0_DATA5 ((uint32_t)1U << 31U) |
| 279 | #define IOCTRL30_POC_VI0_DATA4 ((uint32_t)1U << 30U) |
| 280 | #define IOCTRL30_POC_VI0_DATA3 ((uint32_t)1U << 29U) |
| 281 | #define IOCTRL30_POC_VI0_DATA2 ((uint32_t)1U << 28U) |
| 282 | #define IOCTRL30_POC_VI0_DATA1 ((uint32_t)1U << 27U) |
| 283 | #define IOCTRL30_POC_VI0_DATA0 ((uint32_t)1U << 26U) |
| 284 | #define IOCTRL30_POC_VI0_VSYNC_N ((uint32_t)1U << 25U) |
| 285 | #define IOCTRL30_POC_VI0_HSYNC_N ((uint32_t)1U << 24U) |
| 286 | #define IOCTRL30_POC_VI0_CLKENB ((uint32_t)1U << 23U) |
| 287 | #define IOCTRL30_POC_VI0_CLK ((uint32_t)1U << 22U) |
| 288 | #define IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U) |
| 289 | #define IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U) |
| 290 | #define IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U) |
| 291 | #define IOCTRL30_POC_DU_DOTCLKOUT ((uint32_t)1U << 18U) |
| 292 | #define IOCTRL30_POC_DU_DB7 ((uint32_t)1U << 17U) |
| 293 | #define IOCTRL30_POC_DU_DB6 ((uint32_t)1U << 16U) |
| 294 | #define IOCTRL30_POC_DU_DB5 ((uint32_t)1U << 15U) |
| 295 | #define IOCTRL30_POC_DU_DB4 ((uint32_t)1U << 14U) |
| 296 | #define IOCTRL30_POC_DU_DB3 ((uint32_t)1U << 13U) |
| 297 | #define IOCTRL30_POC_DU_DB2 ((uint32_t)1U << 12U) |
| 298 | #define IOCTRL30_POC_DU_DG7 ((uint32_t)1U << 11U) |
| 299 | #define IOCTRL30_POC_DU_DG6 ((uint32_t)1U << 10U) |
| 300 | #define IOCTRL30_POC_DU_DG5 ((uint32_t)1U << 9U) |
| 301 | #define IOCTRL30_POC_DU_DG4 ((uint32_t)1U << 8U) |
| 302 | #define IOCTRL30_POC_DU_DG3 ((uint32_t)1U << 7U) |
| 303 | #define IOCTRL30_POC_DU_DG2 ((uint32_t)1U << 6U) |
| 304 | #define IOCTRL30_POC_DU_DR7 ((uint32_t)1U << 5U) |
| 305 | #define IOCTRL30_POC_DU_DR6 ((uint32_t)1U << 4U) |
| 306 | #define IOCTRL30_POC_DU_DR5 ((uint32_t)1U << 3U) |
| 307 | #define IOCTRL30_POC_DU_DR4 ((uint32_t)1U << 2U) |
| 308 | #define IOCTRL30_POC_DU_DR3 ((uint32_t)1U << 1U) |
| 309 | #define IOCTRL30_POC_DU_DR2 ((uint32_t)1U << 0U) |
| 310 | |
| 311 | #define IOCTRL31_POC_DUMMY_31 ((uint32_t)1U << 31U) |
| 312 | #define IOCTRL31_POC_DUMMY_30 ((uint32_t)1U << 30U) |
| 313 | #define IOCTRL31_POC_DUMMY_29 ((uint32_t)1U << 29U) |
| 314 | #define IOCTRL31_POC_DUMMY_28 ((uint32_t)1U << 28U) |
| 315 | #define IOCTRL31_POC_DUMMY_27 ((uint32_t)1U << 27U) |
| 316 | #define IOCTRL31_POC_DUMMY_26 ((uint32_t)1U << 26U) |
| 317 | #define IOCTRL31_POC_DUMMY_25 ((uint32_t)1U << 25U) |
| 318 | #define IOCTRL31_POC_DUMMY_24 ((uint32_t)1U << 24U) |
| 319 | #define IOCTRL31_POC_VI1_FIELD ((uint32_t)1U << 23U) |
| 320 | #define IOCTRL31_POC_VI1_DATA11 ((uint32_t)1U << 22U) |
| 321 | #define IOCTRL31_POC_VI1_DATA10 ((uint32_t)1U << 21U) |
| 322 | #define IOCTRL31_POC_VI1_DATA9 ((uint32_t)1U << 20U) |
| 323 | #define IOCTRL31_POC_VI1_DATA8 ((uint32_t)1U << 19U) |
| 324 | #define IOCTRL31_POC_VI1_DATA7 ((uint32_t)1U << 18U) |
| 325 | #define IOCTRL31_POC_VI1_DATA6 ((uint32_t)1U << 17U) |
| 326 | #define IOCTRL31_POC_VI1_DATA5 ((uint32_t)1U << 16U) |
| 327 | #define IOCTRL31_POC_VI1_DATA4 ((uint32_t)1U << 15U) |
| 328 | #define IOCTRL31_POC_VI1_DATA3 ((uint32_t)1U << 14U) |
| 329 | #define IOCTRL31_POC_VI1_DATA2 ((uint32_t)1U << 13U) |
| 330 | #define IOCTRL31_POC_VI1_DATA1 ((uint32_t)1U << 12U) |
| 331 | #define IOCTRL31_POC_VI1_DATA0 ((uint32_t)1U << 11U) |
| 332 | #define IOCTRL31_POC_VI1_VSYNC_N ((uint32_t)1U << 10U) |
| 333 | #define IOCTRL31_POC_VI1_HSYNC_N ((uint32_t)1U << 9U) |
| 334 | #define IOCTRL31_POC_VI1_CLKENB ((uint32_t)1U << 8U) |
| 335 | #define IOCTRL31_POC_VI1_CLK ((uint32_t)1U << 7U) |
| 336 | #define IOCTRL31_POC_VI0_FIELD ((uint32_t)1U << 6U) |
| 337 | #define IOCTRL31_POC_VI0_DATA11 ((uint32_t)1U << 5U) |
| 338 | #define IOCTRL31_POC_VI0_DATA10 ((uint32_t)1U << 4U) |
| 339 | #define IOCTRL31_POC_VI0_DATA9 ((uint32_t)1U << 3U) |
| 340 | #define IOCTRL31_POC_VI0_DATA8 ((uint32_t)1U << 2U) |
| 341 | #define IOCTRL31_POC_VI0_DATA7 ((uint32_t)1U << 1U) |
| 342 | #define IOCTRL31_POC_VI0_DATA6 ((uint32_t)1U << 0U) |
| 343 | #define IOCTRL32_POC2_VREF ((uint32_t)1U << 0U) |
| 344 | #define IOCTRL40_SD0TDSEL1 ((uint32_t)1U << 1U) |
| 345 | #define IOCTRL40_SD0TDSEL0 ((uint32_t)1U << 0U) |
| 346 | |
| 347 | #define PUEN0_PUEN_VI0_CLK ((uint32_t)1U << 31U) |
| 348 | #define PUEN0_PUEN_TDI ((uint32_t)1U << 30U) |
| 349 | #define PUEN0_PUEN_TMS ((uint32_t)1U << 29U) |
| 350 | #define PUEN0_PUEN_TCK ((uint32_t)1U << 28U) |
| 351 | #define PUEN0_PUEN_TRST_N ((uint32_t)1U << 27U) |
| 352 | #define PUEN0_PUEN_IRQ0 ((uint32_t)1U << 26U) |
| 353 | #define PUEN0_PUEN_FSCLKST_N ((uint32_t)1U << 25U) |
| 354 | #define PUEN0_PUEN_EXTALR ((uint32_t)1U << 24U) |
| 355 | #define PUEN0_PUEN_PRESETOUT_N ((uint32_t)1U << 23U) |
| 356 | #define PUEN0_PUEN_DU_DOTCLKIN ((uint32_t)1U << 22U) |
| 357 | #define PUEN0_PUEN_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U) |
| 358 | #define PUEN0_PUEN_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U) |
| 359 | #define PUEN0_PUEN_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U) |
| 360 | #define PUEN0_PUEN_DU_DOTCLKOUT ((uint32_t)1U << 18U) |
| 361 | #define PUEN0_PUEN_DU_DB7 ((uint32_t)1U << 17U) |
| 362 | #define PUEN0_PUEN_DU_DB6 ((uint32_t)1U << 16U) |
| 363 | #define PUEN0_PUEN_DU_DB5 ((uint32_t)1U << 15U) |
| 364 | #define PUEN0_PUEN_DU_DB4 ((uint32_t)1U << 14U) |
| 365 | #define PUEN0_PUEN_DU_DB3 ((uint32_t)1U << 13U) |
| 366 | #define PUEN0_PUEN_DU_DB2 ((uint32_t)1U << 12U) |
| 367 | #define PUEN0_PUEN_DU_DG7 ((uint32_t)1U << 11U) |
| 368 | #define PUEN0_PUEN_DU_DG6 ((uint32_t)1U << 10U) |
| 369 | #define PUEN0_PUEN_DU_DG5 ((uint32_t)1U << 9U) |
| 370 | #define PUEN0_PUEN_DU_DG4 ((uint32_t)1U << 8U) |
| 371 | #define PUEN0_PUEN_DU_DG3 ((uint32_t)1U << 7U) |
| 372 | #define PUEN0_PUEN_DU_DG2 ((uint32_t)1U << 6U) |
| 373 | #define PUEN0_PUEN_DU_DR7 ((uint32_t)1U << 5U) |
| 374 | #define PUEN0_PUEN_DU_DR6 ((uint32_t)1U << 4U) |
| 375 | #define PUEN0_PUEN_DU_DR5 ((uint32_t)1U << 3U) |
| 376 | #define PUEN0_PUEN_DU_DR4 ((uint32_t)1U << 2U) |
| 377 | #define PUEN0_PUEN_DU_DR3 ((uint32_t)1U << 1U) |
| 378 | #define PUEN0_PUEN_DU_DR2 ((uint32_t)1U << 0U) |
| 379 | |
| 380 | #define PUEN1_PUEN_VI1_DATA11 ((uint32_t)1U << 31U) |
| 381 | #define PUEN1_PUEN_VI1_DATA10 ((uint32_t)1U << 30U) |
| 382 | #define PUEN1_PUEN_VI1_DATA9 ((uint32_t)1U << 29U) |
| 383 | #define PUEN1_PUEN_VI1_DATA8 ((uint32_t)1U << 28U) |
| 384 | #define PUEN1_PUEN_VI1_DATA7 ((uint32_t)1U << 27U) |
| 385 | #define PUEN1_PUEN_VI1_DATA6 ((uint32_t)1U << 26U) |
| 386 | #define PUEN1_PUEN_VI1_DATA5 ((uint32_t)1U << 25U) |
| 387 | #define PUEN1_PUEN_VI1_DATA4 ((uint32_t)1U << 24U) |
| 388 | #define PUEN1_PUEN_VI1_DATA3 ((uint32_t)1U << 23U) |
| 389 | #define PUEN1_PUEN_VI1_DATA2 ((uint32_t)1U << 22U) |
| 390 | #define PUEN1_PUEN_VI1_DATA1 ((uint32_t)1U << 21U) |
| 391 | #define PUEN1_PUEN_VI1_DATA0 ((uint32_t)1U << 20U) |
| 392 | #define PUEN1_PUEN_VI1_VSYNC_N ((uint32_t)1U << 19U) |
| 393 | #define PUEN1_PUEN_VI1_HSYNC_N ((uint32_t)1U << 18U) |
| 394 | #define PUEN1_PUEN_VI1_CLKENB ((uint32_t)1U << 17U) |
| 395 | #define PUEN1_PUEN_VI1_CLK ((uint32_t)1U << 16U) |
| 396 | #define PUEN1_PUEN_VI0_FIELD ((uint32_t)1U << 15U) |
| 397 | #define PUEN1_PUEN_VI0_DATA11 ((uint32_t)1U << 14U) |
| 398 | #define PUEN1_PUEN_VI0_DATA10 ((uint32_t)1U << 13U) |
| 399 | #define PUEN1_PUEN_VI0_DATA9 ((uint32_t)1U << 12U) |
| 400 | #define PUEN1_PUEN_VI0_DATA8 ((uint32_t)1U << 11U) |
| 401 | #define PUEN1_PUEN_VI0_DATA7 ((uint32_t)1U << 10U) |
| 402 | #define PUEN1_PUEN_VI0_DATA6 ((uint32_t)1U << 9U) |
| 403 | #define PUEN1_PUEN_VI0_DATA5 ((uint32_t)1U << 8U) |
| 404 | #define PUEN1_PUEN_VI0_DATA4 ((uint32_t)1U << 7U) |
| 405 | #define PUEN1_PUEN_VI0_DATA3 ((uint32_t)1U << 6U) |
| 406 | #define PUEN1_PUEN_VI0_DATA2 ((uint32_t)1U << 5U) |
| 407 | #define PUEN1_PUEN_VI0_DATA1 ((uint32_t)1U << 4U) |
| 408 | #define PUEN1_PUEN_VI0_DATA0 ((uint32_t)1U << 3U) |
| 409 | #define PUEN1_PUEN_VI0_VSYNC_N ((uint32_t)1U << 2U) |
| 410 | #define PUEN1_PUEN_VI0_HSYNC_N ((uint32_t)1U << 1U) |
| 411 | #define PUEN1_PUEN_VI0_CLKENB ((uint32_t)1U << 0U) |
| 412 | |
| 413 | #define PUEN2_PUEN_CANFD_CLK ((uint32_t)1U << 31U) |
| 414 | #define PUEN2_PUEN_CANFD1_RX ((uint32_t)1U << 30U) |
| 415 | #define PUEN2_PUEN_CANFD1_TX ((uint32_t)1U << 29U) |
| 416 | #define PUEN2_PUEN_CANFD0_RX ((uint32_t)1U << 28U) |
| 417 | #define PUEN2_PUEN_CANFD0_TX ((uint32_t)1U << 27U) |
| 418 | #define PUEN2_PUEN_AVB0_AVTP_CAPTURE ((uint32_t)1U << 26U) |
| 419 | #define PUEN2_PUEN_AVB0_AVTP_MATCH ((uint32_t)1U << 25U) |
| 420 | #define PUEN2_PUEN_AVB0_LINK ((uint32_t)1U << 24U) |
| 421 | #define PUEN2_PUEN_AVB0_PHY_INT ((uint32_t)1U << 23U) |
| 422 | #define PUEN2_PUEN_AVB0_MAGIC ((uint32_t)1U << 22U) |
| 423 | #define PUEN2_PUEN_AVB0_MDC ((uint32_t)1U << 21U) |
| 424 | #define PUEN2_PUEN_AVB0_MDIO ((uint32_t)1U << 20U) |
| 425 | #define PUEN2_PUEN_AVB0_TXCREFCLK ((uint32_t)1U << 19U) |
| 426 | #define PUEN2_PUEN_AVB0_TD3 ((uint32_t)1U << 18U) |
| 427 | #define PUEN2_PUEN_AVB0_TD2 ((uint32_t)1U << 17U) |
| 428 | #define PUEN2_PUEN_AVB0_TD1 ((uint32_t)1U << 16U) |
| 429 | #define PUEN2_PUEN_AVB0_TD0 ((uint32_t)1U << 15U) |
| 430 | #define PUEN2_PUEN_AVB0_TXC ((uint32_t)1U << 14U) |
| 431 | #define PUEN2_PUEN_AVB0_TX_CTL ((uint32_t)1U << 13U) |
| 432 | #define PUEN2_PUEN_AVB0_RD3 ((uint32_t)1U << 12U) |
| 433 | #define PUEN2_PUEN_AVB0_RD2 ((uint32_t)1U << 11U) |
| 434 | #define PUEN2_PUEN_AVB0_RD1 ((uint32_t)1U << 10U) |
| 435 | #define PUEN2_PUEN_AVB0_RD0 ((uint32_t)1U << 9U) |
| 436 | #define PUEN2_PUEN_AVB0_RXC ((uint32_t)1U << 8U) |
| 437 | #define PUEN2_PUEN_AVB0_RX_CTL ((uint32_t)1U << 7U) |
| 438 | #define PUEN2_PUEN_SDA2 ((uint32_t)1U << 6U) |
| 439 | #define PUEN2_PUEN_SCL2 ((uint32_t)1U << 5U) |
| 440 | #define PUEN2_PUEN_SDA1 ((uint32_t)1U << 4U) |
| 441 | #define PUEN2_PUEN_SCL1 ((uint32_t)1U << 3U) |
| 442 | #define PUEN2_PUEN_SDA0 ((uint32_t)1U << 2U) |
| 443 | #define PUEN2_PUEN_SCL0 ((uint32_t)1U << 1U) |
| 444 | #define PUEN2_PUEN_VI1_FIELD ((uint32_t)1U << 0U) |
| 445 | |
| 446 | #define PUEN3_PUEN_DIGRF_CLKOUT ((uint32_t)1U << 16U) |
| 447 | #define PUEN3_PUEN_DIGRF_CLKIN ((uint32_t)1U << 15U) |
| 448 | #define PUEN3_PUEN_RPC_INT_N ((uint32_t)1U << 14U) |
| 449 | #define PUEN3_PUEN_RPC_WP_N ((uint32_t)1U << 13U) |
| 450 | #define PUEN3_PUEN_RPC_RESET_N ((uint32_t)1U << 12U) |
| 451 | #define PUEN3_PUEN_QSPI1_SSL ((uint32_t)1U << 11U) |
| 452 | #define PUEN3_PUEN_QSPI1_IO3 ((uint32_t)1U << 10U) |
| 453 | #define PUEN3_PUEN_QSPI1_IO2 ((uint32_t)1U << 9U) |
| 454 | #define PUEN3_PUEN_QSPI1_MISO_IO1 ((uint32_t)1U << 8U) |
| 455 | #define PUEN3_PUEN_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U) |
| 456 | #define PUEN3_PUEN_QSPI1_SPCLK ((uint32_t)1U << 6U) |
| 457 | #define PUEN3_PUEN_QSPI0_SSL ((uint32_t)1U << 5U) |
| 458 | #define PUEN3_PUEN_QSPI0_IO3 ((uint32_t)1U << 4U) |
| 459 | #define PUEN3_PUEN_QSPI0_IO2 ((uint32_t)1U << 3U) |
| 460 | #define PUEN3_PUEN_QSPI0_MISO_IO1 ((uint32_t)1U << 2U) |
| 461 | #define PUEN3_PUEN_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U) |
| 462 | #define PUEN3_PUEN_QSPI0_SPCLK ((uint32_t)1U << 0U) |
| 463 | |
| 464 | #define PUD0_PUD_VI0_CLK ((uint32_t)1U << 31U) |
| 465 | #define PUD0_PUD_IRQ0 ((uint32_t)1U << 26U) |
| 466 | #define PUD0_PUD_FSCLKST_N ((uint32_t)1U << 25U) |
| 467 | #define PUD0_PUD_PRESETOUT_N ((uint32_t)1U << 23U) |
| 468 | #define PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U) |
| 469 | #define PUD0_PUD_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U) |
| 470 | #define PUD0_PUD_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U) |
| 471 | #define PUD0_PUD_DU_DOTCLKOUT ((uint32_t)1U << 18U) |
| 472 | #define PUD0_PUD_DU_DB7 ((uint32_t)1U << 17U) |
| 473 | #define PUD0_PUD_DU_DB6 ((uint32_t)1U << 16U) |
| 474 | #define PUD0_PUD_DU_DB5 ((uint32_t)1U << 15U) |
| 475 | #define PUD0_PUD_DU_DB4 ((uint32_t)1U << 14U) |
| 476 | #define PUD0_PUD_DU_DB3 ((uint32_t)1U << 13U) |
| 477 | #define PUD0_PUD_DU_DB2 ((uint32_t)1U << 12U) |
| 478 | #define PUD0_PUD_DU_DG7 ((uint32_t)1U << 11U) |
| 479 | #define PUD0_PUD_DU_DG6 ((uint32_t)1U << 10U) |
| 480 | #define PUD0_PUD_DU_DG5 ((uint32_t)1U << 9U) |
| 481 | #define PUD0_PUD_DU_DG4 ((uint32_t)1U << 8U) |
| 482 | #define PUD0_PUD_DU_DG3 ((uint32_t)1U << 7U) |
| 483 | #define PUD0_PUD_DU_DG2 ((uint32_t)1U << 6U) |
| 484 | #define PUD0_PUD_DU_DR7 ((uint32_t)1U << 5U) |
| 485 | #define PUD0_PUD_DU_DR6 ((uint32_t)1U << 4U) |
| 486 | #define PUD0_PUD_DU_DR5 ((uint32_t)1U << 3U) |
| 487 | #define PUD0_PUD_DU_DR4 ((uint32_t)1U << 2U) |
| 488 | #define PUD0_PUD_DU_DR3 ((uint32_t)1U << 1U) |
| 489 | #define PUD0_PUD_DU_DR2 ((uint32_t)1U << 0U) |
| 490 | |
| 491 | #define PUD1_PUD_VI1_DATA11 ((uint32_t)1U << 31U) |
| 492 | #define PUD1_PUD_VI1_DATA10 ((uint32_t)1U << 30U) |
| 493 | #define PUD1_PUD_VI1_DATA9 ((uint32_t)1U << 29U) |
| 494 | #define PUD1_PUD_VI1_DATA8 ((uint32_t)1U << 28U) |
| 495 | #define PUD1_PUD_VI1_DATA7 ((uint32_t)1U << 27U) |
| 496 | #define PUD1_PUD_VI1_DATA6 ((uint32_t)1U << 26U) |
| 497 | #define PUD1_PUD_VI1_DATA5 ((uint32_t)1U << 25U) |
| 498 | #define PUD1_PUD_VI1_DATA4 ((uint32_t)1U << 24U) |
| 499 | #define PUD1_PUD_VI1_DATA3 ((uint32_t)1U << 23U) |
| 500 | #define PUD1_PUD_VI1_DATA2 ((uint32_t)1U << 22U) |
| 501 | #define PUD1_PUD_VI1_DATA1 ((uint32_t)1U << 21U) |
| 502 | #define PUD1_PUD_VI1_DATA0 ((uint32_t)1U << 20U) |
| 503 | #define PUD1_PUD_VI1_VSYNC_N ((uint32_t)1U << 19U) |
| 504 | #define PUD1_PUD_VI1_HSYNC_N ((uint32_t)1U << 18U) |
| 505 | #define PUD1_PUD_VI1_CLKENB ((uint32_t)1U << 17U) |
| 506 | #define PUD1_PUD_VI1_CLK ((uint32_t)1U << 16U) |
| 507 | #define PUD1_PUD_VI0_FIELD ((uint32_t)1U << 15U) |
| 508 | #define PUD1_PUD_VI0_DATA11 ((uint32_t)1U << 14U) |
| 509 | #define PUD1_PUD_VI0_DATA10 ((uint32_t)1U << 13U) |
| 510 | #define PUD1_PUD_VI0_DATA9 ((uint32_t)1U << 12U) |
| 511 | #define PUD1_PUD_VI0_DATA8 ((uint32_t)1U << 11U) |
| 512 | #define PUD1_PUD_VI0_DATA7 ((uint32_t)1U << 10U) |
| 513 | #define PUD1_PUD_VI0_DATA6 ((uint32_t)1U << 9U) |
| 514 | #define PUD1_PUD_VI0_DATA5 ((uint32_t)1U << 8U) |
| 515 | #define PUD1_PUD_VI0_DATA4 ((uint32_t)1U << 7U) |
| 516 | #define PUD1_PUD_VI0_DATA3 ((uint32_t)1U << 6U) |
| 517 | #define PUD1_PUD_VI0_DATA2 ((uint32_t)1U << 5U) |
| 518 | #define PUD1_PUD_VI0_DATA1 ((uint32_t)1U << 4U) |
| 519 | #define PUD1_PUD_VI0_DATA0 ((uint32_t)1U << 3U) |
| 520 | #define PUD1_PUD_VI0_VSYNC_N ((uint32_t)1U << 2U) |
| 521 | #define PUD1_PUD_VI0_HSYNC_N ((uint32_t)1U << 1U) |
| 522 | #define PUD1_PUD_VI0_CLKENB ((uint32_t)1U << 0U) |
| 523 | |
| 524 | #define PUD2_PUD_CANFD_CLK ((uint32_t)1U << 31U) |
| 525 | #define PUD2_PUD_CANFD1_RX ((uint32_t)1U << 30U) |
| 526 | #define PUD2_PUD_CANFD1_TX ((uint32_t)1U << 29U) |
| 527 | #define PUD2_PUD_CANFD0_RX ((uint32_t)1U << 28U) |
| 528 | #define PUD2_PUD_CANFD0_TX ((uint32_t)1U << 27U) |
| 529 | #define PUD2_PUD_AVB0_AVTP_CAPTURE ((uint32_t)1U << 26U) |
| 530 | #define PUD2_PUD_AVB0_AVTP_MATCH ((uint32_t)1U << 25U) |
| 531 | #define PUD2_PUD_AVB0_LINK ((uint32_t)1U << 24U) |
| 532 | #define PUD2_PUD_AVB0_PHY_INT ((uint32_t)1U << 23U) |
| 533 | #define PUD2_PUD_AVB0_MAGIC ((uint32_t)1U << 22U) |
| 534 | #define PUD2_PUD_AVB0_MDC ((uint32_t)1U << 21U) |
| 535 | #define PUD2_PUD_AVB0_MDIO ((uint32_t)1U << 20U) |
| 536 | #define PUD2_PUD_AVB0_TXCREFCLK ((uint32_t)1U << 19U) |
| 537 | #define PUD2_PUD_AVB0_TD3 ((uint32_t)1U << 18U) |
| 538 | #define PUD2_PUD_AVB0_TD2 ((uint32_t)1U << 17U) |
| 539 | #define PUD2_PUD_AVB0_TD1 ((uint32_t)1U << 16U) |
| 540 | #define PUD2_PUD_AVB0_TD0 ((uint32_t)1U << 15U) |
| 541 | #define PUD2_PUD_AVB0_TXC ((uint32_t)1U << 14U) |
| 542 | #define PUD2_PUD_AVB0_TX_CTL ((uint32_t)1U << 13U) |
| 543 | #define PUD2_PUD_AVB0_RD3 ((uint32_t)1U << 12U) |
| 544 | #define PUD2_PUD_AVB0_RD2 ((uint32_t)1U << 11U) |
| 545 | #define PUD2_PUD_AVB0_RD1 ((uint32_t)1U << 10U) |
| 546 | #define PUD2_PUD_AVB0_RD0 ((uint32_t)1U << 9U) |
| 547 | #define PUD2_PUD_AVB0_RXC ((uint32_t)1U << 8U) |
| 548 | #define PUD2_PUD_AVB0_RX_CTL ((uint32_t)1U << 7U) |
| 549 | #define PUD2_PUD_SDA2 ((uint32_t)1U << 6U) |
| 550 | #define PUD2_PUD_SCL2 ((uint32_t)1U << 5U) |
| 551 | #define PUD2_PUD_SDA1 ((uint32_t)1U << 4U) |
| 552 | #define PUD2_PUD_SCL1 ((uint32_t)1U << 3U) |
| 553 | #define PUD2_PUD_SDA0 ((uint32_t)1U << 2U) |
| 554 | #define PUD2_PUD_SCL0 ((uint32_t)1U << 1U) |
| 555 | #define PUD2_PUD_VI1_FIELD ((uint32_t)1U << 0U) |
| 556 | |
| 557 | #define PUD3_PUD_DIGRF_CLKOUT ((uint32_t)1U << 16U) |
| 558 | #define PUD3_PUD_DIGRF_CLKIN ((uint32_t)1U << 15U) |
| 559 | #define PUD3_PUD_RPC_INT_N ((uint32_t)1U << 14U) |
| 560 | #define PUD3_PUD_RPC_WP_N ((uint32_t)1U << 13U) |
| 561 | #define PUD3_PUD_RPC_RESET_N ((uint32_t)1U << 12U) |
| 562 | #define PUD3_PUD_QSPI1_SSL ((uint32_t)1U << 11U) |
| 563 | #define PUD3_PUD_QSPI1_IO3 ((uint32_t)1U << 10U) |
| 564 | #define PUD3_PUD_QSPI1_IO2 ((uint32_t)1U << 9U) |
| 565 | #define PUD3_PUD_QSPI1_MISO_IO1 ((uint32_t)1U << 8U) |
| 566 | #define PUD3_PUD_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U) |
| 567 | #define PUD3_PUD_QSPI1_SPCLK ((uint32_t)1U << 6U) |
| 568 | #define PUD3_PUD_QSPI0_SSL ((uint32_t)1U << 5U) |
| 569 | #define PUD3_PUD_QSPI0_IO3 ((uint32_t)1U << 4U) |
| 570 | #define PUD3_PUD_QSPI0_IO2 ((uint32_t)1U << 3U) |
| 571 | #define PUD3_PUD_QSPI0_MISO_IO1 ((uint32_t)1U << 2U) |
| 572 | #define PUD3_PUD_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U) |
| 573 | #define PUD3_PUD_QSPI0_SPCLK ((uint32_t)1U << 0U) |
| 574 | |
| 575 | #define MOD_SEL0_sel_hscif0 ((uint32_t)1U << 10U) |
| 576 | #define MOD_SEL0_sel_scif1 ((uint32_t)1U << 9U) |
| 577 | #define MOD_SEL0_sel_canfd0 ((uint32_t)1U << 8U) |
| 578 | #define MOD_SEL0_sel_pwm4 ((uint32_t)1U << 7U) |
| 579 | #define MOD_SEL0_sel_pwm3 ((uint32_t)1U << 6U) |
| 580 | #define MOD_SEL0_sel_pwm2 ((uint32_t)1U << 5U) |
| 581 | #define MOD_SEL0_sel_pwm1 ((uint32_t)1U << 4U) |
| 582 | #define MOD_SEL0_sel_pwm0 ((uint32_t)1U << 3U) |
| 583 | #define MOD_SEL0_sel_rfso ((uint32_t)1U << 2U) |
| 584 | #define MOD_SEL0_sel_rsp ((uint32_t)1U << 1U) |
| 585 | #define MOD_SEL0_sel_tmu ((uint32_t)1U << 0U) |
| 586 | |
| 587 | /* SCIF3 Registers for Dummy write */ |
| 588 | #define SCIF3_BASE (0xE6C50000U) |
| 589 | #define SCIF3_SCFCR (SCIF3_BASE + 0x0018U) |
| 590 | #define SCIF3_SCFDR (SCIF3_BASE + 0x001CU) |
| 591 | #define SCFCR_DATA (0x0000U) |
| 592 | |
| 593 | /* Realtime module stop control */ |
| 594 | #define CPG_BASE (0xE6150000U) |
| 595 | #define CPG_MSTPSR0 (CPG_BASE + 0x0030U) |
| 596 | #define CPG_RMSTPCR0 (CPG_BASE + 0x0110U) |
| 597 | #define RMSTPCR0_RTDMAC (0x00200000U) |
| 598 | |
| 599 | /* RT-DMAC Registers */ |
| 600 | #define RTDMAC_CH (0U) /* choose 0 to 15 */ |
| 601 | |
| 602 | #define RTDMAC_BASE (0xFFC10000U) |
| 603 | #define RTDMAC_RDMOR (RTDMAC_BASE + 0x0060U) |
| 604 | #define RTDMAC_RDMCHCLR (RTDMAC_BASE + 0x0080U) |
| 605 | #define RTDMAC_RDMSAR(x) (RTDMAC_BASE + 0x8000U + (0x80U * (x))) |
| 606 | #define RTDMAC_RDMDAR(x) (RTDMAC_BASE + 0x8004U + (0x80U * (x))) |
| 607 | #define RTDMAC_RDMTCR(x) (RTDMAC_BASE + 0x8008U + (0x80U * (x))) |
| 608 | #define RTDMAC_RDMCHCR(x) (RTDMAC_BASE + 0x800CU + (0x80U * (x))) |
| 609 | #define RTDMAC_RDMCHCRB(x) (RTDMAC_BASE + 0x801CU + (0x80U * (x))) |
| 610 | #define RTDMAC_RDMDPBASE(x) (RTDMAC_BASE + 0x8050U + (0x80U * (x))) |
| 611 | #define RTDMAC_DESC_BASE (RTDMAC_BASE + 0xA000U) |
| 612 | #define RTDMAC_DESC_RDMSAR (RTDMAC_DESC_BASE + 0x0000U) |
| 613 | #define RTDMAC_DESC_RDMDAR (RTDMAC_DESC_BASE + 0x0004U) |
| 614 | #define RTDMAC_DESC_RDMTCR (RTDMAC_DESC_BASE + 0x0008U) |
| 615 | |
| 616 | #define RDMOR_DME (0x0001U) /* DMA Master Enable */ |
| 617 | #define RDMCHCR_DPM_INFINITE (0x30000000U) /* Infinite repeat mode */ |
| 618 | #define RDMCHCR_RPT_TCR (0x02000000U) /* enable to update TCR */ |
| 619 | #define RDMCHCR_TS_2 (0x00000008U) /* Word(2byte) units transfer */ |
| 620 | #define RDMCHCR_RS_AUTO (0x00000400U) /* Auto request */ |
| 621 | #define RDMCHCR_DE (0x00000001U) /* DMA Enable */ |
| 622 | #define RDMCHCRB_DRST (0x00008000U) /* Descriptor reset */ |
| 623 | #define RDMCHCRB_SLM_256 (0x00000080U) /* once in 256 clock cycle */ |
| 624 | #define RDMDPBASE_SEL_EXT (0x00000001U) /* External memory use */ |
| 625 | |
| 626 | static void pfc_reg_write(uint32_t addr, uint32_t data); |
| 627 | static void StartRtDma0_Descriptor(void); |
| 628 | |
| 629 | static void pfc_reg_write(uint32_t addr, uint32_t data) |
| 630 | { |
| 631 | mmio_write_32(PFC_PMMR, ~data); |
| 632 | mmio_write_32((uintptr_t)addr, data); |
| 633 | } |
| 634 | |
| 635 | static void StartRtDma0_Descriptor(void) |
| 636 | { |
| 637 | uint32_t reg; |
| 638 | |
| 639 | /* Module stop clear */ |
| 640 | while((mmio_read_32(CPG_MSTPSR0) & RMSTPCR0_RTDMAC) != 0U) { |
| 641 | reg = mmio_read_32(CPG_RMSTPCR0); |
| 642 | reg &= ~RMSTPCR0_RTDMAC; |
| 643 | cpg_write(CPG_RMSTPCR0, reg); |
| 644 | } |
| 645 | |
| 646 | /* Initialize ch0, Reset Descriptor */ |
| 647 | mmio_write_32(RTDMAC_RDMCHCLR, ((uint32_t)1U << RTDMAC_CH)); |
| 648 | mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_DRST); |
| 649 | |
| 650 | /* Enable DMA */ |
| 651 | mmio_write_16(RTDMAC_RDMOR, RDMOR_DME); |
| 652 | |
| 653 | /* Set first transfer */ |
| 654 | mmio_write_32(RTDMAC_RDMSAR(RTDMAC_CH), RCAR_PRR); |
| 655 | mmio_write_32(RTDMAC_RDMDAR(RTDMAC_CH), SCIF3_SCFDR); |
| 656 | mmio_write_32(RTDMAC_RDMTCR(RTDMAC_CH), 0x00000001U); |
| 657 | |
| 658 | /* Set descriptor */ |
| 659 | mmio_write_32(RTDMAC_DESC_RDMSAR, 0x00000000U); |
| 660 | mmio_write_32(RTDMAC_DESC_RDMDAR, 0x00000000U); |
| 661 | mmio_write_32(RTDMAC_DESC_RDMTCR, 0x00200000U); |
| 662 | mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_SLM_256); |
| 663 | mmio_write_32(RTDMAC_RDMDPBASE(RTDMAC_CH), RTDMAC_DESC_BASE |
| 664 | | RDMDPBASE_SEL_EXT); |
| 665 | |
| 666 | /* Set transfer parameter, Start transfer */ |
| 667 | mmio_write_32(RTDMAC_RDMCHCR(RTDMAC_CH), RDMCHCR_DPM_INFINITE |
| 668 | | RDMCHCR_RPT_TCR |
| 669 | | RDMCHCR_TS_2 |
| 670 | | RDMCHCR_RS_AUTO |
| 671 | | RDMCHCR_DE); |
| 672 | } |
| 673 | |
| 674 | void pfc_init_v3m(void) |
| 675 | { |
| 676 | /* Work around for PFC eratta */ |
| 677 | StartRtDma0_Descriptor(); |
| 678 | |
| 679 | // pin function |
| 680 | // md[4:1]!=0000 |
| 681 | /* initialize GPIO/perihperal function select */ |
| 682 | |
| 683 | pfc_reg_write(PFC_GPSR0, 0x00000000); |
| 684 | |
| 685 | pfc_reg_write(PFC_GPSR1, GPSR1_CANFD_CLK); |
| 686 | |
| 687 | pfc_reg_write(PFC_GPSR2, 0x00000000); |
| 688 | |
| 689 | pfc_reg_write(PFC_GPSR3, 0x00000000); |
| 690 | |
| 691 | pfc_reg_write(PFC_GPSR4, GPSR4_SDA2 |
| 692 | | GPSR4_SCL2); |
| 693 | |
| 694 | pfc_reg_write(PFC_GPSR5, GPSR5_QSPI1_SSL |
| 695 | | GPSR5_QSPI1_IO3 |
| 696 | | GPSR5_QSPI1_IO2 |
| 697 | | GPSR5_QSPI1_MISO_IO1 |
| 698 | | GPSR5_QSPI1_MOSI_IO0 |
| 699 | | GPSR5_QSPI1_SPCLK |
| 700 | | GPSR5_QSPI0_SSL |
| 701 | | GPSR5_QSPI0_IO3 |
| 702 | | GPSR5_QSPI0_IO2 |
| 703 | | GPSR5_QSPI0_MISO_IO1 |
| 704 | | GPSR5_QSPI0_MOSI_IO0 |
| 705 | | GPSR5_QSPI0_SPCLK); |
| 706 | |
| 707 | |
| 708 | /* initialize peripheral function select */ |
| 709 | pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0) |
| 710 | | IPSR_24_FUNC(0) |
| 711 | | IPSR_20_FUNC(0) |
| 712 | | IPSR_16_FUNC(0) |
| 713 | | IPSR_12_FUNC(0) |
| 714 | | IPSR_8_FUNC(0) |
| 715 | | IPSR_4_FUNC(0) |
| 716 | | IPSR_0_FUNC(0)); |
| 717 | |
| 718 | pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0) |
| 719 | | IPSR_24_FUNC(0) |
| 720 | | IPSR_20_FUNC(0) |
| 721 | | IPSR_16_FUNC(0) |
| 722 | | IPSR_12_FUNC(0) |
| 723 | | IPSR_8_FUNC(0) |
| 724 | | IPSR_4_FUNC(0) |
| 725 | | IPSR_0_FUNC(0)); |
| 726 | |
| 727 | pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0) |
| 728 | | IPSR_24_FUNC(0) |
| 729 | | IPSR_20_FUNC(0) |
| 730 | | IPSR_16_FUNC(0) |
| 731 | | IPSR_12_FUNC(0) |
| 732 | | IPSR_8_FUNC(0) |
| 733 | | IPSR_4_FUNC(0) |
| 734 | | IPSR_0_FUNC(0)); |
| 735 | |
| 736 | pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(0) |
| 737 | | IPSR_24_FUNC(0) |
| 738 | | IPSR_20_FUNC(0) |
| 739 | | IPSR_16_FUNC(0) |
| 740 | | IPSR_12_FUNC(0) |
| 741 | | IPSR_8_FUNC(0) |
| 742 | | IPSR_4_FUNC(0) |
| 743 | | IPSR_0_FUNC(0)); |
| 744 | |
| 745 | pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0) |
| 746 | | IPSR_24_FUNC(0) |
| 747 | | IPSR_20_FUNC(0) |
| 748 | | IPSR_16_FUNC(0) |
| 749 | | IPSR_12_FUNC(0) |
| 750 | | IPSR_8_FUNC(0) |
| 751 | | IPSR_4_FUNC(0) |
| 752 | | IPSR_0_FUNC(0)); |
| 753 | |
| 754 | pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0) |
| 755 | | IPSR_24_FUNC(0) |
| 756 | | IPSR_20_FUNC(0) |
| 757 | | IPSR_16_FUNC(0) |
| 758 | | IPSR_12_FUNC(0) |
| 759 | | IPSR_8_FUNC(0) |
| 760 | | IPSR_4_FUNC(0) |
| 761 | | IPSR_0_FUNC(0)); |
| 762 | |
| 763 | pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(0) |
| 764 | | IPSR_24_FUNC(0) |
| 765 | | IPSR_20_FUNC(0) |
| 766 | | IPSR_16_FUNC(0) |
| 767 | | IPSR_12_FUNC(0) |
| 768 | | IPSR_8_FUNC(0) |
| 769 | | IPSR_4_FUNC(0) |
| 770 | | IPSR_0_FUNC(0)); |
| 771 | |
| 772 | pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0) |
| 773 | | IPSR_24_FUNC(4) |
| 774 | | IPSR_20_FUNC(4) |
| 775 | | IPSR_16_FUNC(4) |
| 776 | | IPSR_12_FUNC(4) |
| 777 | | IPSR_8_FUNC(0) |
| 778 | | IPSR_4_FUNC(0) |
| 779 | | IPSR_0_FUNC(0)); |
| 780 | |
| 781 | pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0) |
| 782 | | IPSR_24_FUNC(0) |
| 783 | | IPSR_20_FUNC(0) |
| 784 | | IPSR_16_FUNC(4) |
| 785 | | IPSR_12_FUNC(0) |
| 786 | | IPSR_8_FUNC(0) |
| 787 | | IPSR_4_FUNC(0) |
| 788 | | IPSR_0_FUNC(0)); |
| 789 | |
| 790 | /* initialize POC Control */ |
| 791 | |
| 792 | pfc_reg_write(PFC_IOCTRL30, IOCTRL30_POC_VI0_DATA5 |
| 793 | | IOCTRL30_POC_VI0_DATA4 |
| 794 | | IOCTRL30_POC_VI0_DATA3 |
| 795 | | IOCTRL30_POC_VI0_DATA2 |
| 796 | | IOCTRL30_POC_VI0_DATA1 |
| 797 | | IOCTRL30_POC_VI0_DATA0 |
| 798 | | IOCTRL30_POC_VI0_VSYNC_N |
| 799 | | IOCTRL30_POC_VI0_HSYNC_N |
| 800 | | IOCTRL30_POC_VI0_CLKENB |
| 801 | | IOCTRL30_POC_VI0_CLK |
| 802 | | IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE |
| 803 | | IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC |
| 804 | | IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC |
| 805 | | IOCTRL30_POC_DU_DOTCLKOUT |
| 806 | | IOCTRL30_POC_DU_DB7 |
| 807 | | IOCTRL30_POC_DU_DB6 |
| 808 | | IOCTRL30_POC_DU_DB5 |
| 809 | | IOCTRL30_POC_DU_DB4 |
| 810 | | IOCTRL30_POC_DU_DB3 |
| 811 | | IOCTRL30_POC_DU_DB2 |
| 812 | | IOCTRL30_POC_DU_DG7 |
| 813 | | IOCTRL30_POC_DU_DG6 |
| 814 | | IOCTRL30_POC_DU_DG5 |
| 815 | | IOCTRL30_POC_DU_DG4 |
| 816 | | IOCTRL30_POC_DU_DG3 |
| 817 | | IOCTRL30_POC_DU_DG2 |
| 818 | | IOCTRL30_POC_DU_DR7 |
| 819 | | IOCTRL30_POC_DU_DR6 |
| 820 | | IOCTRL30_POC_DU_DR5 |
| 821 | | IOCTRL30_POC_DU_DR4 |
| 822 | | IOCTRL30_POC_DU_DR3 |
| 823 | | IOCTRL30_POC_DU_DR2); |
| 824 | |
| 825 | pfc_reg_write(PFC_IOCTRL31, IOCTRL31_POC_DUMMY_31 |
| 826 | | IOCTRL31_POC_DUMMY_30 |
| 827 | | IOCTRL31_POC_DUMMY_29 |
| 828 | | IOCTRL31_POC_DUMMY_28 |
| 829 | | IOCTRL31_POC_DUMMY_27 |
| 830 | | IOCTRL31_POC_DUMMY_26 |
| 831 | | IOCTRL31_POC_DUMMY_25 |
| 832 | | IOCTRL31_POC_DUMMY_24 |
| 833 | | IOCTRL31_POC_VI1_FIELD |
| 834 | | IOCTRL31_POC_VI1_DATA11 |
| 835 | | IOCTRL31_POC_VI1_DATA10 |
| 836 | | IOCTRL31_POC_VI1_DATA9 |
| 837 | | IOCTRL31_POC_VI1_DATA8 |
| 838 | | IOCTRL31_POC_VI1_DATA7 |
| 839 | | IOCTRL31_POC_VI1_DATA6 |
| 840 | | IOCTRL31_POC_VI1_DATA5 |
| 841 | | IOCTRL31_POC_VI1_DATA4 |
| 842 | | IOCTRL31_POC_VI1_DATA3 |
| 843 | | IOCTRL31_POC_VI1_DATA2 |
| 844 | | IOCTRL31_POC_VI1_DATA1 |
| 845 | | IOCTRL31_POC_VI1_DATA0 |
| 846 | | IOCTRL31_POC_VI1_VSYNC_N |
| 847 | | IOCTRL31_POC_VI1_HSYNC_N |
| 848 | | IOCTRL31_POC_VI1_CLKENB |
| 849 | | IOCTRL31_POC_VI1_CLK |
| 850 | | IOCTRL31_POC_VI0_FIELD |
| 851 | | IOCTRL31_POC_VI0_DATA11 |
| 852 | | IOCTRL31_POC_VI0_DATA10 |
| 853 | | IOCTRL31_POC_VI0_DATA9 |
| 854 | | IOCTRL31_POC_VI0_DATA8 |
| 855 | | IOCTRL31_POC_VI0_DATA7 |
| 856 | | IOCTRL31_POC_VI0_DATA6); |
| 857 | |
| 858 | pfc_reg_write(PFC_IOCTRL32,0x00000000); |
| 859 | |
| 860 | pfc_reg_write(PFC_IOCTRL40,0x00000000); |
| 861 | |
| 862 | /* initialize Pull enable */ |
| 863 | pfc_reg_write(PFC_PUEN0,PUEN0_PUEN_VI0_CLK |
| 864 | | PUEN0_PUEN_TDI |
| 865 | | PUEN0_PUEN_TMS |
| 866 | | PUEN0_PUEN_TCK |
| 867 | | PUEN0_PUEN_TRST_N |
| 868 | | PUEN0_PUEN_IRQ0 |
| 869 | | PUEN0_PUEN_FSCLKST_N |
| 870 | | PUEN0_PUEN_DU_EXHSYNC_DU_HSYNC |
| 871 | | PUEN0_PUEN_DU_DOTCLKOUT |
| 872 | | PUEN0_PUEN_DU_DB7 |
| 873 | | PUEN0_PUEN_DU_DB6 |
| 874 | | PUEN0_PUEN_DU_DB5 |
| 875 | | PUEN0_PUEN_DU_DB4 |
| 876 | | PUEN0_PUEN_DU_DB3 |
| 877 | | PUEN0_PUEN_DU_DB2 |
| 878 | | PUEN0_PUEN_DU_DG7 |
| 879 | | PUEN0_PUEN_DU_DG6 |
| 880 | | PUEN0_PUEN_DU_DG5 |
| 881 | | PUEN0_PUEN_DU_DG4 |
| 882 | | PUEN0_PUEN_DU_DG3 |
| 883 | | PUEN0_PUEN_DU_DG2 |
| 884 | | PUEN0_PUEN_DU_DR7 |
| 885 | | PUEN0_PUEN_DU_DR6 |
| 886 | | PUEN0_PUEN_DU_DR5 |
| 887 | | PUEN0_PUEN_DU_DR4 |
| 888 | | PUEN0_PUEN_DU_DR3 |
| 889 | | PUEN0_PUEN_DU_DR2); |
| 890 | |
| 891 | pfc_reg_write(PFC_PUEN1,PUEN1_PUEN_VI1_DATA11 |
| 892 | | PUEN1_PUEN_VI1_DATA10 |
| 893 | | PUEN1_PUEN_VI1_DATA9 |
| 894 | | PUEN1_PUEN_VI1_DATA8 |
| 895 | | PUEN1_PUEN_VI1_DATA7 |
| 896 | | PUEN1_PUEN_VI1_DATA6 |
| 897 | | PUEN1_PUEN_VI1_DATA5 |
| 898 | | PUEN1_PUEN_VI1_DATA4 |
| 899 | | PUEN1_PUEN_VI1_DATA3 |
| 900 | | PUEN1_PUEN_VI1_DATA2 |
| 901 | | PUEN1_PUEN_VI1_DATA1 |
| 902 | | PUEN1_PUEN_VI1_DATA0 |
| 903 | | PUEN1_PUEN_VI1_VSYNC_N |
| 904 | | PUEN1_PUEN_VI1_HSYNC_N |
| 905 | | PUEN1_PUEN_VI1_CLKENB |
| 906 | | PUEN1_PUEN_VI1_CLK |
| 907 | | PUEN1_PUEN_VI0_DATA11 |
| 908 | | PUEN1_PUEN_VI0_DATA10 |
| 909 | | PUEN1_PUEN_VI0_DATA9 |
| 910 | | PUEN1_PUEN_VI0_DATA8 |
| 911 | | PUEN1_PUEN_VI0_DATA7 |
| 912 | | PUEN1_PUEN_VI0_DATA6 |
| 913 | | PUEN1_PUEN_VI0_DATA5 |
| 914 | | PUEN1_PUEN_VI0_DATA4 |
| 915 | | PUEN1_PUEN_VI0_DATA3 |
| 916 | | PUEN1_PUEN_VI0_DATA2 |
| 917 | | PUEN1_PUEN_VI0_DATA1); |
| 918 | |
| 919 | pfc_reg_write(PFC_PUEN2,PUEN2_PUEN_CANFD_CLK |
| 920 | | PUEN2_PUEN_CANFD1_RX |
| 921 | | PUEN2_PUEN_CANFD1_TX |
| 922 | | PUEN2_PUEN_CANFD0_RX |
| 923 | | PUEN2_PUEN_CANFD0_TX |
| 924 | | PUEN2_PUEN_AVB0_AVTP_CAPTURE |
| 925 | | PUEN2_PUEN_AVB0_AVTP_MATCH |
| 926 | | PUEN2_PUEN_AVB0_LINK |
| 927 | | PUEN2_PUEN_AVB0_PHY_INT |
| 928 | | PUEN2_PUEN_AVB0_MAGIC |
| 929 | | PUEN2_PUEN_AVB0_TXCREFCLK |
| 930 | | PUEN2_PUEN_AVB0_TD3 |
| 931 | | PUEN2_PUEN_AVB0_TD2 |
| 932 | | PUEN2_PUEN_AVB0_TD1 |
| 933 | | PUEN2_PUEN_AVB0_TD0 |
| 934 | | PUEN2_PUEN_AVB0_TXC |
| 935 | | PUEN2_PUEN_AVB0_TX_CTL |
| 936 | | PUEN2_PUEN_AVB0_RD3 |
| 937 | | PUEN2_PUEN_AVB0_RD2 |
| 938 | | PUEN2_PUEN_AVB0_RD1 |
| 939 | | PUEN2_PUEN_AVB0_RD0 |
| 940 | | PUEN2_PUEN_AVB0_RXC |
| 941 | | PUEN2_PUEN_AVB0_RX_CTL |
| 942 | | PUEN2_PUEN_VI1_FIELD); |
| 943 | |
| 944 | pfc_reg_write(PFC_PUEN3,PUEN3_PUEN_DIGRF_CLKOUT |
| 945 | | PUEN3_PUEN_DIGRF_CLKIN); |
| 946 | |
| 947 | /* initialize PUD Control */ |
| 948 | pfc_reg_write(PFC_PUD0,PUD0_PUD_VI0_CLK |
| 949 | | PUD0_PUD_IRQ0 |
| 950 | | PUD0_PUD_FSCLKST_N |
| 951 | | PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE |
| 952 | | PUD0_PUD_DU_EXVSYNC_DU_VSYNC |
| 953 | | PUD0_PUD_DU_EXHSYNC_DU_HSYNC |
| 954 | | PUD0_PUD_DU_DOTCLKOUT |
| 955 | | PUD0_PUD_DU_DB7 |
| 956 | | PUD0_PUD_DU_DB6 |
| 957 | | PUD0_PUD_DU_DB5 |
| 958 | | PUD0_PUD_DU_DB4 |
| 959 | | PUD0_PUD_DU_DB3 |
| 960 | | PUD0_PUD_DU_DB2 |
| 961 | | PUD0_PUD_DU_DG7 |
| 962 | | PUD0_PUD_DU_DG6 |
| 963 | | PUD0_PUD_DU_DG5 |
| 964 | | PUD0_PUD_DU_DG4 |
| 965 | | PUD0_PUD_DU_DG3 |
| 966 | | PUD0_PUD_DU_DG2 |
| 967 | | PUD0_PUD_DU_DR7 |
| 968 | | PUD0_PUD_DU_DR6 |
| 969 | | PUD0_PUD_DU_DR5 |
| 970 | | PUD0_PUD_DU_DR4 |
| 971 | | PUD0_PUD_DU_DR3 |
| 972 | | PUD0_PUD_DU_DR2); |
| 973 | |
| 974 | pfc_reg_write(PFC_PUD1,PUD1_PUD_VI1_DATA11 |
| 975 | | PUD1_PUD_VI1_DATA10 |
| 976 | | PUD1_PUD_VI1_DATA9 |
| 977 | | PUD1_PUD_VI1_DATA8 |
| 978 | | PUD1_PUD_VI1_DATA7 |
| 979 | | PUD1_PUD_VI1_DATA6 |
| 980 | | PUD1_PUD_VI1_DATA5 |
| 981 | | PUD1_PUD_VI1_DATA4 |
| 982 | | PUD1_PUD_VI1_DATA3 |
| 983 | | PUD1_PUD_VI1_DATA2 |
| 984 | | PUD1_PUD_VI1_DATA1 |
| 985 | | PUD1_PUD_VI1_DATA0 |
| 986 | | PUD1_PUD_VI1_VSYNC_N |
| 987 | | PUD1_PUD_VI1_HSYNC_N |
| 988 | | PUD1_PUD_VI1_CLKENB |
| 989 | | PUD1_PUD_VI1_CLK |
| 990 | | PUD1_PUD_VI0_DATA11 |
| 991 | | PUD1_PUD_VI0_DATA10 |
| 992 | | PUD1_PUD_VI0_DATA9 |
| 993 | | PUD1_PUD_VI0_DATA8 |
| 994 | | PUD1_PUD_VI0_DATA7 |
| 995 | | PUD1_PUD_VI0_DATA6 |
| 996 | | PUD1_PUD_VI0_DATA5 |
| 997 | | PUD1_PUD_VI0_DATA4 |
| 998 | | PUD1_PUD_VI0_DATA3 |
| 999 | | PUD1_PUD_VI0_DATA2 |
| 1000 | | PUD1_PUD_VI0_DATA1 |
| 1001 | | PUD1_PUD_VI0_DATA0 |
| 1002 | | PUD1_PUD_VI0_VSYNC_N |
| 1003 | | PUD1_PUD_VI0_HSYNC_N |
| 1004 | | PUD1_PUD_VI0_CLKENB); |
| 1005 | |
| 1006 | pfc_reg_write(PFC_PUD2,PUD2_PUD_CANFD_CLK |
| 1007 | | PUD2_PUD_CANFD1_RX |
| 1008 | | PUD2_PUD_CANFD1_TX |
| 1009 | | PUD2_PUD_CANFD0_RX |
| 1010 | | PUD2_PUD_CANFD0_TX |
| 1011 | | PUD2_PUD_AVB0_AVTP_CAPTURE |
| 1012 | | PUD2_PUD_VI1_FIELD); |
| 1013 | |
| 1014 | pfc_reg_write(PFC_PUD3,PUD3_PUD_DIGRF_CLKOUT |
| 1015 | | PUD3_PUD_DIGRF_CLKIN); |
| 1016 | |
| 1017 | /* initialize Module Select */ |
| 1018 | pfc_reg_write(PFC_MOD_SEL0,0x00000000); |
| 1019 | |
| 1020 | // gpio |
| 1021 | /* initialize positive/negative logic select */ |
| 1022 | mmio_write_32(GPIO_POSNEG0, 0x00000000U); |
| 1023 | mmio_write_32(GPIO_POSNEG1, 0x00000000U); |
| 1024 | mmio_write_32(GPIO_POSNEG2, 0x00000000U); |
| 1025 | mmio_write_32(GPIO_POSNEG3, 0x00000000U); |
| 1026 | mmio_write_32(GPIO_POSNEG4, 0x00000000U); |
| 1027 | mmio_write_32(GPIO_POSNEG5, 0x00000000U); |
| 1028 | |
| 1029 | /* initialize general IO/interrupt switching */ |
| 1030 | mmio_write_32(GPIO_IOINTSEL0, 0x00000000U); |
| 1031 | mmio_write_32(GPIO_IOINTSEL1, 0x00000000U); |
| 1032 | mmio_write_32(GPIO_IOINTSEL2, 0x00000000U); |
| 1033 | mmio_write_32(GPIO_IOINTSEL3, 0x00000000U); |
| 1034 | mmio_write_32(GPIO_IOINTSEL4, 0x00000000U); |
| 1035 | mmio_write_32(GPIO_IOINTSEL5, 0x00000000U); |
| 1036 | |
| 1037 | /* initialize general output register */ |
| 1038 | mmio_write_32(GPIO_OUTDT0, 0x00000000U); |
| 1039 | mmio_write_32(GPIO_OUTDT1, 0x00000000U); |
| 1040 | mmio_write_32(GPIO_OUTDT2, 0x00000000U); |
| 1041 | mmio_write_32(GPIO_OUTDT3, 0x00000000U); |
| 1042 | mmio_write_32(GPIO_OUTDT4, 0x00000000U); |
| 1043 | mmio_write_32(GPIO_OUTDT5, 0x00000000U); |
| 1044 | |
| 1045 | /* initialize general input/output switching */ |
| 1046 | mmio_write_32(GPIO_INOUTSEL0, 0x00000000U); |
| 1047 | mmio_write_32(GPIO_INOUTSEL1, 0x00000000U); |
| 1048 | mmio_write_32(GPIO_INOUTSEL2, 0x00000000U); |
| 1049 | mmio_write_32(GPIO_INOUTSEL3, 0x00000000U); |
| 1050 | mmio_write_32(GPIO_INOUTSEL4, 0x00000000U); |
| 1051 | mmio_write_32(GPIO_INOUTSEL5, 0x00000000U); |
| 1052 | } |