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Varun Wadekarb316e242015-05-19 16:48:04 +05301#
Varun Wadekared3c62b2017-03-06 09:15:15 -08002# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05303#
dp-armfa3cf0b2017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05305#
6
Varun Wadekara78bb1b2015-08-07 10:03:00 +05307SOC_DIR := plat/nvidia/tegra/soc/${TARGET_SOC}
8
Varun Wadekara441f722017-04-26 13:46:11 -07009# dump the state on crash console
10CRASH_REPORTING := 1
11$(eval $(call add_define,CRASH_REPORTING))
Varun Wadekar6077dce2016-01-27 11:31:06 -080012
Varun Wadekar38c80222017-04-26 13:48:19 -070013# enable assert() for release/debug builds
14ENABLE_ASSERTIONS := 1
Varun Wadekar96658a92017-08-03 11:38:32 -070015PLAT_LOG_LEVEL_ASSERT := 40
16$(eval $(call add_define,PLAT_LOG_LEVEL_ASSERT))
Varun Wadekar38c80222017-04-26 13:48:19 -070017
Varun Wadekara441f722017-04-26 13:46:11 -070018# enable dynamic memory mapping
19PLAT_XLAT_TABLES_DYNAMIC := 1
20$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
21
22# Enable PSCI v1.0 extended state ID format
23PSCI_EXTENDED_STATE_ID := 1
24
25# code and read-only data should be put on separate memory pages
26SEPARATE_CODE_AND_RODATA := 1
27
28# do not use coherent memory
29USE_COHERENT_MEM := 0
30
David Cunadoc5b0c0f2017-10-31 23:19:21 +000031# do not enable SVE
32ENABLE_SVE_FOR_NS := 0
33
Varun Wadekarb316e242015-05-19 16:48:04 +053034include plat/nvidia/tegra/common/tegra_common.mk
35include ${SOC_DIR}/platform_${TARGET_SOC}.mk
Varun Wadekarc39b0ba2015-07-21 10:16:13 +053036
37# modify BUILD_PLAT to point to SoC specific build directory
38BUILD_PLAT := ${BUILD_BASE}/${PLAT}/${TARGET_SOC}/${BUILD_TYPE}
Varun Wadekar66231d12017-06-07 09:57:42 -070039
40# enable signed comparison checks
Douglas Raillard8b043582017-06-22 14:47:01 +010041TF_CFLAGS += -Wsign-compare