blob: 1f5264a111081829cb720737991953f37c4ae48b [file] [log] [blame]
Pankaj Gupta088084e2020-12-09 14:02:40 +05301/*
2 * Copyright 2021 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8#ifndef PLAT_NV_STRG_H
9#define PLAT_NV_STRG_H
10
11#define DEFAULT_SET_VALUE 0xA1
12#define READY_TO_WRITE_VALUE 0xFF
13
14#ifndef NV_STORAGE_BASE_ADDR
15#define NV_STORAGE_BASE_ADDR DEFAULT_NV_STORAGE_BASE_ADDR
16#endif
17
18typedef struct {
19uint8_t warm_rst_flag;
20uint8_t wdt_rst_flag;
21uint8_t dummy[2];
22} nv_app_data_t;
23
24
25/*below enum and above structure should be in-sync. */
26enum app_data_offset {
27 WARM_RESET_FLAG_OFFSET,
28 WDT_RESET_FLAG_OFFSET,
29 APP_DATA_MAX_OFFSET,
30};
31
32int read_nv_app_data(void);
33
34int wr_nv_app_data(int data_offset,
35 uint8_t *data,
36 int data_size);
37
38const nv_app_data_t *get_nv_data(void);
39
40#endif /* PLAT_NV_STRG_H */