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git01.mediatek.com / filogic / atf / 6940996cfdb3c6243c4f38d6e3482679287f8374 / . / fdts / fvp-base-gicv3-psci-aarch32-common.dtsi
blob: 6179c66e7d273d1ac501b88e35c489d253a2a5f6 [file] [log] [blame]
Imre Kisfe7c6c12019-08-08 19:06:12 +0200[diff] [blame]1/*
2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/memreserve/ 0x80000000 0x00010000;
8
9/ {
10};
11
12/ {
13 model = "FVP Base";
14 compatible = "arm,vfp-base", "arm,vexpress";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 chosen { };
20
21 aliases {
22 serial0 = &v2m_serial0;
23 serial1 = &v2m_serial1;
24 serial2 = &v2m_serial2;
25 serial3 = &v2m_serial3;
26 };
27
28 psci {
29 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
30 method = "smc";
31 cpu_suspend = <0x84000001>;
32 cpu_off = <0x84000002>;
33 cpu_on = <0x84000003>;
34 sys_poweroff = <0x84000008>;
35 sys_reset = <0x84000009>;
36 };
37
38 cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 cpu-map {
43 cluster0 {
44 core0 {
45 cpu = <&CPU0>;
46 };
47 core1 {
48 cpu = <&CPU1>;
49 };
50 core2 {
51 cpu = <&CPU2>;
52 };
53 core3 {
54 cpu = <&CPU3>;
55 };
56 };
57
58 cluster1 {
59 core0 {
60 cpu = <&CPU4>;
61 };
62 core1 {
63 cpu = <&CPU5>;
64 };
65 core2 {
66 cpu = <&CPU6>;
67 };
68 core3 {
69 cpu = <&CPU7>;
70 };
71 };
72 };
73
74 idle-states {
75 entry-method = "arm,psci";
76
77 CPU_SLEEP_0: cpu-sleep-0 {
78 compatible = "arm,idle-state";
79 local-timer-stop;
80 arm,psci-suspend-param = <0x0010000>;
81 entry-latency-us = <40>;
82 exit-latency-us = <100>;
83 min-residency-us = <150>;
84 };
85
86 CLUSTER_SLEEP_0: cluster-sleep-0 {
87 compatible = "arm,idle-state";
88 local-timer-stop;
89 arm,psci-suspend-param = <0x1010000>;
90 entry-latency-us = <500>;
91 exit-latency-us = <1000>;
92 min-residency-us = <2500>;
93 };
94 };
95
96 CPU0:cpu@0 {
97 device_type = "cpu";
98 compatible = "arm,armv8";
99 reg = <0x0>;
100 enable-method = "psci";
101 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
102 next-level-cache = <&L2_0>;
103 };
104
105 CPU1:cpu@1 {
106 device_type = "cpu";
107 compatible = "arm,armv8";
108 reg = <0x1>;
109 enable-method = "psci";
110 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
111 next-level-cache = <&L2_0>;
112 };
113
114 CPU2:cpu@2 {
115 device_type = "cpu";
116 compatible = "arm,armv8";
117 reg = <0x2>;
118 enable-method = "psci";
119 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
120 next-level-cache = <&L2_0>;
121 };
122
123 CPU3:cpu@3 {
124 device_type = "cpu";
125 compatible = "arm,armv8";
126 reg = <0x3>;
127 enable-method = "psci";
128 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
129 next-level-cache = <&L2_0>;
130 };
131
132 CPU4:cpu@100 {
133 device_type = "cpu";
134 compatible = "arm,armv8";
135 reg = <0x100>;
136 enable-method = "psci";
137 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
138 next-level-cache = <&L2_0>;
139 };
140
141 CPU5:cpu@101 {
142 device_type = "cpu";
143 compatible = "arm,armv8";
144 reg = <0x101>;
145 enable-method = "psci";
146 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
147 next-level-cache = <&L2_0>;
148 };
149
150 CPU6:cpu@102 {
151 device_type = "cpu";
152 compatible = "arm,armv8";
153 reg = <0x102>;
154 enable-method = "psci";
155 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
156 next-level-cache = <&L2_0>;
157 };
158
159 CPU7:cpu@103 {
160 device_type = "cpu";
161 compatible = "arm,armv8";
162 reg = <0x103>;
163 enable-method = "psci";
164 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
165 next-level-cache = <&L2_0>;
166 };
167
168 L2_0: l2-cache0 {
169 compatible = "cache";
170 };
171 };
172
173 memory@80000000 {
174 device_type = "memory";
175 reg = <0x00000000 0x80000000 0 0x7F000000>,
176 <0x00000008 0x80000000 0 0x80000000>;
177 };
178
179 gic: interrupt-controller@2f000000 {
180 compatible = "arm,gic-v3";
181 #interrupt-cells = <3>;
182 #address-cells = <2>;
183 #size-cells = <2>;
184 ranges;
185 interrupt-controller;
186 reg = <0x0 0x2f000000 0 0x10000>, // GICD
187 <0x0 0x2f100000 0 0x200000>, // GICR
188 <0x0 0x2c000000 0 0x2000>, // GICC
189 <0x0 0x2c010000 0 0x2000>, // GICH
190 <0x0 0x2c02f000 0 0x2000>; // GICV
191 interrupts = <1 9 4>;
192
193 its: its@2f020000 {
194 compatible = "arm,gic-v3-its";
195 msi-controller;
196 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
197 };
198 };
199
200 timer {
201 compatible = "arm,armv8-timer";
202 interrupts = <1 13 0xff01>,
203 <1 14 0xff01>,
204 <1 11 0xff01>,
205 <1 10 0xff01>;
206 clock-frequency = <100000000>;
207 };
208
209 timer@2a810000 {
210 compatible = "arm,armv7-timer-mem";
211 reg = <0x0 0x2a810000 0x0 0x10000>;
212 clock-frequency = <100000000>;
213 #address-cells = <2>;
214 #size-cells = <2>;
215 ranges;
216 frame@2a830000 {
217 frame-number = <1>;
218 interrupts = <0 26 4>;
219 reg = <0x0 0x2a830000 0x0 0x10000>;
220 };
221 };
222
223 pmu {
224 compatible = "arm,armv8-pmuv3";
225 interrupts = <0 60 4>,
226 <0 61 4>,
227 <0 62 4>,
228 <0 63 4>;
229 };
230
231 smb {
232 compatible = "simple-bus";
233
234 #address-cells = <2>;
235 #size-cells = <1>;
236 ranges = <0 0 0 0x08000000 0x04000000>,
237 <1 0 0 0x14000000 0x04000000>,
238 <2 0 0 0x18000000 0x04000000>,
239 <3 0 0 0x1c000000 0x04000000>,
240 <4 0 0 0x0c000000 0x04000000>,
241 <5 0 0 0x10000000 0x04000000>;
242
243 #interrupt-cells = <1>;
244 interrupt-map-mask = <0 0 63>;
245 interrupt-map = <0 0 0 &gic 0 0 0 0 4>,
246 <0 0 1 &gic 0 0 0 1 4>,
247 <0 0 2 &gic 0 0 0 2 4>,
248 <0 0 3 &gic 0 0 0 3 4>,
249 <0 0 4 &gic 0 0 0 4 4>,
250 <0 0 5 &gic 0 0 0 5 4>,
251 <0 0 6 &gic 0 0 0 6 4>,
252 <0 0 7 &gic 0 0 0 7 4>,
253 <0 0 8 &gic 0 0 0 8 4>,
254 <0 0 9 &gic 0 0 0 9 4>,
255 <0 0 10 &gic 0 0 0 10 4>,
256 <0 0 11 &gic 0 0 0 11 4>,
257 <0 0 12 &gic 0 0 0 12 4>,
258 <0 0 13 &gic 0 0 0 13 4>,
259 <0 0 14 &gic 0 0 0 14 4>,
260 <0 0 15 &gic 0 0 0 15 4>,
261 <0 0 16 &gic 0 0 0 16 4>,
262 <0 0 17 &gic 0 0 0 17 4>,
263 <0 0 18 &gic 0 0 0 18 4>,
264 <0 0 19 &gic 0 0 0 19 4>,
265 <0 0 20 &gic 0 0 0 20 4>,
266 <0 0 21 &gic 0 0 0 21 4>,
267 <0 0 22 &gic 0 0 0 22 4>,
268 <0 0 23 &gic 0 0 0 23 4>,
269 <0 0 24 &gic 0 0 0 24 4>,
270 <0 0 25 &gic 0 0 0 25 4>,
271 <0 0 26 &gic 0 0 0 26 4>,
272 <0 0 27 &gic 0 0 0 27 4>,
273 <0 0 28 &gic 0 0 0 28 4>,
274 <0 0 29 &gic 0 0 0 29 4>,
275 <0 0 30 &gic 0 0 0 30 4>,
276 <0 0 31 &gic 0 0 0 31 4>,
277 <0 0 32 &gic 0 0 0 32 4>,
278 <0 0 33 &gic 0 0 0 33 4>,
279 <0 0 34 &gic 0 0 0 34 4>,
280 <0 0 35 &gic 0 0 0 35 4>,
281 <0 0 36 &gic 0 0 0 36 4>,
282 <0 0 37 &gic 0 0 0 37 4>,
283 <0 0 38 &gic 0 0 0 38 4>,
284 <0 0 39 &gic 0 0 0 39 4>,
285 <0 0 40 &gic 0 0 0 40 4>,
286 <0 0 41 &gic 0 0 0 41 4>,
287 <0 0 42 &gic 0 0 0 42 4>;
288
289 /include/ "rtsm_ve-motherboard-aarch32.dtsi"
290 };
291
292 panels {
293 panel@0 {
294 compatible = "panel";
295 mode = "XVGA";
296 refresh = <60>;
297 xres = <1024>;
298 yres = <768>;
299 pixclock = <15748>;
300 left_margin = <152>;
301 right_margin = <48>;
302 upper_margin = <23>;
303 lower_margin = <3>;
304 hsync_len = <104>;
305 vsync_len = <4>;
306 sync = <0>;
307 vmode = "FB_VMODE_NONINTERLACED";
308 tim2 = "TIM2_BCD", "TIM2_IPC";
309 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
310 caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
311 bpp = <16>;
312 };
313 };
314};