| developer | 404e08b | 2020-09-18 09:32:31 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
| developer | 404e08b | 2020-09-18 09:32:31 +0800 | [diff] [blame] | 8 | #include <mtgpio.h> |
| 9 | #include <platform_def.h> |
| 10 | |
| developer | 912c7d2 | 2021-03-31 14:53:43 +0800 | [diff] [blame] | 11 | uintptr_t mt_gpio_find_reg_addr(uint32_t pin) |
| developer | 404e08b | 2020-09-18 09:32:31 +0800 | [diff] [blame] | 12 | { |
| 13 | uintptr_t reg_addr = 0U; |
| 14 | struct mt_pin_info gpio_info; |
| 15 | |
| developer | 912c7d2 | 2021-03-31 14:53:43 +0800 | [diff] [blame] | 16 | assert(pin < MAX_GPIO_PIN); |
| 17 | |
| 18 | gpio_info = mt_pin_infos[pin]; |
| developer | 404e08b | 2020-09-18 09:32:31 +0800 | [diff] [blame] | 19 | |
| 20 | switch (gpio_info.base & 0x0f) { |
| 21 | case 0: |
| 22 | reg_addr = IOCFG_RM_BASE; |
| 23 | break; |
| 24 | case 1: |
| 25 | reg_addr = IOCFG_BM_BASE; |
| 26 | break; |
| 27 | case 2: |
| 28 | reg_addr = IOCFG_BL_BASE; |
| 29 | break; |
| 30 | case 3: |
| 31 | reg_addr = IOCFG_BR_BASE; |
| 32 | break; |
| 33 | case 4: |
| 34 | reg_addr = IOCFG_LM_BASE; |
| 35 | break; |
| 36 | case 5: |
| 37 | reg_addr = IOCFG_LB_BASE; |
| 38 | break; |
| 39 | case 6: |
| 40 | reg_addr = IOCFG_RT_BASE; |
| 41 | break; |
| 42 | case 7: |
| 43 | reg_addr = IOCFG_LT_BASE; |
| 44 | break; |
| 45 | case 8: |
| 46 | reg_addr = IOCFG_TL_BASE; |
| 47 | break; |
| 48 | default: |
| 49 | break; |
| 50 | } |
| 51 | |
| 52 | return reg_addr; |
| 53 | } |