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Andre Przywaraffbacb02019-07-10 17:27:17 +01001/*
Javier Almansa Sobrino40f49842020-08-25 16:16:29 +01002 * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
Andre Przywaraffbacb02019-07-10 17:27:17 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef FDT_FIXUP_H
8#define FDT_FIXUP_H
9
Andre Przywaraf2a78fe2021-05-19 09:37:21 +010010#define INVALID_BASE_ADDR ((uintptr_t)~0UL)
11
Andre Przywaraffbacb02019-07-10 17:27:17 +010012int dt_add_psci_node(void *fdt);
13int dt_add_psci_cpu_enable_methods(void *fdt);
Andre Przywara83fc8392019-07-15 09:00:23 +010014int fdt_add_reserved_memory(void *dtb, const char *node_name,
15 uintptr_t base, size_t size);
Javier Almansa Sobrino40f49842020-08-25 16:16:29 +010016int fdt_add_cpus_node(void *dtb, unsigned int afflv0,
17 unsigned int afflv1, unsigned int afflv2);
Andre Przywaraf2a78fe2021-05-19 09:37:21 +010018int fdt_adjust_gic_redist(void *dtb, unsigned int nr_cores, uintptr_t gicr_base,
Andre Przywara64b9e142020-08-24 18:28:44 +010019 unsigned int gicr_frame_size);
Andre Przywaraffbacb02019-07-10 17:27:17 +010020
21#endif /* FDT_FIXUP_H */