Gary Morrison | d4d951a | 2021-11-10 14:40:15 -0600 | [diff] [blame] | 1 | Generic Threat Model |
Olivier Deprez | 86d1ffd | 2021-06-01 15:37:16 +0200 | [diff] [blame] | 2 | ******************** |
Zelalem | 05fed52 | 2021-02-24 19:20:09 -0600 | [diff] [blame] | 3 | |
Olivier Deprez | 86d1ffd | 2021-06-01 15:37:16 +0200 | [diff] [blame] | 4 | ************************ |
| 5 | Introduction |
| 6 | ************************ |
| 7 | This document provides a generic threat model for TF-A firmware. |
Zelalem | 05fed52 | 2021-02-24 19:20:09 -0600 | [diff] [blame] | 8 | |
Zelalem Aweke | 023b1a4 | 2021-10-21 13:59:45 -0500 | [diff] [blame] | 9 | .. note:: |
| 10 | |
| 11 | This threat model doesn't consider Root and Realm worlds introduced by |
| 12 | :ref:`Realm Management Extension (RME)`. |
| 13 | |
Zelalem | 05fed52 | 2021-02-24 19:20:09 -0600 | [diff] [blame] | 14 | ************************ |
| 15 | Target of Evaluation |
| 16 | ************************ |
| 17 | In this threat model, the target of evaluation is the Trusted |
| 18 | Firmware for A-class Processors (TF-A). This includes the boot ROM (BL1), |
| 19 | the trusted boot firmware (BL2) and the runtime EL3 firmware (BL31) as |
| 20 | shown on Figure 1. Everything else on Figure 1 is outside of the scope of |
| 21 | the evaluation. |
| 22 | |
| 23 | TF-A can be configured in various ways. In this threat model we consider |
| 24 | only the most basic configuration. To that end we make the following |
| 25 | assumptions: |
| 26 | |
| 27 | - All TF-A images are run from either ROM or on-chip trusted SRAM. This means |
| 28 | TF-A is not vulnerable to an attacker that can probe or tamper with off-chip |
| 29 | memory. |
Zelalem Aweke | 023b1a4 | 2021-10-21 13:59:45 -0500 | [diff] [blame] | 30 | |
Zelalem | 05fed52 | 2021-02-24 19:20:09 -0600 | [diff] [blame] | 31 | - Trusted boot is enabled. This means an attacker can't boot arbitrary images |
| 32 | that are not approved by platform providers. |
Zelalem Aweke | 023b1a4 | 2021-10-21 13:59:45 -0500 | [diff] [blame] | 33 | |
Zelalem | 05fed52 | 2021-02-24 19:20:09 -0600 | [diff] [blame] | 34 | - There is no Secure-EL2. We don't consider threats that may come with |
| 35 | Secure-EL2 software. |
| 36 | |
| 37 | Data Flow Diagram |
| 38 | ====================== |
| 39 | Figure 1 shows a high-level data flow diagram for TF-A. The diagram |
| 40 | shows a model of the different components of a TF-A-based system and |
| 41 | their interactions with TF-A. A description of each diagram element |
| 42 | is given on Table 1. On the diagram, the red broken lines indicate |
| 43 | trust boundaries. Components outside of the broken lines |
| 44 | are considered untrusted by TF-A. |
| 45 | |
| 46 | .. uml:: ../resources/diagrams/plantuml/tfa_dfd.puml |
| 47 | :caption: Figure 1: TF-A Data Flow Diagram |
| 48 | |
| 49 | .. table:: Table 1: TF-A Data Flow Diagram Description |
| 50 | |
| 51 | +-----------------+--------------------------------------------------------+ |
| 52 | | Diagram Element | Description | |
| 53 | +=================+========================================================+ |
| 54 | | ``DF1`` | | At boot time, images are loaded from non-volatile | |
| 55 | | | memory and verified by TF-A boot firmware. These | |
| 56 | | | images include TF-A BL2 and BL31 images, as well as | |
| 57 | | | other secure and non-secure images. | |
| 58 | +-----------------+--------------------------------------------------------+ |
| 59 | | ``DF2`` | | TF-A log system framework outputs debug messages | |
| 60 | | | over a UART interface. | |
| 61 | +-----------------+--------------------------------------------------------+ |
| 62 | | ``DF3`` | | Debug and trace IP on a platform can allow access | |
| 63 | | | to registers and memory of TF-A. | |
| 64 | +-----------------+--------------------------------------------------------+ |
| 65 | | ``DF4`` | | Secure world software (e.g. trusted OS) interact | |
| 66 | | | with TF-A through SMC call interface and/or shared | |
| 67 | | | memory. | |
| 68 | +-----------------+--------------------------------------------------------+ |
| 69 | | ``DF5`` | | Non-secure world software (e.g. rich OS) interact | |
| 70 | | | with TF-A through SMC call interface and/or shared | |
| 71 | | | memory. | |
| 72 | +-----------------+--------------------------------------------------------+ |
| 73 | | ``DF6`` | | This path represents the interaction between TF-A and| |
| 74 | | | various hardware IPs such as TrustZone controller | |
| 75 | | | and GIC. At boot time TF-A configures/initializes the| |
| 76 | | | IPs and interacts with them at runtime through | |
| 77 | | | interrupts and registers. | |
| 78 | +-----------------+--------------------------------------------------------+ |
| 79 | |
| 80 | |
| 81 | ********************* |
| 82 | Threat Analysis |
| 83 | ********************* |
| 84 | In this section we identify and provide assessment of potential threats to TF-A |
| 85 | firmware. The threats are identified for each diagram element on the |
| 86 | data flow diagram above. |
| 87 | |
| 88 | For each threat, we identify the *asset* that is under threat, the |
| 89 | *threat agent* and the *threat type*. Each threat is given a *risk rating* |
| 90 | that represents the impact and likelihood of that threat. We also discuss |
| 91 | potential mitigations. |
| 92 | |
| 93 | Assets |
| 94 | ================== |
| 95 | We have identified the following assets for TF-A: |
| 96 | |
| 97 | .. table:: Table 2: TF-A Assets |
| 98 | |
| 99 | +--------------------+---------------------------------------------------+ |
| 100 | | Asset | Description | |
| 101 | +====================+===================================================+ |
| 102 | | ``Sensitive Data`` | | These include sensitive data that an attacker | |
| 103 | | | must not be able to tamper with (e.g. the Root | |
| 104 | | | of Trust Public Key) or see (e.g. secure logs, | |
| 105 | | | debugging information such as crash reports). | |
| 106 | +--------------------+---------------------------------------------------+ |
| 107 | | ``Code Execution`` | | This represents the requirement that the | |
| 108 | | | platform should run only TF-A code approved by | |
| 109 | | | the platform provider. | |
| 110 | +--------------------+---------------------------------------------------+ |
| 111 | | ``Availability`` | | This represents the requirement that TF-A | |
| 112 | | | services should always be available for use. | |
| 113 | +--------------------+---------------------------------------------------+ |
| 114 | |
| 115 | Threat Agents |
| 116 | ===================== |
| 117 | To understand the attack surface, it is important to identify potential |
| 118 | attackers, i.e. attack entry points. The following threat agents are |
| 119 | in scope of this threat model. |
| 120 | |
| 121 | .. table:: Table 3: Threat Agents |
| 122 | |
| 123 | +-------------------+-------------------------------------------------------+ |
| 124 | | Threat Agent | Description | |
| 125 | +===================+=======================================================+ |
| 126 | | ``NSCode`` | | Malicious or faulty code running in the Non-secure | |
| 127 | | | world, including NS-EL0 NS-EL1 and NS-EL2 levels | |
| 128 | +-------------------+-------------------------------------------------------+ |
| 129 | | ``SecCode`` | | Malicious or faulty code running in the secure | |
| 130 | | | world, including S-EL0 and S-EL1 levels | |
| 131 | +-------------------+-------------------------------------------------------+ |
| 132 | | ``AppDebug`` | | Physical attacker using debug signals to access | |
| 133 | | | TF-A resources | |
| 134 | +-------------------+-------------------------------------------------------+ |
| 135 | | ``PhysicalAccess``| | Physical attacker having access to external device | |
| 136 | | | communication bus and to external flash | |
| 137 | | | communication bus using common hardware | |
| 138 | +-------------------+-------------------------------------------------------+ |
| 139 | |
| 140 | .. note:: |
| 141 | |
| 142 | In this threat model an advanced physical attacker that has the capability |
| 143 | to tamper with a hardware (e.g. "rewiring" a chip using a focused |
| 144 | ion beam (FIB) workstation or decapsulate the chip using chemicals) is |
| 145 | considered out-of-scope. |
| 146 | |
| 147 | Threat Types |
| 148 | ======================== |
| 149 | In this threat model we categorize threats using the `STRIDE threat |
| 150 | analysis technique`_. In this technique a threat is categorized as one |
| 151 | or more of these types: ``Spoofing``, ``Tampering``, ``Repudiation``, |
| 152 | ``Information disclosure``, ``Denial of service`` or |
| 153 | ``Elevation of privilege``. |
| 154 | |
| 155 | Threat Risk Ratings |
| 156 | ======================== |
| 157 | For each threat identified, a risk rating that ranges |
| 158 | from *informational* to *critical* is given based on the likelihood of the |
| 159 | threat occuring if a mitigation is not in place, and the impact of the |
| 160 | threat (i.e. how severe the consequences could be). Table 4 explains each |
| 161 | rating in terms of score, impact and likelihood. |
| 162 | |
| 163 | .. table:: Table 4: Rating and score as applied to impact and likelihood |
| 164 | |
| 165 | +-----------------------+-------------------------+---------------------------+ |
| 166 | | **Rating (Score)** | **Impact** | **Likelihood** | |
| 167 | +=======================+=========================+===========================+ |
| 168 | | ``Critical (5)`` | | Extreme impact to | | Threat is almost | |
| 169 | | | entire organization | certain to be exploited.| |
| 170 | | | if exploited. | | |
| 171 | | | | | Knowledge of the threat | |
| 172 | | | | and how to exploit it | |
| 173 | | | | are in the public | |
| 174 | | | | domain. | |
| 175 | +-----------------------+-------------------------+---------------------------+ |
| 176 | | ``High (4)`` | | Major impact to entire| | Threat is relatively | |
| 177 | | | organization or single| easy to detect and | |
| 178 | | | line of business if | exploit by an attacker | |
| 179 | | | exploited | with little skill. | |
| 180 | +-----------------------+-------------------------+---------------------------+ |
| 181 | | ``Medium (3)`` | | Noticeable impact to | | A knowledgeable insider | |
| 182 | | | line of business if | or expert attacker could| |
| 183 | | | exploited. | exploit the threat | |
| 184 | | | | without much difficulty.| |
| 185 | +-----------------------+-------------------------+---------------------------+ |
| 186 | | ``Low (2)`` | | Minor damage if | | Exploiting the threat | |
| 187 | | | exploited or could | would require | |
| 188 | | | be used in conjunction| considerable expertise | |
| 189 | | | with other | and resources | |
| 190 | | | vulnerabilities to | | |
| 191 | | | perform a more serious| | |
| 192 | | | attack | | |
| 193 | +-----------------------+-------------------------+---------------------------+ |
| 194 | | ``Informational (1)`` | | Poor programming | | Threat is not likely | |
| 195 | | | practice or poor | to be exploited on its | |
| 196 | | | design decision that | own, but may be used to | |
| 197 | | | may not represent an | gain information for | |
| 198 | | | immediate risk on its | launching another | |
| 199 | | | own, but may have | attack | |
| 200 | | | security implications | | |
| 201 | | | if multiplied and/or | | |
| 202 | | | combined with other | | |
| 203 | | | threats. | | |
| 204 | +-----------------------+-------------------------+---------------------------+ |
| 205 | |
| 206 | Aggregate risk scores are assigned to identified threats; |
| 207 | specifically, the impact score multiplied by the likelihood score. |
| 208 | For example, a threat with high likelihood and low impact would have an |
| 209 | aggregate risk score of eight (8); that is, four (4) for high likelihood |
| 210 | multiplied by two (2) for low impact. The aggregate risk score determines |
| 211 | the finding's overall risk level, as shown in the following table. |
| 212 | |
| 213 | .. table:: Table 5: Overall risk levels and corresponding aggregate scores |
| 214 | |
| 215 | +---------------------+-----------------------------------+ |
| 216 | | Overall Risk Level | Aggregate Risk Score | |
| 217 | | | (Impact multiplied by Likelihood) | |
| 218 | +=====================+===================================+ |
| 219 | | Critical | 20–25 | |
| 220 | +---------------------+-----------------------------------+ |
| 221 | | High | 12–19 | |
| 222 | +---------------------+-----------------------------------+ |
| 223 | | Medium | 6–11 | |
| 224 | +---------------------+-----------------------------------+ |
| 225 | | Low | 2–5 | |
| 226 | +---------------------+-----------------------------------+ |
| 227 | | Informational | 1 | |
| 228 | +---------------------+-----------------------------------+ |
| 229 | |
| 230 | The likelihood and impact of a threat depends on the |
| 231 | target environment in which TF-A is running. For example, attacks |
| 232 | that require physical access are unlikely in server environments while |
| 233 | they are more common in Internet of Things(IoT) environments. |
| 234 | In this threat model we consider three target environments: |
| 235 | ``Internet of Things(IoT)``, ``Mobile`` and ``Server``. |
| 236 | |
| 237 | Threat Assessment |
| 238 | ============================ |
| 239 | The following threats were identified by applying STRIDE analysis on |
| 240 | each diagram element of the data flow diagram. |
| 241 | |
| 242 | +------------------------+----------------------------------------------------+ |
| 243 | | ID | 01 | |
| 244 | +========================+====================================================+ |
| 245 | | ``Threat`` | | **An attacker can mangle firmware images to | |
| 246 | | | execute arbitrary code** | |
| 247 | | | | |
| 248 | | | | Some TF-A images are loaded from external | |
| 249 | | | storage. It is possible for an attacker to access| |
| 250 | | | the external flash memory and change its contents| |
| 251 | | | physically, through the Rich OS, or using the | |
| 252 | | | updating mechanism to modify the non-volatile | |
| 253 | | | images to execute arbitrary code. | |
| 254 | +------------------------+----------------------------------------------------+ |
| 255 | | ``Diagram Elements`` | DF1, DF4, DF5 | |
| 256 | +------------------------+----------------------------------------------------+ |
| 257 | | ``Affected TF-A | BL2, BL31 | |
| 258 | | Components`` | | |
| 259 | +------------------------+----------------------------------------------------+ |
| 260 | | ``Assets`` | Code Execution | |
| 261 | +------------------------+----------------------------------------------------+ |
| 262 | | ``Threat Agent`` | PhysicalAccess, NSCode, SecCode | |
| 263 | +------------------------+----------------------------------------------------+ |
| 264 | | ``Threat Type`` | Tampering, Elevation of Privilege | |
| 265 | +------------------------+------------------+-----------------+---------------+ |
| 266 | | ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | |
| 267 | +------------------------+------------------+-----------------+---------------+ |
| 268 | | ``Impact`` | Critical (5) | Critical (5) | Critical (5) | |
| 269 | +------------------------+------------------+-----------------+---------------+ |
| 270 | | ``Likelihood`` | Critical (5) | Critical (5) | Critical (5) | |
| 271 | +------------------------+------------------+-----------------+---------------+ |
| 272 | | ``Total Risk Rating`` | Critical (25) | Critical (25) | Critical (25) | |
| 273 | +------------------------+------------------+-----------------+---------------+ |
| 274 | | ``Mitigations`` | | TF-A implements the `Trusted Board Boot (TBB)`_ | |
| 275 | | | feature which prevents malicious firmware from | |
| 276 | | | running on the platform by authenticating all | |
| 277 | | | firmware images. In addition to this, the TF-A | |
| 278 | | | boot firmware performs extra checks on | |
| 279 | | | unauthenticated data, such as FIP metadata, prior| |
| 280 | | | to use. | |
| 281 | +------------------------+----------------------------------------------------+ |
| 282 | |
| 283 | +------------------------+----------------------------------------------------+ |
| 284 | | ID | 02 | |
| 285 | +========================+====================================================+ |
| 286 | | ``Threat`` | | **An attacker may attempt to boot outdated, | |
| 287 | | | potentially vulnerable firmware image** | |
| 288 | | | | |
| 289 | | | | When updating firmware, an attacker may attempt | |
| 290 | | | to rollback to an older version that has unfixed | |
| 291 | | | vulnerabilities. | |
| 292 | +------------------------+----------------------------------------------------+ |
| 293 | | ``Diagram Elements`` | DF1, DF4, DF5 | |
| 294 | +------------------------+----------------------------------------------------+ |
| 295 | | ``Affected TF-A | BL2, BL31 | |
| 296 | | Components`` | | |
| 297 | +------------------------+----------------------------------------------------+ |
| 298 | | ``Assets`` | Code Execution | |
| 299 | +------------------------+----------------------------------------------------+ |
| 300 | | ``Threat Agent`` | PhysicalAccess, NSCode, SecCode | |
| 301 | +------------------------+----------------------------------------------------+ |
| 302 | | ``Threat Type`` | Tampering | |
| 303 | +------------------------+------------------+-----------------+---------------+ |
| 304 | | ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | |
| 305 | +------------------------+------------------+-----------------+---------------+ |
| 306 | | ``Impact`` | Critical (5) | Critical (5) | Critical (5) | |
| 307 | +------------------------+------------------+-----------------+---------------+ |
| 308 | | ``Likelihood`` | Critical (5) | Critical (5) | Critical (5) | |
| 309 | +------------------------+------------------+-----------------+---------------+ |
| 310 | | ``Total Risk Rating`` | Critical (25) | Critical (25) | Critical (25) | |
| 311 | +------------------------+------------------+-----------------+---------------+ |
| 312 | | ``Mitigations`` | | TF-A supports anti-rollback protection using | |
| 313 | | | non-volatile counters (NV counters) as required | |
| 314 | | | by `TBBR-Client specification`_. After a firmware| |
| 315 | | | image is validated, the image revision number | |
| 316 | | | taken from a certificate extension field is | |
| 317 | | | compared with the corresponding NV counter stored| |
| 318 | | | in hardware to make sure the new counter value is| |
| 319 | | | larger or equal to the current counter value. | |
| 320 | | | Platforms must implement this protection using | |
| 321 | | | platform specific hardware NV counters. | |
| 322 | +------------------------+----------------------------------------------------+ |
| 323 | |
| 324 | +------------------------+-------------------------------------------------------+ |
| 325 | | ID | 03 | |
| 326 | +========================+=======================================================+ |
| 327 | | ``Threat`` | | **An attacker can use Time-of-Check-Time-of-Use | |
| 328 | | | (TOCTOU) attack to bypass image authentication | |
| 329 | | | during the boot process** | |
| 330 | | | | |
| 331 | | | | Time-of-Check-Time-of-Use (TOCTOU) threats occur | |
| 332 | | | when the security check is produced before the time | |
| 333 | | | the resource is accessed. If an attacker is sitting | |
| 334 | | | in the middle of the off-chip images, they could | |
| 335 | | | change the binary containing executable code right | |
| 336 | | | after the integrity and authentication check has | |
| 337 | | | been performed. | |
| 338 | +------------------------+-------------------------------------------------------+ |
| 339 | | ``Diagram Elements`` | DF1 | |
| 340 | +------------------------+-------------------------------------------------------+ |
| 341 | | ``Affected TF-A | BL1, BL2 | |
| 342 | | Components`` | | |
| 343 | +------------------------+-------------------------------------------------------+ |
| 344 | | ``Assets`` | Code Execution, Sensitive Data | |
| 345 | +------------------------+-------------------------------------------------------+ |
| 346 | | ``Threat Agent`` | PhysicalAccess | |
| 347 | +------------------------+-------------------------------------------------------+ |
| 348 | | ``Threat Type`` | Elevation of Privilege | |
| 349 | +------------------------+---------------------+-----------------+---------------+ |
| 350 | | ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | |
| 351 | +------------------------+---------------------+-----------------+---------------+ |
| 352 | | ``Impact`` | N/A | Critical (5) | Critical (5) | |
| 353 | +------------------------+---------------------+-----------------+---------------+ |
| 354 | | ``Likelihood`` | N/A | Medium (3) | Medium (3) | |
| 355 | +------------------------+---------------------+-----------------+---------------+ |
| 356 | | ``Total Risk Rating`` | N/A | High (15) | High (15) | |
| 357 | +------------------------+---------------------+-----------------+---------------+ |
| 358 | | ``Mitigations`` | | TF-A boot firmware copies image to on-chip | |
| 359 | | | memory before authenticating an image. | |
| 360 | +------------------------+-------------------------------------------------------+ |
| 361 | |
| 362 | +------------------------+-------------------------------------------------------+ |
| 363 | | ID | 04 | |
| 364 | +========================+=======================================================+ |
| 365 | | ``Threat`` | | **An attacker with physical access can execute | |
| 366 | | | arbitrary image by bypassing the signature | |
| 367 | | | verification stage using glitching techniques** | |
| 368 | | | | |
| 369 | | | | Glitching (Fault injection) attacks attempt to put | |
| 370 | | | a hardware into a undefined state by manipulating an| |
| 371 | | | environmental variable such as power supply. | |
| 372 | | | | |
| 373 | | | | TF-A relies on a chain of trust that starts with the| |
| 374 | | | ROTPK, which is the key stored inside the chip and | |
| 375 | | | the root of all validation processes. If an attacker| |
| 376 | | | can break this chain of trust, they could execute | |
| 377 | | | arbitrary code on the device. This could be | |
| 378 | | | achieved with physical access to the device by | |
| 379 | | | attacking the normal execution flow of the | |
| 380 | | | process using glitching techniques that target | |
| 381 | | | points where the image is validated against the | |
| 382 | | | signature. | |
| 383 | +------------------------+-------------------------------------------------------+ |
| 384 | | ``Diagram Elements`` | DF1 | |
| 385 | +------------------------+-------------------------------------------------------+ |
| 386 | | ``Affected TF-A | BL1, BL2 | |
| 387 | | Components`` | | |
| 388 | +------------------------+-------------------------------------------------------+ |
| 389 | | ``Assets`` | Code Execution | |
| 390 | +------------------------+-------------------------------------------------------+ |
| 391 | | ``Threat Agent`` | PhysicalAccess | |
| 392 | +------------------------+-------------------------------------------------------+ |
| 393 | | ``Threat Type`` | Tampering, Elevation of Privilege | |
| 394 | +------------------------+---------------------+-----------------+---------------+ |
| 395 | | ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | |
| 396 | +------------------------+---------------------+-----------------+---------------+ |
| 397 | | ``Impact`` | N/A | Critical (5) | Critical (5) | |
| 398 | +------------------------+---------------------+-----------------+---------------+ |
| 399 | | ``Likelihood`` | N/A | Medium (3) | Medium (3) | |
| 400 | +------------------------+---------------------+-----------------+---------------+ |
| 401 | | ``Total Risk Rating`` | N/A | High (15) | High (15) | |
| 402 | +------------------------+---------------------+-----------------+---------------+ |
| 403 | | ``Mitigations`` | | The most effective mitigation is adding glitching | |
| 404 | | | detection and mitigation circuit at the hardware | |
| 405 | | | level. However, software techniques, | |
| 406 | | | such as adding redundant checks when performing | |
| 407 | | | conditional branches that are security sensitive, | |
| 408 | | | can be used to harden TF-A against such attacks. | |
| 409 | | | **At the moment TF-A doesn't implement such | |
| 410 | | | mitigations.** | |
| 411 | +------------------------+-------------------------------------------------------+ |
| 412 | |
| 413 | +------------------------+---------------------------------------------------+ |
| 414 | | ID | 05 | |
| 415 | +========================+===================================================+ |
| 416 | | ``Threat`` | | **Information leak via UART logs such as | |
| 417 | | | crashes** | |
| 418 | | | | |
| 419 | | | | During the development stages of software it is | |
| 420 | | | common to include crash reports with detailed | |
| 421 | | | information of the CPU state including current | |
| 422 | | | values of the registers, privilege level and | |
| 423 | | | stack dumps. This information is useful when | |
| 424 | | | debugging problems before releasing the | |
| 425 | | | production version, but it could be used by an | |
| 426 | | | attacker to develop a working exploit if left | |
| 427 | | | in the production version. | |
| 428 | +------------------------+---------------------------------------------------+ |
| 429 | | ``Diagram Elements`` | DF2 | |
| 430 | +------------------------+---------------------------------------------------+ |
| 431 | | ``Affected TF-A | BL1, BL2, BL31 | |
| 432 | | Components`` | | |
| 433 | +------------------------+---------------------------------------------------+ |
| 434 | | ``Assets`` | Sensitive Data | |
| 435 | +------------------------+---------------------------------------------------+ |
| 436 | | ``Threat Agent`` | AppDebug | |
| 437 | +------------------------+---------------------------------------------------+ |
| 438 | | ``Threat Type`` | Information Disclosure | |
| 439 | +------------------------+------------------+----------------+---------------+ |
| 440 | | ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | |
| 441 | +------------------------+------------------+----------------+---------------+ |
| 442 | | ``Impact`` | N/A | Low (2) | Low (2) | |
| 443 | +------------------------+------------------+----------------+---------------+ |
| 444 | | ``Likelihood`` | N/A | High (4) | High (4) | |
| 445 | +------------------------+------------------+----------------+---------------+ |
| 446 | | ``Total Risk Rating`` | N/A | Medium (8) | Medium (8) | |
| 447 | +------------------------+------------------+----------------+---------------+ |
| 448 | | ``Mitigations`` | | In TF-A, crash reporting is only enabled for | |
| 449 | | | debug builds by default. Alternatively, the log | |
| 450 | | | level can be tuned at build time (from verbose | |
| 451 | | | to no output at all), independently of the | |
| 452 | | | build type. | |
| 453 | +------------------------+---------------------------------------------------+ |
| 454 | |
| 455 | +------------------------+----------------------------------------------------+ |
| 456 | | ID | 06 | |
| 457 | +========================+====================================================+ |
| 458 | | ``Threat`` | | **An attacker can read sensitive data and | |
| 459 | | | execute arbitrary code through the external | |
| 460 | | | debug and trace interface** | |
| 461 | | | | |
| 462 | | | | Arm processors include hardware-assisted debug | |
| 463 | | | and trace features that can be controlled without| |
| 464 | | | the need for software operating on the platform. | |
| 465 | | | If left enabled without authentication, this | |
| 466 | | | feature can be used by an attacker to inspect and| |
| 467 | | | modify TF-A registers and memory allowing the | |
| 468 | | | attacker to read sensitive data and execute | |
| 469 | | | arbitrary code. | |
| 470 | +------------------------+----------------------------------------------------+ |
| 471 | | ``Diagram Elements`` | DF3 | |
| 472 | +------------------------+----------------------------------------------------+ |
| 473 | | ``Affected TF-A | BL1, BL2, BL31 | |
| 474 | | Components`` | | |
| 475 | +------------------------+----------------------------------------------------+ |
| 476 | | ``Assets`` | Code Execution, Sensitive Data | |
| 477 | +------------------------+----------------------------------------------------+ |
| 478 | | ``Threat Agent`` | AppDebug | |
| 479 | +------------------------+----------------------------------------------------+ |
| 480 | | ``Threat Type`` | Tampering, Information Disclosure, | |
| 481 | | | Elevation of privilege | |
| 482 | +------------------------+------------------+---------------+-----------------+ |
| 483 | | ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | |
| 484 | +------------------------+------------------+---------------+-----------------+ |
| 485 | | ``Impact`` | N/A | High (4) | High (4) | |
| 486 | +------------------------+------------------+---------------+-----------------+ |
| 487 | | ``Likelihood`` | N/A | Critical (5) | Critical (5) | |
| 488 | +------------------------+------------------+---------------+-----------------+ |
| 489 | | ``Total Risk Rating`` | N/A | Critical (20) | Critical (20) | |
| 490 | +------------------------+------------------+---------------+-----------------+ |
| 491 | | ``Mitigations`` | | Configuration of debug and trace capabilities is | |
| 492 | | | platform specific. Therefore, platforms must | |
| 493 | | | disable the debug and trace capability for | |
| 494 | | | production releases or enable proper debug | |
| 495 | | | authentication as recommended by [`DEN0034`_]. | |
| 496 | +------------------------+----------------------------------------------------+ |
| 497 | |
| 498 | +------------------------+------------------------------------------------------+ |
| 499 | | ID | 07 | |
| 500 | +========================+======================================================+ |
| 501 | | ``Threat`` | | **An attacker can perform a denial-of-service | |
| 502 | | | attack by using a broken SMC call that causes the | |
| 503 | | | system to reboot or enter into unknown state.** | |
| 504 | | | | |
| 505 | | | | Secure and non-secure clients access TF-A services | |
| 506 | | | through SMC calls. Malicious code can attempt to | |
| 507 | | | place the TF-A runtime into an inconsistent state | |
| 508 | | | by calling unimplemented SMC call or by passing | |
| 509 | | | invalid arguments. | |
| 510 | +------------------------+------------------------------------------------------+ |
| 511 | | ``Diagram Elements`` | DF4, DF5 | |
| 512 | +------------------------+------------------------------------------------------+ |
| 513 | | ``Affected TF-A | BL31 | |
| 514 | | Components`` | | |
| 515 | +------------------------+------------------------------------------------------+ |
| 516 | | ``Assets`` | Availability | |
| 517 | +------------------------+------------------------------------------------------+ |
| 518 | | ``Threat Agent`` | NSCode, SecCode | |
| 519 | +------------------------+------------------------------------------------------+ |
| 520 | | ``Threat Type`` | Denial of Service | |
| 521 | +------------------------+-------------------+----------------+-----------------+ |
| 522 | | ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | |
| 523 | +------------------------+-------------------+----------------+-----------------+ |
| 524 | | ``Impact`` | Medium (3) | Medium (3) | Medium (3) | |
| 525 | +------------------------+-------------------+----------------+-----------------+ |
| 526 | | ``Likelihood`` | High (4) | High (4) | High (4) | |
| 527 | +------------------------+-------------------+----------------+-----------------+ |
| 528 | | ``Total Risk Rating`` | High (12) | High (12) | High (12) | |
| 529 | +------------------------+-------------------+----------------+-----------------+ |
| 530 | | ``Mitigations`` | | The generic TF-A code validates SMC function ids | |
| 531 | | | and arguments before using them. | |
| 532 | | | Platforms that implement SiP services must also | |
| 533 | | | validate SMC call arguments. | |
| 534 | +------------------------+------------------------------------------------------+ |
| 535 | |
| 536 | +------------------------+------------------------------------------------------+ |
| 537 | | ID | 08 | |
| 538 | +========================+======================================================+ |
| 539 | | ``Threat`` | | **Memory corruption due to memory overflows and | |
| 540 | | | lack of boundary checking when accessing resources | |
| 541 | | | could allow an attacker to execute arbitrary code, | |
| 542 | | | modify some state variable to change the normal | |
| 543 | | | flow of the program, or leak sensitive | |
| 544 | | | information** | |
| 545 | | | | |
| 546 | | | | Like in other software, the Trusted Firmware has | |
| 547 | | | multiple points where memory corruption security | |
| 548 | | | errors can arise. Memory corruption is a dangerous | |
| 549 | | | security issue since it could allow an attacker | |
| 550 | | | to execute arbitrary code, modify some state | |
| 551 | | | variable to change the normal flow of the program, | |
| 552 | | | or leak sensitive information. | |
| 553 | | | | |
| 554 | | | | Some of the errors include integer overflow, | |
| 555 | | | buffer overflow, incorrect array boundary checks, | |
| 556 | | | and incorrect error management. | |
| 557 | | | Improper use of asserts instead of proper input | |
| 558 | | | validations might also result in these kinds of | |
| 559 | | | errors in release builds. | |
| 560 | +------------------------+------------------------------------------------------+ |
| 561 | | ``Diagram Elements`` | DF4, DF5 | |
| 562 | +------------------------+------------------------------------------------------+ |
| 563 | | ``Affected TF-A | BL1, BL2, BL31 | |
| 564 | | Components`` | | |
| 565 | +------------------------+------------------------------------------------------+ |
| 566 | | ``Assets`` | Code Execution, Sensitive Data | |
| 567 | +------------------------+------------------------------------------------------+ |
| 568 | | ``Threat Agent`` | NSCode, SecCode | |
| 569 | +------------------------+------------------------------------------------------+ |
| 570 | | ``Threat Type`` | Tampering, Information Disclosure, | |
| 571 | | | Elevation of Privilege | |
| 572 | +------------------------+-------------------+-----------------+----------------+ |
| 573 | | ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | |
| 574 | +------------------------+-------------------+-----------------+----------------+ |
| 575 | | ``Impact`` | Critical (5) | Critical (5) | Critical (5) | |
| 576 | +------------------------+-------------------+-----------------+----------------+ |
| 577 | | ``Likelihood`` | Medium (3 | Medium (3) | Medium (3) | |
| 578 | +------------------------+-------------------+-----------------+----------------+ |
| 579 | | ``Total Risk Rating`` | High (15) | High (15) | High (15) | |
| 580 | +------------------------+-------------------+-----------------+----------------+ |
| 581 | | ``Mitigations`` | | TF-A uses a combination of manual code reviews and | |
| 582 | | | automated program analysis and testing to detect | |
| 583 | | | and fix memory corruption bugs. All TF-A code | |
| 584 | | | including platform code go through manual code | |
| 585 | | | reviews. Additionally, static code analysis is | |
| 586 | | | performed using Coverity Scan on all TF-A code. | |
| 587 | | | The code is also tested with | |
| 588 | | | `Trusted Firmware-A Tests`_ on Juno and FVP | |
| 589 | | | platforms. | |
| 590 | | | | |
| 591 | | | | Data received from normal world, such as addresses | |
| 592 | | | and sizes identifying memory regions, are | |
| 593 | | | sanitized before being used. These security checks | |
| 594 | | | make sure that the normal world software does not | |
| 595 | | | access memory beyond its limit. | |
| 596 | | | | |
| 597 | | | | By default *asserts* are only used to check for | |
| 598 | | | programming errors in debug builds. Other types of | |
| 599 | | | errors are handled through condition checks that | |
| 600 | | | remain enabled in release builds. See | |
| 601 | | | `TF-A error handling policy`_. TF-A provides an | |
| 602 | | | option to use *asserts* in release builds, however | |
| 603 | | | we recommend using proper runtime checks instead | |
| 604 | | | of relying on asserts in release builds. | |
| 605 | +------------------------+------------------------------------------------------+ |
| 606 | |
| 607 | +------------------------+------------------------------------------------------+ |
| 608 | | ID | 09 | |
| 609 | +========================+======================================================+ |
| 610 | | ``Threat`` | | **Improperly handled SMC calls can leak register | |
| 611 | | | contents** | |
| 612 | | | | |
| 613 | | | | When switching between secure and non-secure | |
| 614 | | | states, register contents of Secure world or | |
| 615 | | | register contents of other normal world clients | |
| 616 | | | can be leaked. | |
| 617 | +------------------------+------------------------------------------------------+ |
| 618 | | ``Diagram Elements`` | DF5 | |
| 619 | +------------------------+------------------------------------------------------+ |
| 620 | | ``Affected TF-A | BL31 | |
| 621 | | Components`` | | |
| 622 | +------------------------+------------------------------------------------------+ |
| 623 | | ``Assets`` | Sensitive Data | |
| 624 | +------------------------+------------------------------------------------------+ |
| 625 | | ``Threat Agent`` | NSCode | |
| 626 | +------------------------+------------------------------------------------------+ |
| 627 | | ``Threat Type`` | Information Disclosure | |
| 628 | +------------------------+-------------------+----------------+-----------------+ |
| 629 | | ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | |
| 630 | +------------------------+-------------------+----------------+-----------------+ |
| 631 | | ``Impact`` | Medium (3) | Medium (3) | Medium (3) | |
| 632 | +------------------------+-------------------+----------------+-----------------+ |
| 633 | | ``Likelihood`` | High (4) | High (4) | High (4) | |
| 634 | +------------------------+-------------------+----------------+-----------------+ |
| 635 | | ``Total Risk Rating`` | High (12) | High (12) | High (12) | |
| 636 | +------------------------+-------------------+----------------+-----------------+ |
| 637 | | ``Mitigations`` | | TF-A saves and restores registers | |
| 638 | | | by default when switching contexts. Build options | |
| 639 | | | are also provided to save/restore additional | |
| 640 | | | registers such as floating-point registers. | |
| 641 | +------------------------+------------------------------------------------------+ |
| 642 | |
| 643 | +------------------------+-----------------------------------------------------+ |
| 644 | | ID | 10 | |
| 645 | +========================+=====================================================+ |
| 646 | | ``Threat`` | | **SMC calls can leak sensitive information from | |
| 647 | | | TF-A memory via microarchitectural side channels**| |
| 648 | | | | |
| 649 | | | | Microarchitectural side-channel attacks such as | |
| 650 | | | `Spectre`_ can be used to leak data across | |
| 651 | | | security boundaries. An attacker might attempt to | |
| 652 | | | use this kind of attack to leak sensitive | |
| 653 | | | data from TF-A memory. | |
| 654 | +------------------------+-----------------------------------------------------+ |
| 655 | | ``Diagram Elements`` | DF4, DF5 | |
| 656 | +------------------------+-----------------------------------------------------+ |
| 657 | | ``Affected TF-A | BL31 | |
| 658 | | Components`` | | |
| 659 | +------------------------+-----------------------------------------------------+ |
| 660 | | ``Assets`` | Sensitive Data | |
| 661 | +------------------------+-----------------------------------------------------+ |
| 662 | | ``Threat Agent`` | SecCode, NSCode | |
| 663 | +------------------------+-----------------------------------------------------+ |
| 664 | | ``Threat Type`` | Information Disclosure | |
| 665 | +------------------------+-------------------+----------------+----------------+ |
| 666 | | ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | |
| 667 | +------------------------+-------------------+----------------+----------------+ |
| 668 | | ``Impact`` | Medium (3) | Medium (3) | Medium (3) | |
| 669 | +------------------------+-------------------+----------------+----------------+ |
| 670 | | ``Likelihood`` | Medium (3) | Medium (3) | Medium (3) | |
| 671 | +------------------------+-------------------+----------------+----------------+ |
| 672 | | ``Total Risk Rating`` | Medium (9) | Medium (9) | Medium (9) | |
| 673 | +------------------------+-------------------+----------------+----------------+ |
| 674 | | ``Mitigations`` | | TF-A implements software mitigations for Spectre | |
| 675 | | | type attacks as recommended by `Cache Speculation | |
| 676 | | | Side-channels`_ for the generic code. SiPs should | |
| 677 | | | implement similar mitigations for code that is | |
| 678 | | | deemed to be vulnerable to such attacks. | |
| 679 | +------------------------+-----------------------------------------------------+ |
| 680 | |
| 681 | +------------------------+----------------------------------------------------+ |
| 682 | | ID | 11 | |
| 683 | +========================+====================================================+ |
| 684 | | ``Threat`` | | **Misconfiguration of the Memory Management Unit | |
| 685 | | | (MMU) may allow a normal world software to | |
| 686 | | | access sensitive data or execute arbitrary | |
| 687 | | | code** | |
| 688 | | | | |
| 689 | | | | A misconfiguration of the MMU could | |
| 690 | | | lead to an open door for software running in the | |
| 691 | | | normal world to access sensitive data or even | |
| 692 | | | execute code if the proper security mechanisms | |
| 693 | | | are not in place. | |
| 694 | +------------------------+----------------------------------------------------+ |
| 695 | | ``Diagram Elements`` | DF5, DF6 | |
| 696 | +------------------------+----------------------------------------------------+ |
| 697 | | ``Affected TF-A | BL1, BL2, BL31 | |
| 698 | | Components`` | | |
| 699 | +------------------------+----------------------------------------------------+ |
| 700 | | ``Assets`` | Sensitive Data, Code execution | |
| 701 | +------------------------+----------------------------------------------------+ |
| 702 | | ``Threat Agent`` | NSCode | |
| 703 | +------------------------+----------------------------------------------------+ |
| 704 | | ``Threat Type`` | Information Disclosure, Elevation of Privilege | |
| 705 | +------------------------+-----------------+-----------------+----------------+ |
| 706 | | ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | |
| 707 | +------------------------+-----------------+-----------------+----------------+ |
| 708 | | ``Impact`` | Critical (5) | Critical (5) | Critical (5) | |
| 709 | +------------------------+-----------------+-----------------+----------------+ |
| 710 | | ``Likelihood`` | High (4) | High (4) | High (4) | |
| 711 | +------------------------+-----------------+-----------------+----------------+ |
| 712 | | ``Total Risk Rating`` | Critical (20) | Critical (20) | Critical (20) | |
| 713 | +------------------------+-----------------+-----------------+----------------+ |
| 714 | | ``Mitigations`` | | In TF-A, configuration of the MMU is done | |
| 715 | | | through a translation tables library. The | |
| 716 | | | library provides APIs to define memory regions | |
| 717 | | | and assign attributes including memory types and | |
| 718 | | | access permissions. Memory configurations are | |
| 719 | | | platform specific, therefore platforms need make | |
| 720 | | | sure the correct attributes are assigned to | |
| 721 | | | memory regions. When assigning access | |
| 722 | | | permissions, principle of least privilege ought | |
| 723 | | | to be enforced, i.e. we should not grant more | |
| 724 | | | privileges than strictly needed, e.g. code | |
| 725 | | | should be read-only executable, RO data should | |
| 726 | | | be read-only XN, and so on. | |
| 727 | +------------------------+----------------------------------------------------+ |
| 728 | |
| 729 | +------------------------+-----------------------------------------------------+ |
| 730 | | ID | 12 | |
| 731 | +========================+=====================================================+ |
| 732 | | ``Threat`` | | **Incorrect configuration of Performance Monitor | |
| 733 | | | Unit (PMU) counters can allow an attacker to | |
| 734 | | | mount side-channel attacks using information | |
| 735 | | | exposed by the counters** | |
| 736 | | | | |
| 737 | | | | Non-secure software can configure PMU registers | |
| 738 | | | to count events at any exception level and in | |
| 739 | | | both Secure and Non-secure states. This allows | |
| 740 | | | a Non-secure software (or a lower-level Secure | |
| 741 | | | software) to potentially carry out | |
| 742 | | | side-channel timing attacks against TF-A. | |
| 743 | +------------------------+-----------------------------------------------------+ |
| 744 | | ``Diagram Elements`` | DF5, DF6 | |
| 745 | +------------------------+-----------------------------------------------------+ |
| 746 | | ``Affected TF-A | BL31 | |
| 747 | | Components`` | | |
| 748 | +------------------------+-----------------------------------------------------+ |
| 749 | | ``Assets`` | Sensitive Data | |
| 750 | +------------------------+-----------------------------------------------------+ |
| 751 | | ``Threat Agent`` | NSCode | |
| 752 | +------------------------+-----------------------------------------------------+ |
| 753 | | ``Threat Type`` | Information Disclosure | |
| 754 | +------------------------+-------------------+----------------+----------------+ |
| 755 | | ``Impact`` | Medium (3) | Medium (3) | Medium (3) | |
| 756 | +------------------------+-------------------+----------------+----------------+ |
| 757 | | ``Likelihood`` | Low (2) | Low (2) | Low (2) | |
| 758 | +------------------------+-------------------+----------------+----------------+ |
| 759 | | ``Total Risk Rating`` | Medium (6) | Medium (6) | Medium (6) | |
| 760 | +------------------------+-------------------+----------------+----------------+ |
| 761 | | ``Mitigations`` | | TF-A follows mitigation strategies as described | |
| 762 | | | in `Secure Development Guidelines`_. General | |
| 763 | | | events and cycle counting in the Secure world is | |
| 764 | | | prohibited by default when applicable. However, | |
| 765 | | | on some implementations (e.g. PMUv3) Secure world | |
| 766 | | | event counting depends on external debug interface| |
| 767 | | | signals, i.e. Secure world event counting is | |
| 768 | | | enabled if external debug is enabled. | |
| 769 | | | Configuration of debug signals is platform | |
| 770 | | | specific, therefore platforms need to make sure | |
| 771 | | | that external debug is disabled in production or | |
| 772 | | | proper debug authentication is in place. | |
| 773 | +------------------------+-----------------------------------------------------+ |
| 774 | |
| 775 | -------------- |
| 776 | |
| 777 | *Copyright (c) 2021, Arm Limited. All rights reserved.* |
| 778 | |
| 779 | |
| 780 | .. _STRIDE threat analysis technique: https://docs.microsoft.com/en-us/azure/security/develop/threat-modeling-tool-threats#stride-model |
| 781 | .. _DEN0034: https://developer.arm.com/documentation/den0034/latest |
| 782 | .. _Cache Speculation Side-channels: https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability |
| 783 | .. _Spectre: https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability |
| 784 | .. _TBBR-Client specification: https://developer.arm.com/documentation/den0006/d/ |
| 785 | .. _Trusted Board Boot (TBB): https://trustedfirmware-a.readthedocs.io/en/latest/design/trusted-board-boot.html |
| 786 | .. _TF-A error handling policy: https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#error-handling-and-robustness |
| 787 | .. _Secure Development Guidelines: https://trustedfirmware-a.readthedocs.io/en/latest/process/security-hardening.html#secure-development-guidelines |
Olivier Deprez | 86d1ffd | 2021-06-01 15:37:16 +0200 | [diff] [blame] | 788 | .. _Trusted Firmware-A Tests: https://git.trustedfirmware.org/TF-A/tf-a-tests.git/about/ |