Rex-BC Chen | abd9ecf | 2021-10-06 19:25:50 +0800 | [diff] [blame] | 1 | /* |
jason-ch chen | a07e3ea | 2021-11-16 10:18:46 +0800 | [diff] [blame] | 2 | * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved. |
Rex-BC Chen | abd9ecf | 2021-10-06 19:25:50 +0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <common/debug.h> |
| 8 | #include <common/runtime_svc.h> |
jason-ch chen | a07e3ea | 2021-11-16 10:18:46 +0800 | [diff] [blame] | 9 | #include <mt_spm_vcorefs.h> |
| 10 | #include <mtk_sip_svc.h> |
Rex-BC Chen | 1782ce9 | 2021-12-02 14:03:44 +0800 | [diff] [blame] | 11 | #include <plat_dfd.h> |
jason-ch chen | a07e3ea | 2021-11-16 10:18:46 +0800 | [diff] [blame] | 12 | #include "plat_sip_calls.h" |
Rex-BC Chen | abd9ecf | 2021-10-06 19:25:50 +0800 | [diff] [blame] | 13 | |
| 14 | uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid, |
| 15 | u_register_t x1, |
| 16 | u_register_t x2, |
| 17 | u_register_t x3, |
| 18 | u_register_t x4, |
| 19 | void *cookie, |
| 20 | void *handle, |
| 21 | u_register_t flags) |
| 22 | { |
jason-ch chen | a07e3ea | 2021-11-16 10:18:46 +0800 | [diff] [blame] | 23 | uint64_t ret; |
| 24 | |
Rex-BC Chen | abd9ecf | 2021-10-06 19:25:50 +0800 | [diff] [blame] | 25 | switch (smc_fid) { |
jason-ch chen | a07e3ea | 2021-11-16 10:18:46 +0800 | [diff] [blame] | 26 | case MTK_SIP_VCORE_CONTROL_ARCH32: |
| 27 | case MTK_SIP_VCORE_CONTROL_ARCH64: |
| 28 | ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4); |
| 29 | SMC_RET2(handle, ret, x4); |
| 30 | break; |
Rex-BC Chen | 1782ce9 | 2021-12-02 14:03:44 +0800 | [diff] [blame] | 31 | case MTK_SIP_KERNEL_DFD_AARCH32: |
| 32 | case MTK_SIP_KERNEL_DFD_AARCH64: |
| 33 | ret = dfd_smc_dispatcher(x1, x2, x3, x4); |
| 34 | SMC_RET1(handle, ret); |
| 35 | break; |
Rex-BC Chen | abd9ecf | 2021-10-06 19:25:50 +0800 | [diff] [blame] | 36 | default: |
| 37 | ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); |
| 38 | break; |
| 39 | } |
| 40 | |
| 41 | SMC_RET1(handle, SMC_UNK); |
| 42 | } |