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git01.mediatek.com / filogic / atf / 686ecbd51064cb162fb76ae291a8fcbb83d32eb2 / . / plat / mediatek / mt8173 / drivers / pmic / pmic_wrap_init.h
blob: 0b20500544ec200b1014b98e61404faeb7fb7818 [file] [log] [blame]
developer65014b82015-04-13 14:47:57 +0800[diff] [blame]1/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __PMIC_WRAP_INIT_H__
32#define __PMIC_WRAP_INIT_H__
33
34/* external API */
35int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
36int32_t pwrap_write(uint32_t adr, uint32_t wdata);
37
38static struct mt8173_pmic_wrap_regs *const mt8173_pwrap =
39 (void *)PMIC_WRAP_BASE;
40
41/* timeout setting */
42enum {
43 TIMEOUT_RESET = 50, /* us */
44 TIMEOUT_READ = 50, /* us */
45 TIMEOUT_WAIT_IDLE = 50 /* us */
46};
47
48/* PMIC_WRAP registers */
49struct mt8173_pmic_wrap_regs {
50 uint32_t mux_sel;
51 uint32_t wrap_en;
52 uint32_t dio_en;
53 uint32_t sidly;
54 uint32_t rddmy;
55 uint32_t si_ck_con;
56 uint32_t cshext_write;
57 uint32_t cshext_read;
58 uint32_t cslext_start;
59 uint32_t cslext_end;
60 uint32_t staupd_prd;
61 uint32_t staupd_grpen;
62 uint32_t reserved[4];
63 uint32_t staupd_man_trig;
64 uint32_t staupd_sta;
65 uint32_t wrap_sta;
66 uint32_t harb_init;
67 uint32_t harb_hprio;
68 uint32_t hiprio_arb_en;
69 uint32_t harb_sta0;
70 uint32_t harb_sta1;
71 uint32_t man_en;
72 uint32_t man_cmd;
73 uint32_t man_rdata;
74 uint32_t man_vldclr;
75 uint32_t wacs0_en;
76 uint32_t init_done0;
77 uint32_t wacs0_cmd;
78 uint32_t wacs0_rdata;
79 uint32_t wacs0_vldclr;
80 uint32_t wacs1_en;
81 uint32_t init_done1;
82 uint32_t wacs1_cmd;
83 uint32_t wacs1_rdata;
84 uint32_t wacs1_vldclr;
85 uint32_t wacs2_en;
86 uint32_t init_done2;
87 uint32_t wacs2_cmd;
88 uint32_t wacs2_rdata;
89 uint32_t wacs2_vldclr;
90 uint32_t int_en;
91 uint32_t int_flg_raw;
92 uint32_t int_flg;
93 uint32_t int_clr;
94 uint32_t sig_adr;
95 uint32_t sig_mode;
96 uint32_t sig_value;
97 uint32_t sig_errval;
98 uint32_t crc_en;
99 uint32_t timer_en;
100 uint32_t timer_sta;
101 uint32_t wdt_unit;
102 uint32_t wdt_src_en;
103 uint32_t wdt_flg;
104 uint32_t debug_int_sel;
105 uint32_t dvfs_adr0;
106 uint32_t dvfs_wdata0;
107 uint32_t dvfs_adr1;
108 uint32_t dvfs_wdata1;
109 uint32_t dvfs_adr2;
110 uint32_t dvfs_wdata2;
111 uint32_t dvfs_adr3;
112 uint32_t dvfs_wdata3;
113 uint32_t dvfs_adr4;
114 uint32_t dvfs_wdata4;
115 uint32_t dvfs_adr5;
116 uint32_t dvfs_wdata5;
117 uint32_t dvfs_adr6;
118 uint32_t dvfs_wdata6;
119 uint32_t dvfs_adr7;
120 uint32_t dvfs_wdata7;
121 uint32_t spminf_sta;
122 uint32_t cipher_key_sel;
123 uint32_t cipher_iv_sel;
124 uint32_t cipher_en;
125 uint32_t cipher_rdy;
126 uint32_t cipher_mode;
127 uint32_t cipher_swrst;
128 uint32_t dcm_en;
129 uint32_t dcm_dbc_prd;
130};
131
132enum {
133 RDATA_WACS_RDATA_SHIFT = 0,
134 RDATA_WACS_FSM_SHIFT = 16,
135 RDATA_WACS_REQ_SHIFT = 19,
136 RDATA_SYNC_IDLE_SHIFT,
137 RDATA_INIT_DONE_SHIFT,
138 RDATA_SYS_IDLE_SHIFT,
139};
140
141enum {
142 RDATA_WACS_RDATA_MASK = 0xffff,
143 RDATA_WACS_FSM_MASK = 0x7,
144 RDATA_WACS_REQ_MASK = 0x1,
145 RDATA_SYNC_IDLE_MASK = 0x1,
146 RDATA_INIT_DONE_MASK = 0x1,
147 RDATA_SYS_IDLE_MASK = 0x1,
148};
149
150/* WACS_FSM */
151enum {
152 WACS_FSM_IDLE = 0x00,
153 WACS_FSM_REQ = 0x02,
154 WACS_FSM_WFDLE = 0x04,
155 WACS_FSM_WFVLDCLR = 0x06,
156 WACS_INIT_DONE = 0x01,
157 WACS_SYNC_IDLE = 0x01,
158 WACS_SYNC_BUSY = 0x00
159};
160
161/* error information flag */
162enum {
163 E_PWR_INVALID_ARG = 1,
164 E_PWR_INVALID_RW = 2,
165 E_PWR_INVALID_ADDR = 3,
166 E_PWR_INVALID_WDAT = 4,
167 E_PWR_INVALID_OP_MANUAL = 5,
168 E_PWR_NOT_IDLE_STATE = 6,
169 E_PWR_NOT_INIT_DONE = 7,
170 E_PWR_NOT_INIT_DONE_READ = 8,
171 E_PWR_WAIT_IDLE_TIMEOUT = 9,
172 E_PWR_WAIT_IDLE_TIMEOUT_READ = 10,
173 E_PWR_INIT_SIDLY_FAIL = 11,
174 E_PWR_RESET_TIMEOUT = 12,
175 E_PWR_TIMEOUT = 13,
176 E_PWR_INIT_RESET_SPI = 20,
177 E_PWR_INIT_SIDLY = 21,
178 E_PWR_INIT_REG_CLOCK = 22,
179 E_PWR_INIT_ENABLE_PMIC = 23,
180 E_PWR_INIT_DIO = 24,
181 E_PWR_INIT_CIPHER = 25,
182 E_PWR_INIT_WRITE_TEST = 26,
183 E_PWR_INIT_ENABLE_CRC = 27,
184 E_PWR_INIT_ENABLE_DEWRAP = 28,
185 E_PWR_INIT_ENABLE_EVENT = 29,
186 E_PWR_READ_TEST_FAIL = 30,
187 E_PWR_WRITE_TEST_FAIL = 31,
188 E_PWR_SWITCH_DIO = 32
189};
190
191#endif /* __PMIC_WRAP_INIT_H__ */