blob: 5c20932ebd533a3fd9524882eec7b3eb0a23fb85 [file] [log] [blame]
Haojian Zhuang20cd3232017-05-31 11:00:15 +08001/*
Wing Lib7e93082021-12-23 11:32:08 -08002 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
Haojian Zhuang20cd3232017-05-31 11:00:15 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Haojian Zhuang20cd3232017-05-31 11:00:15 +08007#include <assert.h>
Haojian Zhuang20cd3232017-05-31 11:00:15 +08008#include <endian.h>
9#include <errno.h>
Haojian Zhuang20cd3232017-05-31 11:00:15 +080010#include <stdint.h>
11#include <string.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012
13#include <platform_def.h>
14
15#include <arch_helpers.h>
16#include <common/debug.h>
17#include <drivers/delay_timer.h>
18#include <drivers/ufs.h>
19#include <lib/mmio.h>
Haojian Zhuang20cd3232017-05-31 11:00:15 +080020
21#define CDB_ADDR_MASK 127
22#define ALIGN_CDB(x) (((x) + CDB_ADDR_MASK) & ~CDB_ADDR_MASK)
23#define ALIGN_8(x) (((x) + 7) & ~7)
24
25#define UFS_DESC_SIZE 0x400
26#define MAX_UFS_DESC_SIZE 0x8000 /* 32 descriptors */
27
28#define MAX_PRDT_SIZE 0x40000 /* 256KB */
29
30static ufs_params_t ufs_params;
31static int nutrs; /* Number of UTP Transfer Request Slots */
32
33int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd)
34{
35 unsigned int data;
36
Jorge Troncoso453e5e72021-09-23 17:14:29 -070037 if (base == 0 || cmd == NULL)
38 return -EINVAL;
39
Haojian Zhuang20cd3232017-05-31 11:00:15 +080040 data = mmio_read_32(base + HCS);
41 if ((data & HCS_UCRDY) == 0)
42 return -EBUSY;
43 mmio_write_32(base + IS, ~0);
44 mmio_write_32(base + UCMDARG1, cmd->arg1);
45 mmio_write_32(base + UCMDARG2, cmd->arg2);
46 mmio_write_32(base + UCMDARG3, cmd->arg3);
47 mmio_write_32(base + UICCMD, cmd->op);
48
49 do {
50 data = mmio_read_32(base + IS);
51 } while ((data & UFS_INT_UCCS) == 0);
52 mmio_write_32(base + IS, UFS_INT_UCCS);
Haojian Zhuang836eadc2017-06-12 22:18:15 +080053 return mmio_read_32(base + UCMDARG2) & CONFIG_RESULT_CODE_MASK;
Haojian Zhuang20cd3232017-05-31 11:00:15 +080054}
55
56int ufshc_dme_get(unsigned int attr, unsigned int idx, unsigned int *val)
57{
58 uintptr_t base;
59 unsigned int data;
Jorge Troncoso453e5e72021-09-23 17:14:29 -070060 int result, retries;
61 uic_cmd_t cmd;
Haojian Zhuang20cd3232017-05-31 11:00:15 +080062
Jorge Troncoso453e5e72021-09-23 17:14:29 -070063 assert(ufs_params.reg_base != 0);
64
65 if (val == NULL)
66 return -EINVAL;
Haojian Zhuang20cd3232017-05-31 11:00:15 +080067
68 base = ufs_params.reg_base;
69 for (retries = 0; retries < 100; retries++) {
70 data = mmio_read_32(base + HCS);
71 if ((data & HCS_UCRDY) != 0)
72 break;
73 mdelay(1);
74 }
75 if (retries >= 100)
76 return -EBUSY;
77
Jorge Troncoso453e5e72021-09-23 17:14:29 -070078 cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx);
79 cmd.arg2 = 0;
80 cmd.arg3 = 0;
81 cmd.op = DME_GET;
82 for (retries = 0; retries < UFS_UIC_COMMAND_RETRIES; ++retries) {
83 result = ufshc_send_uic_cmd(base, &cmd);
84 if (result == 0)
85 break;
Haojian Zhuang20cd3232017-05-31 11:00:15 +080086 data = mmio_read_32(base + IS);
87 if (data & UFS_INT_UE)
88 return -EINVAL;
Jorge Troncoso453e5e72021-09-23 17:14:29 -070089 }
90 if (retries >= UFS_UIC_COMMAND_RETRIES)
91 return -EIO;
Haojian Zhuang20cd3232017-05-31 11:00:15 +080092
93 *val = mmio_read_32(base + UCMDARG3);
94 return 0;
95}
96
97int ufshc_dme_set(unsigned int attr, unsigned int idx, unsigned int val)
98{
99 uintptr_t base;
100 unsigned int data;
Jorge Troncoso453e5e72021-09-23 17:14:29 -0700101 int result, retries;
102 uic_cmd_t cmd;
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800103
104 assert((ufs_params.reg_base != 0));
105
106 base = ufs_params.reg_base;
Jorge Troncoso453e5e72021-09-23 17:14:29 -0700107 cmd.arg1 = (attr << 16) | GEN_SELECTOR_IDX(idx);
108 cmd.arg2 = 0;
109 cmd.arg3 = val;
110 cmd.op = DME_SET;
111
112 for (retries = 0; retries < UFS_UIC_COMMAND_RETRIES; ++retries) {
113 result = ufshc_send_uic_cmd(base, &cmd);
114 if (result == 0)
115 break;
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800116 data = mmio_read_32(base + IS);
117 if (data & UFS_INT_UE)
118 return -EINVAL;
Jorge Troncoso453e5e72021-09-23 17:14:29 -0700119 }
120 if (retries >= UFS_UIC_COMMAND_RETRIES)
121 return -EIO;
122
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800123 return 0;
124}
125
Jorge Troncoso5f449162021-09-30 16:29:32 -0700126static int ufshc_hce_enable(uintptr_t base)
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800127{
128 unsigned int data;
Jorge Troncoso5f449162021-09-30 16:29:32 -0700129 int retries;
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800130
131 /* Enable Host Controller */
132 mmio_write_32(base + HCE, HCE_ENABLE);
Jorge Troncoso5f449162021-09-30 16:29:32 -0700133
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800134 /* Wait until basic initialization sequence completed */
Jorge Troncoso5f449162021-09-30 16:29:32 -0700135 for (retries = 0; retries < HCE_ENABLE_INNER_RETRIES; ++retries) {
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800136 data = mmio_read_32(base + HCE);
Jorge Troncoso5f449162021-09-30 16:29:32 -0700137 if (data & HCE_ENABLE) {
138 break;
139 }
140 udelay(HCE_ENABLE_TIMEOUT_US);
141 }
142 if (retries >= HCE_ENABLE_INNER_RETRIES) {
143 return -ETIMEDOUT;
144 }
145
146 return 0;
147}
148
149static int ufshc_reset(uintptr_t base)
150{
151 unsigned int data;
152 int retries, result;
153
154 for (retries = 0; retries < HCE_ENABLE_OUTER_RETRIES; ++retries) {
155 result = ufshc_hce_enable(base);
156 if (result == 0) {
157 break;
158 }
159 }
160 if (retries >= HCE_ENABLE_OUTER_RETRIES) {
161 return -EIO;
162 }
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800163
164 /* Enable Interrupts */
165 data = UFS_INT_UCCS | UFS_INT_ULSS | UFS_INT_UE | UFS_INT_UTPES |
166 UFS_INT_DFES | UFS_INT_HCFES | UFS_INT_SBFES;
167 mmio_write_32(base + IE, data);
Jorge Troncoso5f449162021-09-30 16:29:32 -0700168
169 return 0;
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800170}
171
Jorge Troncoso63d7c162021-10-05 22:46:35 -0700172static int ufshc_dme_link_startup(uintptr_t base)
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800173{
174 uic_cmd_t cmd;
Jorge Troncoso63d7c162021-10-05 22:46:35 -0700175
176 memset(&cmd, 0, sizeof(cmd));
177 cmd.op = DME_LINKSTARTUP;
178 return ufshc_send_uic_cmd(base, &cmd);
179}
180
181static int ufshc_link_startup(uintptr_t base)
182{
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800183 int data, result;
184 int retries;
185
Jorge Troncoso63d7c162021-10-05 22:46:35 -0700186 for (retries = DME_LINKSTARTUP_RETRIES; retries > 0; retries--) {
187 result = ufshc_dme_link_startup(base);
188 if (result != 0) {
189 /* Reset controller before trying again */
190 result = ufshc_reset(base);
191 if (result != 0) {
192 return result;
193 }
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800194 continue;
Jorge Troncoso63d7c162021-10-05 22:46:35 -0700195 }
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800196 while ((mmio_read_32(base + HCS) & HCS_DP) == 0)
197 ;
198 data = mmio_read_32(base + IS);
199 if (data & UFS_INT_ULSS)
200 mmio_write_32(base + IS, UFS_INT_ULSS);
201 return 0;
202 }
203 return -EIO;
204}
205
206/* Check Door Bell register to get an empty slot */
207static int get_empty_slot(int *slot)
208{
209 unsigned int data;
210 int i;
211
212 data = mmio_read_32(ufs_params.reg_base + UTRLDBR);
213 for (i = 0; i < nutrs; i++) {
214 if ((data & 1) == 0)
215 break;
216 data = data >> 1;
217 }
218 if (i >= nutrs)
219 return -EBUSY;
220 *slot = i;
221 return 0;
222}
223
224static void get_utrd(utp_utrd_t *utrd)
225{
226 uintptr_t base;
227 int slot = 0, result;
228 utrd_header_t *hd;
229
230 assert(utrd != NULL);
231 result = get_empty_slot(&slot);
232 assert(result == 0);
233
234 /* clear utrd */
235 memset((void *)utrd, 0, sizeof(utp_utrd_t));
236 base = ufs_params.desc_base + (slot * UFS_DESC_SIZE);
237 /* clear the descriptor */
238 memset((void *)base, 0, UFS_DESC_SIZE);
239
240 utrd->header = base;
241 utrd->task_tag = slot + 1;
242 /* CDB address should be aligned with 128 bytes */
243 utrd->upiu = ALIGN_CDB(utrd->header + sizeof(utrd_header_t));
244 utrd->resp_upiu = ALIGN_8(utrd->upiu + sizeof(cmd_upiu_t));
245 utrd->size_upiu = utrd->resp_upiu - utrd->upiu;
246 utrd->size_resp_upiu = ALIGN_8(sizeof(resp_upiu_t));
247 utrd->prdt = utrd->resp_upiu + utrd->size_resp_upiu;
248
249 hd = (utrd_header_t *)utrd->header;
250 hd->ucdba = utrd->upiu & UINT32_MAX;
251 hd->ucdbau = (utrd->upiu >> 32) & UINT32_MAX;
252 /* Both RUL and RUO is based on DWORD */
253 hd->rul = utrd->size_resp_upiu >> 2;
254 hd->ruo = utrd->size_upiu >> 2;
255 (void)result;
256}
257
258/*
259 * Prepare UTRD, Command UPIU, Response UPIU.
260 */
261static int ufs_prepare_cmd(utp_utrd_t *utrd, uint8_t op, uint8_t lun,
262 int lba, uintptr_t buf, size_t length)
263{
264 utrd_header_t *hd;
265 cmd_upiu_t *upiu;
266 prdt_t *prdt;
267 unsigned int ulba;
268 unsigned int lba_cnt;
269 int prdt_size;
270
271
272 mmio_write_32(ufs_params.reg_base + UTRLBA,
273 utrd->header & UINT32_MAX);
274 mmio_write_32(ufs_params.reg_base + UTRLBAU,
275 (utrd->upiu >> 32) & UINT32_MAX);
276
277 hd = (utrd_header_t *)utrd->header;
278 upiu = (cmd_upiu_t *)utrd->upiu;
279
280 hd->i = 1;
281 hd->ct = CT_UFS_STORAGE;
282 hd->ocs = OCS_MASK;
283
284 upiu->trans_type = CMD_UPIU;
285 upiu->task_tag = utrd->task_tag;
286 upiu->cdb[0] = op;
287 ulba = (unsigned int)lba;
288 lba_cnt = (unsigned int)(length >> UFS_BLOCK_SHIFT);
289 switch (op) {
290 case CDBCMD_TEST_UNIT_READY:
291 break;
292 case CDBCMD_READ_CAPACITY_10:
293 hd->dd = DD_OUT;
294 upiu->flags = UPIU_FLAGS_R | UPIU_FLAGS_ATTR_S;
295 upiu->lun = lun;
296 break;
297 case CDBCMD_READ_10:
298 hd->dd = DD_OUT;
299 upiu->flags = UPIU_FLAGS_R | UPIU_FLAGS_ATTR_S;
300 upiu->lun = lun;
301 upiu->cdb[1] = RW_WITHOUT_CACHE;
302 /* set logical block address */
303 upiu->cdb[2] = (ulba >> 24) & 0xff;
304 upiu->cdb[3] = (ulba >> 16) & 0xff;
305 upiu->cdb[4] = (ulba >> 8) & 0xff;
306 upiu->cdb[5] = ulba & 0xff;
307 /* set transfer length */
308 upiu->cdb[7] = (lba_cnt >> 8) & 0xff;
309 upiu->cdb[8] = lba_cnt & 0xff;
310 break;
311 case CDBCMD_WRITE_10:
312 hd->dd = DD_IN;
313 upiu->flags = UPIU_FLAGS_W | UPIU_FLAGS_ATTR_S;
314 upiu->lun = lun;
315 upiu->cdb[1] = RW_WITHOUT_CACHE;
316 /* set logical block address */
317 upiu->cdb[2] = (ulba >> 24) & 0xff;
318 upiu->cdb[3] = (ulba >> 16) & 0xff;
319 upiu->cdb[4] = (ulba >> 8) & 0xff;
320 upiu->cdb[5] = ulba & 0xff;
321 /* set transfer length */
322 upiu->cdb[7] = (lba_cnt >> 8) & 0xff;
323 upiu->cdb[8] = lba_cnt & 0xff;
324 break;
325 default:
326 assert(0);
Jonathan Wright39b42212018-03-13 15:24:29 +0000327 break;
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800328 }
329 if (hd->dd == DD_IN)
330 flush_dcache_range(buf, length);
331 else if (hd->dd == DD_OUT)
332 inv_dcache_range(buf, length);
333 if (length) {
334 upiu->exp_data_trans_len = htobe32(length);
335 assert(lba_cnt <= UINT16_MAX);
336 prdt = (prdt_t *)utrd->prdt;
337
338 prdt_size = 0;
339 while (length > 0) {
340 prdt->dba = (unsigned int)(buf & UINT32_MAX);
341 prdt->dbau = (unsigned int)((buf >> 32) & UINT32_MAX);
342 /* prdt->dbc counts from 0 */
343 if (length > MAX_PRDT_SIZE) {
344 prdt->dbc = MAX_PRDT_SIZE - 1;
345 length = length - MAX_PRDT_SIZE;
346 } else {
347 prdt->dbc = length - 1;
348 length = 0;
349 }
350 buf += MAX_PRDT_SIZE;
351 prdt++;
352 prdt_size += sizeof(prdt_t);
353 }
354 utrd->size_prdt = ALIGN_8(prdt_size);
355 hd->prdtl = utrd->size_prdt >> 2;
356 hd->prdto = (utrd->size_upiu + utrd->size_resp_upiu) >> 2;
357 }
358
359 flush_dcache_range((uintptr_t)utrd, sizeof(utp_utrd_t));
360 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE);
361 return 0;
362}
363
364static int ufs_prepare_query(utp_utrd_t *utrd, uint8_t op, uint8_t idn,
365 uint8_t index, uint8_t sel,
366 uintptr_t buf, size_t length)
367{
368 utrd_header_t *hd;
369 query_upiu_t *query_upiu;
370
371
372 hd = (utrd_header_t *)utrd->header;
373 query_upiu = (query_upiu_t *)utrd->upiu;
374
375 mmio_write_32(ufs_params.reg_base + UTRLBA,
376 utrd->header & UINT32_MAX);
377 mmio_write_32(ufs_params.reg_base + UTRLBAU,
378 (utrd->header >> 32) & UINT32_MAX);
379
380
381 hd->i = 1;
382 hd->ct = CT_UFS_STORAGE;
383 hd->ocs = OCS_MASK;
384
385 query_upiu->trans_type = QUERY_REQUEST_UPIU;
386 query_upiu->task_tag = utrd->task_tag;
387 query_upiu->ts.desc.opcode = op;
388 query_upiu->ts.desc.idn = idn;
389 query_upiu->ts.desc.index = index;
390 query_upiu->ts.desc.selector = sel;
391 switch (op) {
392 case QUERY_READ_DESC:
393 query_upiu->query_func = QUERY_FUNC_STD_READ;
394 query_upiu->ts.desc.length = htobe16(length);
395 break;
396 case QUERY_WRITE_DESC:
397 query_upiu->query_func = QUERY_FUNC_STD_WRITE;
398 query_upiu->ts.desc.length = htobe16(length);
399 memcpy((void *)(utrd->upiu + sizeof(query_upiu_t)),
400 (void *)buf, length);
401 break;
402 case QUERY_READ_ATTR:
403 case QUERY_READ_FLAG:
404 query_upiu->query_func = QUERY_FUNC_STD_READ;
405 break;
406 case QUERY_CLEAR_FLAG:
407 case QUERY_SET_FLAG:
408 query_upiu->query_func = QUERY_FUNC_STD_WRITE;
409 break;
410 case QUERY_WRITE_ATTR:
411 query_upiu->query_func = QUERY_FUNC_STD_WRITE;
412 memcpy((void *)&query_upiu->ts.attr.value, (void *)buf, length);
413 break;
414 default:
415 assert(0);
Jonathan Wright39b42212018-03-13 15:24:29 +0000416 break;
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800417 }
418 flush_dcache_range((uintptr_t)utrd, sizeof(utp_utrd_t));
419 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE);
420 return 0;
421}
422
423static void ufs_prepare_nop_out(utp_utrd_t *utrd)
424{
425 utrd_header_t *hd;
426 nop_out_upiu_t *nop_out;
427
428 mmio_write_32(ufs_params.reg_base + UTRLBA,
429 utrd->header & UINT32_MAX);
430 mmio_write_32(ufs_params.reg_base + UTRLBAU,
431 (utrd->header >> 32) & UINT32_MAX);
432
433 hd = (utrd_header_t *)utrd->header;
434 nop_out = (nop_out_upiu_t *)utrd->upiu;
435
436 hd->i = 1;
437 hd->ct = CT_UFS_STORAGE;
438 hd->ocs = OCS_MASK;
439
440 nop_out->trans_type = 0;
441 nop_out->task_tag = utrd->task_tag;
442 flush_dcache_range((uintptr_t)utrd, sizeof(utp_utrd_t));
443 flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE);
444}
445
446static void ufs_send_request(int task_tag)
447{
448 unsigned int data;
449 int slot;
450
451 slot = task_tag - 1;
452 /* clear all interrupts */
453 mmio_write_32(ufs_params.reg_base + IS, ~0);
454
455 mmio_write_32(ufs_params.reg_base + UTRLRSR, 1);
456 do {
457 data = mmio_read_32(ufs_params.reg_base + UTRLRSR);
458 } while (data == 0);
459
460 data = UTRIACR_IAEN | UTRIACR_CTR | UTRIACR_IACTH(0x1F) |
461 UTRIACR_IATOVAL(0xFF);
462 mmio_write_32(ufs_params.reg_base + UTRIACR, data);
463 /* send request */
464 mmio_setbits_32(ufs_params.reg_base + UTRLDBR, 1 << slot);
465}
466
467static int ufs_check_resp(utp_utrd_t *utrd, int trans_type)
468{
469 utrd_header_t *hd;
470 resp_upiu_t *resp;
471 unsigned int data;
472 int slot;
473
474 hd = (utrd_header_t *)utrd->header;
475 resp = (resp_upiu_t *)utrd->resp_upiu;
476 inv_dcache_range((uintptr_t)hd, UFS_DESC_SIZE);
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800477 do {
478 data = mmio_read_32(ufs_params.reg_base + IS);
479 if ((data & ~(UFS_INT_UCCS | UFS_INT_UTRCS)) != 0)
480 return -EIO;
481 } while ((data & UFS_INT_UTRCS) == 0);
482 slot = utrd->task_tag - 1;
483
484 data = mmio_read_32(ufs_params.reg_base + UTRLDBR);
485 assert((data & (1 << slot)) == 0);
486 assert(hd->ocs == OCS_SUCCESS);
487 assert((resp->trans_type & TRANS_TYPE_CODE_MASK) == trans_type);
488 (void)resp;
489 (void)slot;
490 return 0;
491}
492
493#ifdef UFS_RESP_DEBUG
494static void dump_upiu(utp_utrd_t *utrd)
495{
496 utrd_header_t *hd;
497 int i;
498
499 hd = (utrd_header_t *)utrd->header;
500 INFO("utrd:0x%x, ruo:0x%x, rul:0x%x, ocs:0x%x, UTRLDBR:0x%x\n",
501 (unsigned int)(uintptr_t)utrd, hd->ruo, hd->rul, hd->ocs,
502 mmio_read_32(ufs_params.reg_base + UTRLDBR));
503 for (i = 0; i < sizeof(utrd_header_t); i += 4) {
504 INFO("[%lx]:0x%x\n",
505 (uintptr_t)utrd->header + i,
506 *(unsigned int *)((uintptr_t)utrd->header + i));
507 }
508
509 for (i = 0; i < sizeof(cmd_upiu_t); i += 4) {
510 INFO("cmd[%lx]:0x%x\n",
511 utrd->upiu + i,
512 *(unsigned int *)(utrd->upiu + i));
513 }
514 for (i = 0; i < sizeof(resp_upiu_t); i += 4) {
515 INFO("resp[%lx]:0x%x\n",
516 utrd->resp_upiu + i,
517 *(unsigned int *)(utrd->resp_upiu + i));
518 }
519 for (i = 0; i < sizeof(prdt_t); i += 4) {
520 INFO("prdt[%lx]:0x%x\n",
521 utrd->prdt + i,
522 *(unsigned int *)(utrd->prdt + i));
523 }
524}
525#endif
526
527static void ufs_verify_init(void)
528{
529 utp_utrd_t utrd;
530 int result;
531
532 get_utrd(&utrd);
533 ufs_prepare_nop_out(&utrd);
534 ufs_send_request(utrd.task_tag);
535 result = ufs_check_resp(&utrd, NOP_IN_UPIU);
536 assert(result == 0);
537 (void)result;
538}
539
540static void ufs_verify_ready(void)
541{
542 utp_utrd_t utrd;
543 int result;
544
545 get_utrd(&utrd);
546 ufs_prepare_cmd(&utrd, CDBCMD_TEST_UNIT_READY, 0, 0, 0, 0);
547 ufs_send_request(utrd.task_tag);
548 result = ufs_check_resp(&utrd, RESPONSE_UPIU);
549 assert(result == 0);
550 (void)result;
551}
552
553static void ufs_query(uint8_t op, uint8_t idn, uint8_t index, uint8_t sel,
554 uintptr_t buf, size_t size)
555{
556 utp_utrd_t utrd;
557 query_resp_upiu_t *resp;
558 int result;
559
560 switch (op) {
561 case QUERY_READ_FLAG:
562 case QUERY_READ_ATTR:
563 case QUERY_READ_DESC:
564 case QUERY_WRITE_DESC:
565 case QUERY_WRITE_ATTR:
566 assert(((buf & 3) == 0) && (size != 0));
567 break;
Jonathan Wright39b42212018-03-13 15:24:29 +0000568 default:
569 /* Do nothing in default case */
570 break;
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800571 }
572 get_utrd(&utrd);
573 ufs_prepare_query(&utrd, op, idn, index, sel, buf, size);
574 ufs_send_request(utrd.task_tag);
575 result = ufs_check_resp(&utrd, QUERY_RESPONSE_UPIU);
576 assert(result == 0);
577 resp = (query_resp_upiu_t *)utrd.resp_upiu;
578#ifdef UFS_RESP_DEBUG
579 dump_upiu(&utrd);
580#endif
581 assert(resp->query_resp == QUERY_RESP_SUCCESS);
582
583 switch (op) {
584 case QUERY_READ_FLAG:
585 *(uint32_t *)buf = (uint32_t)resp->ts.flag.value;
586 break;
587 case QUERY_READ_ATTR:
588 case QUERY_READ_DESC:
589 memcpy((void *)buf,
590 (void *)(utrd.resp_upiu + sizeof(query_resp_upiu_t)),
591 size);
592 break;
Jonathan Wright39b42212018-03-13 15:24:29 +0000593 default:
594 /* Do nothing in default case */
595 break;
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800596 }
597 (void)result;
598}
599
600unsigned int ufs_read_attr(int idn)
601{
602 unsigned int value;
603
604 ufs_query(QUERY_READ_ATTR, idn, 0, 0,
605 (uintptr_t)&value, sizeof(value));
606 return value;
607}
608
609void ufs_write_attr(int idn, unsigned int value)
610{
611 ufs_query(QUERY_WRITE_ATTR, idn, 0, 0,
612 (uintptr_t)&value, sizeof(value));
613}
614
615unsigned int ufs_read_flag(int idn)
616{
617 unsigned int value;
618
619 ufs_query(QUERY_READ_FLAG, idn, 0, 0,
620 (uintptr_t)&value, sizeof(value));
621 return value;
622}
623
624void ufs_set_flag(int idn)
625{
626 ufs_query(QUERY_SET_FLAG, idn, 0, 0, 0, 0);
627}
628
629void ufs_clear_flag(int idn)
630{
631 ufs_query(QUERY_CLEAR_FLAG, idn, 0, 0, 0, 0);
632}
633
634void ufs_read_desc(int idn, int index, uintptr_t buf, size_t size)
635{
636 ufs_query(QUERY_READ_DESC, idn, index, 0, buf, size);
637}
638
639void ufs_write_desc(int idn, int index, uintptr_t buf, size_t size)
640{
641 ufs_query(QUERY_WRITE_DESC, idn, index, 0, buf, size);
642}
643
Florian La Roche231c2442019-01-27 14:30:12 +0100644static void ufs_read_capacity(int lun, unsigned int *num, unsigned int *size)
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800645{
646 utp_utrd_t utrd;
647 resp_upiu_t *resp;
648 sense_data_t *sense;
649 unsigned char data[CACHE_WRITEBACK_GRANULE << 1];
650 uintptr_t buf;
651 int result;
652 int retry;
653
654 assert((ufs_params.reg_base != 0) &&
655 (ufs_params.desc_base != 0) &&
656 (ufs_params.desc_size >= UFS_DESC_SIZE) &&
657 (num != NULL) && (size != NULL));
658
659 /* align buf address */
660 buf = (uintptr_t)data;
661 buf = (buf + CACHE_WRITEBACK_GRANULE - 1) &
662 ~(CACHE_WRITEBACK_GRANULE - 1);
663 memset((void *)buf, 0, CACHE_WRITEBACK_GRANULE);
664 flush_dcache_range(buf, CACHE_WRITEBACK_GRANULE);
665 do {
666 get_utrd(&utrd);
667 ufs_prepare_cmd(&utrd, CDBCMD_READ_CAPACITY_10, lun, 0,
668 buf, READ_CAPACITY_LENGTH);
669 ufs_send_request(utrd.task_tag);
670 result = ufs_check_resp(&utrd, RESPONSE_UPIU);
671 assert(result == 0);
672#ifdef UFS_RESP_DEBUG
673 dump_upiu(&utrd);
674#endif
675 resp = (resp_upiu_t *)utrd.resp_upiu;
676 retry = 0;
677 sense = &resp->sd.sense;
678 if (sense->resp_code == SENSE_DATA_VALID) {
679 if ((sense->sense_key == SENSE_KEY_UNIT_ATTENTION) &&
680 (sense->asc == 0x29) && (sense->ascq == 0)) {
681 retry = 1;
682 }
683 }
684 inv_dcache_range(buf, CACHE_WRITEBACK_GRANULE);
685 /* last logical block address */
686 *num = be32toh(*(unsigned int *)buf);
687 if (*num)
688 *num += 1;
689 /* logical block length in bytes */
690 *size = be32toh(*(unsigned int *)(buf + 4));
691 } while (retry);
692 (void)result;
693}
694
695size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size)
696{
697 utp_utrd_t utrd;
698 resp_upiu_t *resp;
699 int result;
700
701 assert((ufs_params.reg_base != 0) &&
702 (ufs_params.desc_base != 0) &&
703 (ufs_params.desc_size >= UFS_DESC_SIZE));
704
705 memset((void *)buf, 0, size);
706 get_utrd(&utrd);
707 ufs_prepare_cmd(&utrd, CDBCMD_READ_10, lun, lba, buf, size);
708 ufs_send_request(utrd.task_tag);
709 result = ufs_check_resp(&utrd, RESPONSE_UPIU);
710 assert(result == 0);
711#ifdef UFS_RESP_DEBUG
712 dump_upiu(&utrd);
713#endif
714 resp = (resp_upiu_t *)utrd.resp_upiu;
715 (void)result;
716 return size - resp->res_trans_cnt;
717}
718
719size_t ufs_write_blocks(int lun, int lba, const uintptr_t buf, size_t size)
720{
721 utp_utrd_t utrd;
722 resp_upiu_t *resp;
723 int result;
724
725 assert((ufs_params.reg_base != 0) &&
726 (ufs_params.desc_base != 0) &&
727 (ufs_params.desc_size >= UFS_DESC_SIZE));
728
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800729 get_utrd(&utrd);
730 ufs_prepare_cmd(&utrd, CDBCMD_WRITE_10, lun, lba, buf, size);
731 ufs_send_request(utrd.task_tag);
732 result = ufs_check_resp(&utrd, RESPONSE_UPIU);
733 assert(result == 0);
734#ifdef UFS_RESP_DEBUG
735 dump_upiu(&utrd);
736#endif
737 resp = (resp_upiu_t *)utrd.resp_upiu;
738 (void)result;
739 return size - resp->res_trans_cnt;
740}
741
742static void ufs_enum(void)
743{
744 unsigned int blk_num, blk_size;
745 int i;
746
747 /* 0 means 1 slot */
748 nutrs = (mmio_read_32(ufs_params.reg_base + CAP) & CAP_NUTRS_MASK) + 1;
749 if (nutrs > (ufs_params.desc_size / UFS_DESC_SIZE))
750 nutrs = ufs_params.desc_size / UFS_DESC_SIZE;
751
752 ufs_verify_init();
753 ufs_verify_ready();
754
755 ufs_set_flag(FLAG_DEVICE_INIT);
John Stultz938d1dc2019-05-13 16:56:19 -0700756 mdelay(200);
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800757 /* dump available LUNs */
758 for (i = 0; i < UFS_MAX_LUNS; i++) {
759 ufs_read_capacity(i, &blk_num, &blk_size);
760 if (blk_num && blk_size) {
761 INFO("UFS LUN%d contains %d blocks with %d-byte size\n",
762 i, blk_num, blk_size);
763 }
764 }
765}
766
fengbaopeng44070ef2018-02-12 20:53:54 +0800767static void ufs_get_device_info(struct ufs_dev_desc *card_data)
768{
769 uint8_t desc_buf[DESC_DEVICE_MAX_SIZE];
770
771 ufs_query(QUERY_READ_DESC, DESC_TYPE_DEVICE, 0, 0,
772 (uintptr_t)desc_buf, DESC_DEVICE_MAX_SIZE);
773
774 /*
775 * getting vendor (manufacturerID) and Bank Index in big endian
776 * format
777 */
778 card_data->wmanufacturerid = (uint16_t)((desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8) |
779 (desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]));
780}
781
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800782int ufs_init(const ufs_ops_t *ops, ufs_params_t *params)
783{
784 int result;
785 unsigned int data;
786 uic_cmd_t cmd;
fengbaopeng44070ef2018-02-12 20:53:54 +0800787 struct ufs_dev_desc card = {0};
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800788
789 assert((params != NULL) &&
790 (params->reg_base != 0) &&
791 (params->desc_base != 0) &&
792 (params->desc_size >= UFS_DESC_SIZE));
793
794 memcpy(&ufs_params, params, sizeof(ufs_params_t));
795
796 if (ufs_params.flags & UFS_FLAGS_SKIPINIT) {
797 result = ufshc_dme_get(0x1571, 0, &data);
798 assert(result == 0);
799 result = ufshc_dme_get(0x41, 0, &data);
800 assert(result == 0);
801 if (data == 1) {
802 /* prepare to exit hibernate mode */
803 memset(&cmd, 0, sizeof(uic_cmd_t));
804 cmd.op = DME_HIBERNATE_EXIT;
805 result = ufshc_send_uic_cmd(ufs_params.reg_base,
806 &cmd);
807 assert(result == 0);
808 data = mmio_read_32(ufs_params.reg_base + UCMDARG2);
809 assert(data == 0);
810 do {
811 data = mmio_read_32(ufs_params.reg_base + IS);
812 } while ((data & UFS_INT_UHXS) == 0);
813 mmio_write_32(ufs_params.reg_base + IS, UFS_INT_UHXS);
814 data = mmio_read_32(ufs_params.reg_base + HCS);
815 assert((data & HCS_UPMCRS_MASK) == HCS_PWR_LOCAL);
816 }
817 result = ufshc_dme_get(0x1568, 0, &data);
818 assert(result == 0);
819 assert((data > 0) && (data <= 3));
820 } else {
821 assert((ops != NULL) && (ops->phy_init != NULL) &&
822 (ops->phy_set_pwr_mode != NULL));
823
Jorge Troncoso5f449162021-09-30 16:29:32 -0700824 result = ufshc_reset(ufs_params.reg_base);
825 assert(result == 0);
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800826 ops->phy_init(&ufs_params);
827 result = ufshc_link_startup(ufs_params.reg_base);
828 assert(result == 0);
fengbaopeng44070ef2018-02-12 20:53:54 +0800829
830 ufs_enum();
831
832 ufs_get_device_info(&card);
833 if (card.wmanufacturerid == UFS_VENDOR_SKHYNIX) {
834 ufs_params.flags |= UFS_FLAGS_VENDOR_SKHYNIX;
835 }
836
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800837 ops->phy_set_pwr_mode(&ufs_params);
838 }
839
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800840 (void)result;
841 return 0;
842}