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Soby Mathew12012dd2015-10-26 14:01:53 +00001/*
Madhukar Pappireddyb5859d02023-08-03 14:17:54 -05002 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
Florian Lugoud4e25032021-09-08 12:40:24 +02003 * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved.
Soby Mathew12012dd2015-10-26 14:01:53 +00004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathew12012dd2015-10-26 14:01:53 +00006 */
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007
Soby Mathew12012dd2015-10-26 14:01:53 +00008#include <assert.h>
Antonio Nino Diaza4210cb2018-08-21 09:44:43 +01009#include <stdbool.h>
Soby Mathew12012dd2015-10-26 14:01:53 +000010
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <arch_helpers.h>
12#include <common/bl_common.h>
Claus Pedersen785e66c2022-09-12 22:42:58 +000013#include <common/debug.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <bl31/interrupt_mgmt.h>
15#include <drivers/arm/gic_common.h>
16#include <drivers/arm/gicv3.h>
17#include <lib/cassert.h>
18#include <plat/common/platform.h>
19
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090020#ifdef IMAGE_BL31
Soby Mathew12012dd2015-10-26 14:01:53 +000021
22/*
23 * The following platform GIC functions are weakly defined. They
24 * provide typical implementations that may be re-used by multiple
25 * platforms but may also be overridden by a platform if required.
26 */
27#pragma weak plat_ic_get_pending_interrupt_id
28#pragma weak plat_ic_get_pending_interrupt_type
29#pragma weak plat_ic_acknowledge_interrupt
30#pragma weak plat_ic_get_interrupt_type
31#pragma weak plat_ic_end_of_interrupt
32#pragma weak plat_interrupt_type_to_line
33
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +010034#pragma weak plat_ic_get_running_priority
Jeenu Viswambharan522a4652017-09-22 08:32:09 +010035#pragma weak plat_ic_is_spi
36#pragma weak plat_ic_is_ppi
37#pragma weak plat_ic_is_sgi
Jeenu Viswambharan24e70292017-09-22 08:32:09 +010038#pragma weak plat_ic_get_interrupt_active
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +010039#pragma weak plat_ic_enable_interrupt
40#pragma weak plat_ic_disable_interrupt
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +010041#pragma weak plat_ic_set_interrupt_priority
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010042#pragma weak plat_ic_set_interrupt_type
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +010043#pragma weak plat_ic_raise_el3_sgi
Florian Lugoud4e25032021-09-08 12:40:24 +020044#pragma weak plat_ic_raise_ns_sgi
45#pragma weak plat_ic_raise_s_el1_sgi
Jeenu Viswambharandce70b32017-09-22 08:32:09 +010046#pragma weak plat_ic_set_spi_routing
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +010047#pragma weak plat_ic_set_interrupt_pending
48#pragma weak plat_ic_clear_interrupt_pending
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +010049
Soby Mathew12012dd2015-10-26 14:01:53 +000050/*
51 * This function returns the highest priority pending interrupt at
52 * the Interrupt controller
53 */
54uint32_t plat_ic_get_pending_interrupt_id(void)
55{
56 unsigned int irqnr;
57
58 assert(IS_IN_EL3());
59 irqnr = gicv3_get_pending_interrupt_id();
Antonio Nino Diaza4210cb2018-08-21 09:44:43 +010060 return gicv3_is_intr_id_special_identifier(irqnr) ?
Soby Mathew12012dd2015-10-26 14:01:53 +000061 INTR_ID_UNAVAILABLE : irqnr;
62}
63
64/*
65 * This function returns the type of the highest priority pending interrupt
66 * at the Interrupt controller. In the case of GICv3, the Highest Priority
67 * Pending interrupt system register (`ICC_HPPIR0_EL1`) is read to determine
68 * the id of the pending interrupt. The type of interrupt depends upon the
69 * id value as follows.
70 * 1. id = PENDING_G1S_INTID (1020) is reported as a S-EL1 interrupt
71 * 2. id = PENDING_G1NS_INTID (1021) is reported as a Non-secure interrupt.
72 * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt
73 * type.
74 * 4. All other interrupt id's are reported as EL3 interrupt.
75 */
76uint32_t plat_ic_get_pending_interrupt_type(void)
77{
78 unsigned int irqnr;
Antonio Nino Diaza4210cb2018-08-21 09:44:43 +010079 uint32_t type;
Soby Mathew12012dd2015-10-26 14:01:53 +000080
81 assert(IS_IN_EL3());
82 irqnr = gicv3_get_pending_interrupt_type();
83
84 switch (irqnr) {
85 case PENDING_G1S_INTID:
Antonio Nino Diaza4210cb2018-08-21 09:44:43 +010086 type = INTR_TYPE_S_EL1;
87 break;
Soby Mathew12012dd2015-10-26 14:01:53 +000088 case PENDING_G1NS_INTID:
Antonio Nino Diaza4210cb2018-08-21 09:44:43 +010089 type = INTR_TYPE_NS;
90 break;
Soby Mathew12012dd2015-10-26 14:01:53 +000091 case GIC_SPURIOUS_INTERRUPT:
Antonio Nino Diaza4210cb2018-08-21 09:44:43 +010092 type = INTR_TYPE_INVAL;
93 break;
Soby Mathew12012dd2015-10-26 14:01:53 +000094 default:
Antonio Nino Diaza4210cb2018-08-21 09:44:43 +010095 type = INTR_TYPE_EL3;
96 break;
Soby Mathew12012dd2015-10-26 14:01:53 +000097 }
Antonio Nino Diaza4210cb2018-08-21 09:44:43 +010098
99 return type;
Soby Mathew12012dd2015-10-26 14:01:53 +0000100}
101
102/*
103 * This function returns the highest priority pending interrupt at
104 * the Interrupt controller and indicates to the Interrupt controller
105 * that the interrupt processing has started.
106 */
107uint32_t plat_ic_acknowledge_interrupt(void)
108{
109 assert(IS_IN_EL3());
110 return gicv3_acknowledge_interrupt();
111}
112
113/*
114 * This function returns the type of the interrupt `id`, depending on how
Madhukar Pappireddyb5859d02023-08-03 14:17:54 -0500115 * the interrupt has been configured in the interrupt controller.
Soby Mathew12012dd2015-10-26 14:01:53 +0000116 */
117uint32_t plat_ic_get_interrupt_type(uint32_t id)
118{
Madhukar Pappireddyb5859d02023-08-03 14:17:54 -0500119 unsigned int group;
120
Soby Mathew12012dd2015-10-26 14:01:53 +0000121 assert(IS_IN_EL3());
Madhukar Pappireddyb5859d02023-08-03 14:17:54 -0500122 group = gicv3_get_interrupt_group(id, plat_my_core_pos());
123
124 switch (group) {
125 case INTR_GROUP0:
126 return INTR_TYPE_EL3;
127 case INTR_GROUP1S:
128 return INTR_TYPE_S_EL1;
129 case INTR_GROUP1NS:
130 return INTR_TYPE_NS;
131 default:
132 assert(false); /* Unreachable */
133 return INTR_TYPE_EL3;
134 }
Soby Mathew12012dd2015-10-26 14:01:53 +0000135}
136
137/*
138 * This functions is used to indicate to the interrupt controller that
139 * the processing of the interrupt corresponding to the `id` has
140 * finished.
141 */
142void plat_ic_end_of_interrupt(uint32_t id)
143{
144 assert(IS_IN_EL3());
145 gicv3_end_of_interrupt(id);
146}
147
148/*
149 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
150 * The interrupt controller knows which pin/line it uses to signal a type of
151 * interrupt. It lets the interrupt management framework determine for a type of
152 * interrupt and security state, which line should be used in the SCR_EL3 to
153 * control its routing to EL3. The interrupt line is represented as the bit
154 * position of the IRQ or FIQ bit in the SCR_EL3.
155 */
156uint32_t plat_interrupt_type_to_line(uint32_t type,
157 uint32_t security_state)
158{
Antonio Nino Diaza4210cb2018-08-21 09:44:43 +0100159 assert((type == INTR_TYPE_S_EL1) ||
160 (type == INTR_TYPE_EL3) ||
161 (type == INTR_TYPE_NS));
Soby Mathew12012dd2015-10-26 14:01:53 +0000162
163 assert(sec_state_is_valid(security_state));
164 assert(IS_IN_EL3());
165
166 switch (type) {
167 case INTR_TYPE_S_EL1:
168 /*
169 * The S-EL1 interrupts are signaled as IRQ in S-EL0/1 contexts
170 * and as FIQ in the NS-EL0/1/2 contexts
171 */
172 if (security_state == SECURE)
173 return __builtin_ctz(SCR_IRQ_BIT);
174 else
175 return __builtin_ctz(SCR_FIQ_BIT);
Daniel Boulby8942a1b2018-06-22 14:16:03 +0100176 assert(0); /* Unreachable */
Soby Mathew12012dd2015-10-26 14:01:53 +0000177 case INTR_TYPE_NS:
178 /*
179 * The Non secure interrupts will be signaled as FIQ in S-EL0/1
180 * contexts and as IRQ in the NS-EL0/1/2 contexts.
181 */
182 if (security_state == SECURE)
183 return __builtin_ctz(SCR_FIQ_BIT);
184 else
185 return __builtin_ctz(SCR_IRQ_BIT);
Daniel Boulby8942a1b2018-06-22 14:16:03 +0100186 assert(0); /* Unreachable */
Soby Mathew12012dd2015-10-26 14:01:53 +0000187 case INTR_TYPE_EL3:
188 /*
189 * The EL3 interrupts are signaled as FIQ in both S-EL0/1 and
190 * NS-EL0/1/2 contexts
191 */
192 return __builtin_ctz(SCR_FIQ_BIT);
Jonathan Wrightb669ca72018-03-14 17:55:32 +0000193 default:
194 panic();
Soby Mathew12012dd2015-10-26 14:01:53 +0000195 }
196}
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100197
198unsigned int plat_ic_get_running_priority(void)
199{
200 return gicv3_get_running_priority();
201}
202
Jeenu Viswambharan522a4652017-09-22 08:32:09 +0100203int plat_ic_is_spi(unsigned int id)
204{
205 return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID);
206}
207
208int plat_ic_is_ppi(unsigned int id)
209{
210 return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID);
211}
212
213int plat_ic_is_sgi(unsigned int id)
214{
215 return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID);
216}
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100217
218unsigned int plat_ic_get_interrupt_active(unsigned int id)
219{
220 return gicv3_get_interrupt_active(id, plat_my_core_pos());
221}
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +0100222
223void plat_ic_enable_interrupt(unsigned int id)
224{
225 gicv3_enable_interrupt(id, plat_my_core_pos());
226}
227
228void plat_ic_disable_interrupt(unsigned int id)
229{
230 gicv3_disable_interrupt(id, plat_my_core_pos());
231}
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +0100232
233void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority)
234{
235 gicv3_set_interrupt_priority(id, plat_my_core_pos(), priority);
236}
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100237
Madhukar Pappireddy67ac77c2023-09-06 16:50:22 -0500238bool plat_ic_has_interrupt_type(unsigned int type)
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100239{
Madhukar Pappireddy81e46872023-08-03 14:29:40 -0500240 if ((type == INTR_TYPE_EL3) || (type == INTR_TYPE_S_EL1) ||
241 (type == INTR_TYPE_NS)) {
Madhukar Pappireddy67ac77c2023-09-06 16:50:22 -0500242 return true;
Madhukar Pappireddy81e46872023-08-03 14:29:40 -0500243 }
244
Madhukar Pappireddy67ac77c2023-09-06 16:50:22 -0500245 return false;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100246}
247
248void plat_ic_set_interrupt_type(unsigned int id, unsigned int type)
249{
Madhukar Pappireddyb5859d02023-08-03 14:17:54 -0500250 unsigned int group;
251
252 switch (type) {
253 case INTR_TYPE_EL3:
254 group = INTR_GROUP0;
255 break;
256 case INTR_TYPE_S_EL1:
257 group = INTR_GROUP1S;
258 break;
259 case INTR_TYPE_NS:
260 group = INTR_GROUP1NS;
261 break;
262 default:
263 assert(false); /* Unreachable */
264 group = INTR_GROUP0;
265 break;
266 }
267
268 gicv3_set_interrupt_group(id, plat_my_core_pos(), group);
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100269}
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100270
271void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target)
272{
273 /* Target must be a valid MPIDR in the system */
274 assert(plat_core_pos_by_mpidr(target) >= 0);
275
276 /* Verify that this is a secure EL3 SGI */
Antonio Nino Diaza4210cb2018-08-21 09:44:43 +0100277 assert(plat_ic_get_interrupt_type((unsigned int)sgi_num) ==
278 INTR_TYPE_EL3);
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100279
Florian Lugoud4e25032021-09-08 12:40:24 +0200280 gicv3_raise_sgi((unsigned int)sgi_num, GICV3_G0, target);
281}
282
283void plat_ic_raise_ns_sgi(int sgi_num, u_register_t target)
284{
285 /* Target must be a valid MPIDR in the system */
286 assert(plat_core_pos_by_mpidr(target) >= 0);
287
288 /* Verify that this is a non-secure SGI */
289 assert(plat_ic_get_interrupt_type((unsigned int)sgi_num) ==
290 INTR_TYPE_NS);
291
292 gicv3_raise_sgi((unsigned int)sgi_num, GICV3_G1NS, target);
293}
294
295void plat_ic_raise_s_el1_sgi(int sgi_num, u_register_t target)
296{
297 /* Target must be a valid MPIDR in the system */
298 assert(plat_core_pos_by_mpidr(target) >= 0);
299
300 /* Verify that this is a secure EL1 SGI */
301 assert(plat_ic_get_interrupt_type((unsigned int)sgi_num) ==
302 INTR_TYPE_S_EL1);
303
304 gicv3_raise_sgi((unsigned int)sgi_num, GICV3_G1S, target);
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100305}
Jeenu Viswambharandce70b32017-09-22 08:32:09 +0100306
307void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode,
308 u_register_t mpidr)
309{
310 unsigned int irm = 0;
311
312 switch (routing_mode) {
313 case INTR_ROUTING_MODE_PE:
314 assert(plat_core_pos_by_mpidr(mpidr) >= 0);
315 irm = GICV3_IRM_PE;
316 break;
317 case INTR_ROUTING_MODE_ANY:
318 irm = GICV3_IRM_ANY;
319 break;
320 default:
Daniel Boulby8942a1b2018-06-22 14:16:03 +0100321 assert(0); /* Unreachable */
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000322 break;
Jeenu Viswambharandce70b32017-09-22 08:32:09 +0100323 }
324
325 gicv3_set_spi_routing(id, irm, mpidr);
326}
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +0100327
328void plat_ic_set_interrupt_pending(unsigned int id)
329{
330 /* Disallow setting SGIs pending */
331 assert(id >= MIN_PPI_ID);
332 gicv3_set_interrupt_pending(id, plat_my_core_pos());
333}
334
335void plat_ic_clear_interrupt_pending(unsigned int id)
336{
337 /* Disallow setting SGIs pending */
338 assert(id >= MIN_PPI_ID);
339 gicv3_clear_interrupt_pending(id, plat_my_core_pos());
340}
Jeenu Viswambharan62505072017-09-22 08:32:09 +0100341
342unsigned int plat_ic_set_priority_mask(unsigned int mask)
343{
344 return gicv3_set_pmr(mask);
345}
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +0100346
347unsigned int plat_ic_get_interrupt_id(unsigned int raw)
348{
Antonio Nino Diaza4210cb2018-08-21 09:44:43 +0100349 unsigned int id = raw & INT_ID_MASK;
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +0100350
Antonio Nino Diaza4210cb2018-08-21 09:44:43 +0100351 return gicv3_is_intr_id_special_identifier(id) ?
352 INTR_ID_UNAVAILABLE : id;
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +0100353}
Soby Mathew12012dd2015-10-26 14:01:53 +0000354#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900355#ifdef IMAGE_BL32
Soby Mathew12012dd2015-10-26 14:01:53 +0000356
357#pragma weak plat_ic_get_pending_interrupt_id
358#pragma weak plat_ic_acknowledge_interrupt
359#pragma weak plat_ic_end_of_interrupt
360
Soby Mathew0d268dc2016-07-11 14:13:56 +0100361/* In AArch32, the secure group1 interrupts are targeted to Secure PL1 */
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700362#ifndef __aarch64__
Soby Mathew0d268dc2016-07-11 14:13:56 +0100363#define IS_IN_EL1() IS_IN_SECURE()
364#endif
365
Soby Mathew12012dd2015-10-26 14:01:53 +0000366/*
367 * This function returns the highest priority pending interrupt at
368 * the Interrupt controller
369 */
370uint32_t plat_ic_get_pending_interrupt_id(void)
371{
372 unsigned int irqnr;
373
374 assert(IS_IN_EL1());
375 irqnr = gicv3_get_pending_interrupt_id_sel1();
376 return (irqnr == GIC_SPURIOUS_INTERRUPT) ?
377 INTR_ID_UNAVAILABLE : irqnr;
378}
379
380/*
381 * This function returns the highest priority pending interrupt at
382 * the Interrupt controller and indicates to the Interrupt controller
383 * that the interrupt processing has started.
384 */
385uint32_t plat_ic_acknowledge_interrupt(void)
386{
387 assert(IS_IN_EL1());
388 return gicv3_acknowledge_interrupt_sel1();
389}
390
391/*
392 * This functions is used to indicate to the interrupt controller that
393 * the processing of the interrupt corresponding to the `id` has
394 * finished.
395 */
396void plat_ic_end_of_interrupt(uint32_t id)
397{
398 assert(IS_IN_EL1());
399 gicv3_end_of_interrupt_sel1(id);
400}
401#endif