Jeetesh Burman | 50cd106 | 2018-07-19 13:07:23 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef SE_PRIVATE_H |
| 8 | #define SE_PRIVATE_H |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
| 12 | /* SE0 security register */ |
| 13 | #define SE0_SECURITY U(0x18) |
| 14 | #define SE0_SECURITY_SE_SOFT_SETTING (((uint32_t)1) << 16U) |
| 15 | |
| 16 | /* SE0 config register */ |
| 17 | #define SE0_SHA_CONFIG U(0x104) |
| 18 | #define SE0_SHA_TASK_CONFIG U(0x108) |
| 19 | #define SE0_SHA_CONFIG_HW_INIT_HASH ((1U) << 0U) |
| 20 | #define SE0_SHA_CONFIG_HW_INIT_HASH_DISABLE U(0) |
| 21 | |
| 22 | #define SE0_CONFIG_ENC_ALG_SHIFT U(12) |
| 23 | #define SE0_CONFIG_ENC_ALG_SHA \ |
| 24 | (((uint32_t)3) << SE0_CONFIG_ENC_ALG_SHIFT) |
| 25 | #define SE0_CONFIG_DEC_ALG_SHIFT U(8) |
| 26 | #define SE0_CONFIG_DEC_ALG_NOP \ |
| 27 | (((uint32_t)0) << SE0_CONFIG_DEC_ALG_SHIFT) |
| 28 | #define SE0_CONFIG_DST_SHIFT U(2) |
| 29 | #define SE0_CONFIG_DST_HASHREG \ |
| 30 | (((uint32_t)1) << SE0_CONFIG_DST_SHIFT) |
| 31 | #define SHA256_HASH_SIZE_BYTES U(256) |
| 32 | |
| 33 | #define SE0_CONFIG_ENC_MODE_SHIFT U(24) |
| 34 | #define SE0_CONFIG_ENC_MODE_SHA256 \ |
| 35 | (((uint32_t)5) << SE0_CONFIG_ENC_MODE_SHIFT) |
| 36 | |
| 37 | /* SHA input message length */ |
| 38 | #define SE0_SHA_MSG_LENGTH_0 U(0x11c) |
| 39 | #define SE0_SHA_MSG_LENGTH_1 U(0x120) |
| 40 | #define SE0_SHA_MSG_LENGTH_2 U(0x124) |
| 41 | #define SE0_SHA_MSG_LENGTH_3 U(0x128) |
| 42 | |
| 43 | /* SHA input message left */ |
| 44 | #define SE0_SHA_MSG_LEFT_0 U(0x12c) |
| 45 | #define SE0_SHA_MSG_LEFT_1 U(0x130) |
| 46 | #define SE0_SHA_MSG_LEFT_2 U(0x134) |
| 47 | #define SE0_SHA_MSG_LEFT_3 U(0x138) |
| 48 | |
| 49 | /* SE Hash Result */ |
| 50 | #define SE0_SHA_HASH_RESULT_0 U(0x13c) |
| 51 | |
| 52 | /* SE OPERATION */ |
| 53 | #define SE0_OPERATION_REG_OFFSET U(0x17c) |
| 54 | #define SE0_UNIT_OPERATION_PKT_LASTBUF_SHIFT U(16) |
| 55 | #define SE0_UNIT_OPERATION_PKT_LASTBUF_FIELD \ |
| 56 | (((uint32_t)0x1) << SE0_UNIT_OPERATION_PKT_LASTBUF_SHIFT) |
| 57 | #define SE0_OPERATION_SHIFT U(0) |
| 58 | #define SE0_OP_START \ |
| 59 | (((uint32_t)0x1) << SE0_OPERATION_SHIFT) |
| 60 | |
| 61 | /* SE Interrupt */ |
| 62 | #define SE0_SHA_INT_ENABLE U(0x180) |
| 63 | |
| 64 | #define SE0_INT_STATUS_REG_OFFSET U(0x184) |
| 65 | #define SE0_INT_OP_DONE_SHIFT U(4) |
| 66 | #define SE0_INT_OP_DONE_CLEAR \ |
| 67 | (((uint32_t)0) << SE0_INT_OP_DONE_SHIFT) |
| 68 | #define SE0_INT_OP_DONE(x) \ |
| 69 | ((x) & (((uint32_t)0x1) << SE0_INT_OP_DONE_SHIFT)) |
| 70 | |
| 71 | /* SE SHA status */ |
| 72 | #define SE0_SHA_STATUS_0 U(0x188) |
| 73 | #define SE0_SHA_STATUS_IDLE U(0) |
| 74 | |
| 75 | /* SE error status */ |
| 76 | #define SE0_ERR_STATUS_REG_OFFSET U(0x18c) |
| 77 | #define SE0_ERR_STATUS_CLEAR U(0) |
| 78 | #define SE0_IN_ADDR U(0x10c) |
| 79 | #define SE0_IN_HI_ADDR_HI U(0x110) |
| 80 | #define SE0_IN_HI_ADDR_HI_0_MSB_SHIFT U(24) |
| 81 | |
| 82 | /* SE error status */ |
| 83 | #define SECURE_SCRATCH_TZDRAM_SHA256_HASH_START SECURE_SCRATCH_RSV63_LO |
| 84 | #define SECURE_SCRATCH_TZDRAM_SHA256_HASH_END SECURE_SCRATCH_RSV66_HI |
| 85 | |
| 86 | /******************************************************************************* |
| 87 | * Inline functions definition |
| 88 | ******************************************************************************/ |
| 89 | |
| 90 | static inline uint32_t tegra_se_read_32(uint32_t offset) |
| 91 | { |
| 92 | return mmio_read_32((uint32_t)(TEGRA_SE0_BASE + offset)); |
| 93 | } |
| 94 | |
| 95 | static inline void tegra_se_write_32(uint32_t offset, uint32_t val) |
| 96 | { |
| 97 | mmio_write_32(((uint32_t)(TEGRA_SE0_BASE + offset)), val); |
| 98 | } |
| 99 | |
| 100 | #endif /* SE_PRIVATE_H */ |