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developer2a56b2c2020-06-16 13:28:28 +08001/*
2 * Copyright (c) 2020, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef MTSPMC_PRIVATE_H
8#define MTSPMC_PRIVATE_H
9
10#include <lib/utils_def.h>
11#include <platform_def.h>
12
13unsigned long read_cpuectlr(void);
14void write_cpuectlr(unsigned long cpuectlr);
15
16unsigned long read_cpupwrctlr_el1(void);
17void write_cpupwrctlr_el1(unsigned long cpuectlr);
18
19/*
20 * per_cpu/cluster helper
21 */
22struct per_cpu_reg {
23 unsigned int cluster_addr;
24 unsigned int cpu_stride;
25};
26
27#define per_cpu(cluster, cpu, reg) \
28 (reg[cluster].cluster_addr + (cpu << reg[cluster].cpu_stride))
29
30#define per_cluster(cluster, reg) (reg[cluster].cluster_addr)
31
32#define SPM_REG(ofs) (uint32_t)(SPM_BASE + (ofs))
33#define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs))
34#define INFRACFG_AO_REG(ofs) (uint32_t)(INFRACFG_AO_BASE + (ofs))
35
36/* === SPMC related registers */
37#define SPM_POWERON_CONFIG_EN SPM_REG(0x000)
38/* bit-fields of SPM_POWERON_CONFIG_EN */
39#define PROJECT_CODE (U(0xb16) << 16)
40#define BCLK_CG_EN BIT(0)
41
42#define SPM_PWR_STATUS SPM_REG(0x16c)
43#define SPM_PWR_STATUS_2ND SPM_REG(0x170)
44#define SPM_CPU_PWR_STATUS SPM_REG(0x174)
45
46/* bit-fields of SPM_PWR_STATUS */
47#define MD BIT(0)
48#define CONN BIT(1)
49#define DDRPHY BIT(2)
50#define DISP BIT(3)
51#define MFG BIT(4)
52#define ISP BIT(5)
53#define INFRA BIT(6)
54#define VDEC BIT(7)
55#define MP0_CPUTOP BIT(8)
56#define MP0_CPU0 BIT(9)
57#define MP0_CPU1 BIT(10)
58#define MP0_CPU2 BIT(11)
59#define MP0_CPU3 BIT(12)
60#define MCUSYS BIT(14)
61#define MP0_CPU4 BIT(15)
62#define MP0_CPU5 BIT(16)
63#define MP0_CPU6 BIT(17)
64#define MP0_CPU7 BIT(18)
65#define VEN BIT(21)
66
67/* === SPMC related registers */
68#define SPM_MCUSYS_PWR_CON MCUCFG_REG(0xd200)
69#define SPM_MP0_CPUTOP_PWR_CON MCUCFG_REG(0xd204)
70#define SPM_MP0_CPU0_PWR_CON MCUCFG_REG(0xd208)
71#define SPM_MP0_CPU1_PWR_CON MCUCFG_REG(0xd20c)
72#define SPM_MP0_CPU2_PWR_CON MCUCFG_REG(0xd210)
73#define SPM_MP0_CPU3_PWR_CON MCUCFG_REG(0xd214)
74#define SPM_MP0_CPU4_PWR_CON MCUCFG_REG(0xd218)
75#define SPM_MP0_CPU5_PWR_CON MCUCFG_REG(0xd21c)
76#define SPM_MP0_CPU6_PWR_CON MCUCFG_REG(0xd220)
77#define SPM_MP0_CPU7_PWR_CON MCUCFG_REG(0xd224)
78
79/* bit fields of SPM_*_PWR_CON */
80#define PWR_ON_ACK BIT(31)
81#define VPROC_EXT_OFF BIT(7)
82#define DORMANT_EN BIT(6)
83#define RESETPWRON_CONFIG BIT(5)
84#define PWR_CLK_DIS BIT(4)
85#define PWR_ON BIT(2)
86#define PWR_RST_B BIT(0)
87
88/**** per_cpu registers for SPM_MP0_CPU?_PWR_CON */
89static const struct per_cpu_reg SPM_CPU_PWR[] = {
90 { .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2U }
91};
92
93/**** per_cluster registers for SPM_MP0_CPUTOP_PWR_CON */
94static const struct per_cpu_reg SPM_CLUSTER_PWR[] = {
95 { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON, .cpu_stride = 0U }
96};
97
98/* === MCUCFG related registers */
99/* aa64naa32 */
100#define MCUCFG_MP0_CLUSTER_CFG5 MCUCFG_REG(0xc8e4)
101/* reset vectors */
102#define MCUCFG_MP0_CLUSTER_CFG8 MCUCFG_REG(0xc900)
103#define MCUCFG_MP0_CLUSTER_CFG10 MCUCFG_REG(0xc908)
104#define MCUCFG_MP0_CLUSTER_CFG12 MCUCFG_REG(0xc910)
105#define MCUCFG_MP0_CLUSTER_CFG14 MCUCFG_REG(0xc918)
106#define MCUCFG_MP0_CLUSTER_CFG16 MCUCFG_REG(0xc920)
107#define MCUCFG_MP0_CLUSTER_CFG18 MCUCFG_REG(0xc928)
108#define MCUCFG_MP0_CLUSTER_CFG20 MCUCFG_REG(0xc930)
109#define MCUCFG_MP0_CLUSTER_CFG22 MCUCFG_REG(0xc938)
110
111/* MCUSYS DREQ BIG VPROC ISO control */
112#define DREQ20_BIG_VPROC_ISO MCUCFG_REG(0xad8c)
113
114/**** per_cpu registers for MCUCFG_MP0_CLUSTER_CFG? */
115static const struct per_cpu_reg MCUCFG_BOOTADDR[] = {
116 { .cluster_addr = MCUCFG_MP0_CLUSTER_CFG8, .cpu_stride = 3U }
117};
118
119/**** per_cpu registers for MCUCFG_MP0_CLUSTER_CFG5 */
120static const struct per_cpu_reg MCUCFG_INITARCH[] = {
121 { .cluster_addr = MCUCFG_MP0_CLUSTER_CFG5, .cpu_stride = 0U }
122};
123
124#define MCUCFG_INITARCH_CPU_BIT(cpu) BIT(16U + cpu)
developer2a56b2c2020-06-16 13:28:28 +0800125/* === CPC control */
126#define MCUCFG_CPC_FLOW_CTRL_CFG MCUCFG_REG(0xa814)
127#define MCUCFG_CPC_SPMC_PWR_STATUS MCUCFG_REG(0xa840)
128
129/* bit fields of CPC_FLOW_CTRL_CFG */
130#define CPC_CTRL_ENABLE BIT(16)
developer1c2a2102020-06-16 11:48:36 +0800131#define SSPM_CORE_PWR_ON_EN BIT(7) /* for cpu-hotplug */
developer2a56b2c2020-06-16 13:28:28 +0800132#define SSPM_ALL_PWR_CTRL_EN BIT(13) /* for cpu-hotplug */
133#define GIC_WAKEUP_IGNORE(cpu) BIT(21 + cpu)
134
135/* bit fields of CPC_SPMC_PWR_STATUS */
developer1c2a2102020-06-16 11:48:36 +0800136#define CORE_SPMC_PWR_ON_ACK GENMASK(11, 0)
developer2a56b2c2020-06-16 13:28:28 +0800137
138/* === APB Module infracfg_ao */
139#define INFRA_TOPAXI_PROTECTEN INFRACFG_AO_REG(0x0220)
140#define INFRA_TOPAXI_PROTECTEN_STA0 INFRACFG_AO_REG(0x0224)
141#define INFRA_TOPAXI_PROTECTEN_STA1 INFRACFG_AO_REG(0x0228)
142#define INFRA_TOPAXI_PROTECTEN_SET INFRACFG_AO_REG(0x02a0)
143#define INFRA_TOPAXI_PROTECTEN_CLR INFRACFG_AO_REG(0x02a4)
144#define INFRA_TOPAXI_PROTECTEN_1 INFRACFG_AO_REG(0x0250)
145#define INFRA_TOPAXI_PROTECTEN_STA0_1 INFRACFG_AO_REG(0x0254)
146#define INFRA_TOPAXI_PROTECTEN_STA1_1 INFRACFG_AO_REG(0x0258)
147#define INFRA_TOPAXI_PROTECTEN_1_SET INFRACFG_AO_REG(0x02a8)
148#define INFRA_TOPAXI_PROTECTEN_1_CLR INFRACFG_AO_REG(0x02ac)
149
150/* bit fields of INFRA_TOPAXI_PROTECTEN */
151#define MP0_SPMC_PROT_STEP1_0_MASK BIT(12)
152#define MP0_SPMC_PROT_STEP1_1_MASK (BIT(26) | BIT(12))
153
154/* === SPARK */
155#define VOLTAGE_04 U(0x40)
156#define VOLTAGE_05 U(0x60)
157
158#define PTP3_CPU0_SPMC_SW_CFG MCUCFG_REG(0x200)
159#define CPU0_ILDO_CONTROL5 MCUCFG_REG(0x334)
160#define CPU0_ILDO_CONTROL8 MCUCFG_REG(0x340)
161
162/* bit fields of CPU0_ILDO_CONTROL5 */
163#define ILDO_RET_VOSEL GENMASK(7, 0)
164
165/* bit fields of PTP3_CPU_SPMC_SW_CFG */
166#define SW_SPARK_EN BIT(0)
167
168/* bit fields of CPU0_ILDO_CONTROL8 */
169#define ILDO_BYPASS_B BIT(0)
170
171static const struct per_cpu_reg MCUCFG_SPARK[] = {
172 { .cluster_addr = PTP3_CPU0_SPMC_SW_CFG, .cpu_stride = 11U }
173};
174
175static const struct per_cpu_reg ILDO_CONTROL5[] = {
176 { .cluster_addr = CPU0_ILDO_CONTROL5, .cpu_stride = 11U }
177};
178
179static const struct per_cpu_reg ILDO_CONTROL8[] = {
180 { .cluster_addr = CPU0_ILDO_CONTROL8, .cpu_stride = 11U }
181};
182
183#endif /* MTSPMC_PRIVATE_H */