| Amit Nagal | 055796f | 2024-06-05 12:32:38 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. |
| 3 | * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. |
| 4 | * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. |
| 5 | * |
| 6 | * SPDX-License-Identifier: BSD-3-Clause |
| 7 | */ |
| 8 | |
| 9 | #include <arch.h> |
| 10 | #include <asm_macros.S> |
| 11 | #include <drivers/arm/gicv3.h> |
| 12 | |
| 13 | #include <platform_def.h> |
| 14 | |
| 15 | .globl plat_secondary_cold_boot_setup |
| 16 | .globl plat_is_my_cpu_primary |
| 17 | .globl platform_mem_init |
| 18 | .globl plat_my_core_pos |
| 19 | |
| 20 | /* ----------------------------------------------------- |
| 21 | * void plat_secondary_cold_boot_setup (void); |
| 22 | * |
| 23 | * This function performs any platform specific actions |
| 24 | * needed for a secondary cpu after a cold reset e.g |
| 25 | * mark the cpu's presence, mechanism to place it in a |
| 26 | * holding pen etc. |
| 27 | * TODO: Should we read the PSYS register to make sure |
| 28 | * that the request has gone through. |
| 29 | * ----------------------------------------------------- |
| 30 | */ |
| 31 | func plat_secondary_cold_boot_setup |
| 32 | mrs x0, mpidr_el1 |
| 33 | |
| 34 | /* |
| 35 | * There is no sane reason to come out of this wfi. This |
| 36 | * cpu will be powered on and reset by the cpu_on pm api |
| 37 | */ |
| 38 | dsb sy |
| 39 | bl plat_panic_handler |
| 40 | endfunc plat_secondary_cold_boot_setup |
| 41 | |
| 42 | func plat_is_my_cpu_primary |
| 43 | mov x9, x30 |
| 44 | bl plat_my_core_pos |
| 45 | cmp x0, #PRIMARY_CPU |
| 46 | cset x0, eq |
| 47 | ret x9 |
| 48 | endfunc plat_is_my_cpu_primary |
| 49 | |
| 50 | /* ----------------------------------------------------- |
| 51 | * unsigned int plat_my_core_pos(void) |
| 52 | * This function uses the plat_core_pos_by_mpidr() |
| 53 | * definition to get the index of the calling CPU. |
| 54 | * ----------------------------------------------------- |
| 55 | */ |
| 56 | func plat_my_core_pos |
| 57 | mrs x0, mpidr_el1 |
| 58 | b plat_core_pos_by_mpidr |
| 59 | endfunc plat_my_core_pos |
| 60 | |
| 61 | /* --------------------------------------------------------------------- |
| 62 | * We don't need to carry out any memory initialization on platform |
| 63 | * The Secure RAM is accessible straight away. |
| 64 | * --------------------------------------------------------------------- |
| 65 | */ |
| 66 | func platform_mem_init |
| 67 | ret |
| 68 | endfunc platform_mem_init |