developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | #ifndef __MCUCFG_H__ |
| 31 | #define __MCUCFG_H__ |
| 32 | |
| 33 | #include <mt8173_def.h> |
| 34 | #include <stdint.h> |
| 35 | |
| 36 | struct mt8173_mcucfg_regs { |
| 37 | uint32_t mp0_ca7l_cache_config; |
| 38 | struct { |
| 39 | uint32_t mem_delsel0; |
| 40 | uint32_t mem_delsel1; |
| 41 | } mp0_cpu[4]; |
| 42 | uint32_t mp0_cache_mem_delsel0; |
| 43 | uint32_t mp0_cache_mem_delsel1; |
| 44 | uint32_t mp0_axi_config; |
| 45 | uint32_t mp0_misc_config[2]; |
| 46 | struct { |
| 47 | uint32_t rv_addr_lw; |
| 48 | uint32_t rv_addr_hw; |
| 49 | } mp0_rv_addr[4]; |
| 50 | uint32_t mp0_ca7l_cfg_dis; |
| 51 | uint32_t mp0_ca7l_clken_ctrl; |
| 52 | uint32_t mp0_ca7l_rst_ctrl; |
| 53 | uint32_t mp0_ca7l_misc_config; |
| 54 | uint32_t mp0_ca7l_dbg_pwr_ctrl; |
| 55 | uint32_t mp0_rw_rsvd0; |
| 56 | uint32_t mp0_rw_rsvd1; |
| 57 | uint32_t mp0_ro_rsvd; |
| 58 | uint32_t reserved0_0[100]; |
| 59 | uint32_t mp1_cpucfg; |
| 60 | uint32_t mp1_miscdbg; |
| 61 | uint32_t reserved0_1[13]; |
| 62 | uint32_t mp1_rst_ctl; |
| 63 | uint32_t mp1_clkenm_div; |
| 64 | uint32_t reserved0_2[7]; |
| 65 | uint32_t mp1_config_res; |
| 66 | uint32_t reserved0_3[13]; |
| 67 | struct { |
| 68 | uint32_t rv_addr_lw; |
| 69 | uint32_t rv_addr_hw; |
| 70 | } mp1_rv_addr[2]; |
| 71 | uint32_t reserved0_4[84]; |
| 72 | uint32_t mp0_rst_status; /* 0x400 */ |
| 73 | uint32_t mp0_dbg_ctrl; |
| 74 | uint32_t mp0_dbg_flag; |
| 75 | uint32_t mp0_ca7l_ir_mon; |
| 76 | struct { |
| 77 | uint32_t pc_lw; |
| 78 | uint32_t pc_hw; |
| 79 | uint32_t fp_arch32; |
| 80 | uint32_t sp_arch32; |
| 81 | uint32_t fp_arch64_lw; |
| 82 | uint32_t fp_arch64_hw; |
| 83 | uint32_t sp_arch64_lw; |
| 84 | uint32_t sp_arch64_hw; |
| 85 | } mp0_dbg_core[4]; |
| 86 | uint32_t dfd_ctrl; |
| 87 | uint32_t dfd_cnt_l; |
| 88 | uint32_t dfd_cnt_h; |
| 89 | uint32_t misccfg_mp0_rw_rsvd; |
| 90 | uint32_t misccfg_sec_vio_status0; |
| 91 | uint32_t misccfg_sec_vio_status1; |
| 92 | uint32_t reserved1[22]; |
| 93 | uint32_t misccfg_rw_rsvd; /* 0x500 */ |
| 94 | uint32_t mcusys_dbg_mon_sel_a; |
| 95 | uint32_t mcusys_dbg_mon; |
| 96 | uint32_t reserved2[61]; |
| 97 | uint32_t mcusys_config_a; /* 0x600 */ |
| 98 | uint32_t mcusys_config1_a; |
| 99 | uint32_t mcusys_gic_peribase_a; |
| 100 | uint32_t reserved3; |
| 101 | uint32_t sec_range0_start; /* 0x610 */ |
| 102 | uint32_t sec_range0_end; |
| 103 | uint32_t sec_range_enable; |
| 104 | uint32_t reserved4; |
| 105 | uint32_t int_pol_ctl[8]; /* 0x620 */ |
| 106 | uint32_t aclken_div; /* 0x640 */ |
| 107 | uint32_t pclken_div; |
| 108 | uint32_t l2c_sram_ctrl; |
| 109 | uint32_t armpll_jit_ctrl; |
| 110 | uint32_t cci_addrmap; /* 0x650 */ |
| 111 | uint32_t cci_config; |
| 112 | uint32_t cci_periphbase; |
| 113 | uint32_t cci_nevntcntovfl; |
| 114 | uint32_t cci_clk_ctrl; /* 0x660 */ |
| 115 | uint32_t cci_acel_s1_ctrl; |
| 116 | uint32_t bus_fabric_dcm_ctrl; |
| 117 | uint32_t reserved5; |
| 118 | uint32_t xgpt_ctl; /* 0x670 */ |
| 119 | uint32_t xgpt_idx; |
| 120 | uint32_t ptpod2_ctl0; |
| 121 | uint32_t ptpod2_ctl1; |
| 122 | uint32_t mcusys_revid; |
| 123 | uint32_t mcusys_rw_rsvd0; |
| 124 | uint32_t mcusys_rw_rsvd1; |
| 125 | }; |
| 126 | |
| 127 | static struct mt8173_mcucfg_regs *const mt8173_mcucfg = (void *)MCUCFG_BASE; |
| 128 | |
| 129 | /* cpu boot mode */ |
| 130 | enum { |
| 131 | MP0_CPUCFG_64BIT_SHIFT = 12, |
| 132 | MP1_CPUCFG_64BIT_SHIFT = 28, |
| 133 | MP0_CPUCFG_64BIT = 0xf << MP0_CPUCFG_64BIT_SHIFT, |
| 134 | MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT |
| 135 | }; |
| 136 | |
| 137 | /* scu related */ |
| 138 | enum { |
| 139 | MP0_ACINACTM_SHIFT = 4, |
| 140 | MP1_ACINACTM_SHIFT = 0, |
| 141 | MP0_ACINACTM = 1 << MP0_ACINACTM_SHIFT, |
| 142 | MP1_ACINACTM = 1 << MP1_ACINACTM_SHIFT |
| 143 | }; |
| 144 | |
| 145 | enum { |
| 146 | MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0, |
| 147 | MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4, |
| 148 | MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8, |
| 149 | MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12, |
| 150 | MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16, |
| 151 | |
| 152 | MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK = |
| 153 | 0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT, |
| 154 | MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK = |
| 155 | 0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT, |
| 156 | MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK = |
| 157 | 0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT, |
| 158 | MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK = |
| 159 | 0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT, |
| 160 | MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK = |
| 161 | 0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT |
| 162 | }; |
| 163 | |
| 164 | enum { |
| 165 | MP1_AINACTS_SHIFT = 4, |
| 166 | MP1_AINACTS = 1 << MP1_AINACTS_SHIFT |
| 167 | }; |
| 168 | |
| 169 | enum { |
| 170 | MP1_SW_CG_GEN_SHIFT = 12, |
| 171 | MP1_SW_CG_GEN = 1 << MP1_SW_CG_GEN_SHIFT |
| 172 | }; |
| 173 | |
| 174 | enum { |
| 175 | MP1_L2RSTDISABLE_SHIFT = 14, |
| 176 | MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT |
| 177 | }; |
| 178 | |
| 179 | #endif /* __MCUCFG_H__ */ |