| developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | #include <assert.h> |
| 31 | #include <debug.h> |
| 32 | #include <delay_timer.h> |
| 33 | #include <mt8173_def.h> |
| 34 | #include <pmic_wrap_init.h> |
| 35 | #include <rtc.h> |
| 36 | |
| 37 | /* RTC busy status polling interval and retry count */ |
| 38 | enum { |
| 39 | RTC_WRTGR_POLLING_DELAY_MS = 10, |
| 40 | RTC_WRTGR_POLLING_CNT = 100 |
| 41 | }; |
| 42 | |
| 43 | static uint16_t RTC_Read(uint32_t addr) |
| 44 | { |
| 45 | uint32_t rdata = 0; |
| 46 | |
| 47 | pwrap_read((uint32_t)addr, &rdata); |
| 48 | return (uint16_t)rdata; |
| 49 | } |
| 50 | |
| 51 | static void RTC_Write(uint32_t addr, uint16_t data) |
| 52 | { |
| 53 | pwrap_write((uint32_t)addr, (uint32_t)data); |
| 54 | } |
| 55 | |
| 56 | static inline int32_t rtc_busy_wait(void) |
| 57 | { |
| 58 | uint64_t retry = RTC_WRTGR_POLLING_CNT; |
| 59 | |
| 60 | do { |
| 61 | mdelay(RTC_WRTGR_POLLING_DELAY_MS); |
| 62 | if (!(RTC_Read(RTC_BBPU) & RTC_BBPU_CBUSY)) |
| 63 | return 1; |
| 64 | retry--; |
| 65 | } while (retry); |
| 66 | |
| 67 | ERROR("[RTC] rtc cbusy time out!\n"); |
| 68 | return 0; |
| 69 | } |
| 70 | |
| 71 | static int32_t Write_trigger(void) |
| 72 | { |
| 73 | RTC_Write(RTC_WRTGR, 1); |
| 74 | return rtc_busy_wait(); |
| 75 | } |
| 76 | |
| 77 | static int32_t Writeif_unlock(void) |
| 78 | { |
| 79 | RTC_Write(RTC_PROT, RTC_PROT_UNLOCK1); |
| 80 | if (!Write_trigger()) |
| 81 | return 0; |
| 82 | RTC_Write(RTC_PROT, RTC_PROT_UNLOCK2); |
| 83 | if (!Write_trigger()) |
| 84 | return 0; |
| 85 | |
| 86 | return 1; |
| 87 | } |
| 88 | |
| 89 | void rtc_bbpu_power_down(void) |
| 90 | { |
| 91 | uint16_t bbpu; |
| 92 | |
| 93 | /* pull PWRBB low */ |
| 94 | bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_PWREN; |
| 95 | if (Writeif_unlock()) { |
| 96 | RTC_Write(RTC_BBPU, bbpu); |
| 97 | if (!Write_trigger()) |
| 98 | assert(1); |
| 99 | } else { |
| 100 | assert(1); |
| 101 | } |
| 102 | } |