Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arm_def.h> |
| 8 | #include <arm_gic.h> |
| 9 | #include <plat_arm.h> |
| 10 | #include <platform.h> |
| 11 | #include <platform_def.h> |
| 12 | |
| 13 | /****************************************************************************** |
| 14 | * The following function is defined as weak to allow a platform to override |
| 15 | * the way the Legacy GICv3 driver is initialised and used. |
| 16 | *****************************************************************************/ |
| 17 | #pragma weak plat_arm_gic_driver_init |
| 18 | #pragma weak plat_arm_gic_init |
| 19 | #pragma weak plat_arm_gic_cpuif_enable |
| 20 | #pragma weak plat_arm_gic_cpuif_disable |
| 21 | #pragma weak plat_arm_gic_pcpu_init |
| 22 | |
| 23 | /* |
| 24 | * In the GICv3 Legacy mode, the Group 1 secure interrupts are treated as Group |
| 25 | * 0 interrupts. |
| 26 | */ |
Soby Mathew | cf022c5 | 2016-01-13 17:06:00 +0000 | [diff] [blame] | 27 | static const unsigned int irq_sec_array[] = { |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 28 | PLAT_ARM_G0_IRQS, |
| 29 | PLAT_ARM_G1S_IRQS |
| 30 | }; |
| 31 | |
| 32 | void plat_arm_gic_driver_init(void) |
| 33 | { |
| 34 | arm_gic_init(PLAT_ARM_GICC_BASE, |
| 35 | PLAT_ARM_GICD_BASE, |
| 36 | PLAT_ARM_GICR_BASE, |
| 37 | irq_sec_array, |
| 38 | ARRAY_SIZE(irq_sec_array)); |
| 39 | } |
| 40 | |
| 41 | /****************************************************************************** |
| 42 | * ARM common helper to initialize the GIC. |
| 43 | *****************************************************************************/ |
| 44 | void plat_arm_gic_init(void) |
| 45 | { |
| 46 | arm_gic_setup(); |
| 47 | } |
| 48 | |
| 49 | /****************************************************************************** |
| 50 | * ARM common helper to enable the GIC CPU interface |
| 51 | *****************************************************************************/ |
| 52 | void plat_arm_gic_cpuif_enable(void) |
| 53 | { |
| 54 | arm_gic_cpuif_setup(); |
| 55 | } |
| 56 | |
| 57 | /****************************************************************************** |
| 58 | * ARM common helper to disable the GIC CPU interface |
| 59 | *****************************************************************************/ |
| 60 | void plat_arm_gic_cpuif_disable(void) |
| 61 | { |
| 62 | arm_gic_cpuif_deactivate(); |
| 63 | } |
| 64 | |
| 65 | /****************************************************************************** |
| 66 | * ARM common helper to initialize the per-cpu distributor in GICv2 or |
| 67 | * redistributor interface in GICv3. |
| 68 | *****************************************************************************/ |
| 69 | void plat_arm_gic_pcpu_init(void) |
| 70 | { |
| 71 | arm_gic_pcpu_distif_setup(); |
| 72 | } |
Jeenu Viswambharan | 78132c9 | 2016-12-09 11:12:34 +0000 | [diff] [blame] | 73 | |
| 74 | /****************************************************************************** |
| 75 | * Stubs for Redistributor power management. Although legacy configuration isn't |
| 76 | * supported, these are provided for the sake of uniform GIC API |
| 77 | *****************************************************************************/ |
| 78 | void plat_arm_gic_redistif_on(void) |
| 79 | { |
| 80 | return; |
| 81 | } |
| 82 | |
| 83 | void plat_arm_gic_redistif_off(void) |
| 84 | { |
| 85 | return; |
| 86 | } |