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Pankaj Gupta82bd8432020-12-09 14:02:41 +05301/*
2 * Copyright 2021 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8#ifndef SOC_DEFAULT_HELPER_MACROS_H
9#define SOC_DEFAULT_HELPER_MACROS_H
10
11#ifdef NXP_OCRAM_TZPC_ADDR
12
13/* 0x1: means 4 KB
14 * 0x2: means 8 KB
15 */
16#define TZPC_BLOCK_SIZE 0x1000
17#endif
18
19/* DDR controller offsets and defines */
20#ifdef NXP_DDR_ADDR
21
22#define DDR_CFG_2_OFFSET 0x114
23#define CFG_2_FORCE_REFRESH 0x80000000
24
25#endif /* NXP_DDR_ADDR */
26
27 /* Reset block register offsets */
28#ifdef NXP_RESET_ADDR
29
30/* Register Offset */
31#define RST_RSTCR_OFFSET 0x0
32#define RST_RSTRQMR1_OFFSET 0x10
33#define RST_RSTRQSR1_OFFSET 0x18
34#define BRR_OFFSET 0x60
35
36/* helper macros */
37#define RSTRQSR1_SWRR 0x800
38#define RSTRQMR_RPTOE_MASK (1 << 19)
39
40#endif /* NXP_RESET_ADDR */
41
42/* Secure-Register-File register offsets and bit masks */
43#ifdef NXP_RST_ADDR
44/* Register Offset */
45#define CORE_HOLD_OFFSET 0x140
46#define RSTCNTL_OFFSET 0x180
47
48/* Helper macros */
49#define SW_RST_REQ_INIT 0x1
50#endif
51
52#ifdef NXP_RCPM_ADDR
53/* RCPM Register Offsets */
54#define RCPM_PCPH20SETR_OFFSET 0x0D4
55#define RCPM_PCPH20CLRR_OFFSET 0x0D8
56#define RCPM_POWMGTCSR_OFFSET 0x130
57#define RCPM_IPPDEXPCR0_OFFSET 0x140
58#define RCPM_POWMGTCSR_LPM20_REQ 0x00100000
Jiafei Pan64e2ba72021-09-27 12:18:41 +080059#endif /* NXP_RCPM_ADDR */
60
61#define DCFG_SBEESR2_ADDR 0x20140534
62#define DCFG_MBEESR2_ADDR 0x20140544
63/* SBEESR and MBEESR bit mask */
64#define OCRAM_EESR_MASK 0x00000060
Pankaj Gupta82bd8432020-12-09 14:02:41 +053065
66#endif /* SOC_DEFAULT_HELPER_MACROS_H */