| Ard Biesheuvel | c0415c6 | 2018-12-29 19:44:35 +0100 | [diff] [blame] | 1 | /* |
| Madhukar Pappireddy | aabef8d | 2019-07-08 18:05:24 -0500 | [diff] [blame] | 2 | * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. |
| Ard Biesheuvel | c0415c6 | 2018-12-29 19:44:35 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef SYNQUACER_PLAT_LD_S__ |
| 8 | #define SYNQUACER_PLAT_LD_S__ |
| 9 | |
| Madhukar Pappireddy | aabef8d | 2019-07-08 18:05:24 -0500 | [diff] [blame] | 10 | #include <lib/xlat_tables/xlat_tables_defs.h> |
| Ard Biesheuvel | c0415c6 | 2018-12-29 19:44:35 +0100 | [diff] [blame] | 11 | |
| 12 | #define SPM_SHIM_EXCEPTIONS_VMA SP_DRAM |
| 13 | |
| 14 | MEMORY { |
| 15 | SP_DRAM (rw): ORIGIN = PLAT_SQ_SP_PRIV_BASE, LENGTH = PLAT_SQ_SP_PRIV_SIZE |
| 16 | } |
| 17 | |
| 18 | SECTIONS |
| 19 | { |
| 20 | /* |
| 21 | * Put the page tables in secure DRAM so that the PTW can make cacheable |
| 22 | * accesses, as the core SPM code expects. (The SRAM on SynQuacer does |
| 23 | * not support inner shareable WBWA mappings so it is mapped normal |
| 24 | * non-cacheable) |
| 25 | */ |
| Chris Kay | 33bfc5e | 2023-02-14 11:30:04 +0000 | [diff] [blame] | 26 | .sp_xlat_table (NOLOAD) : ALIGN(PAGE_SIZE) { |
| 27 | *(.sp_xlat_table) |
| Ard Biesheuvel | c0415c6 | 2018-12-29 19:44:35 +0100 | [diff] [blame] | 28 | } >SP_DRAM |
| 29 | } |
| 30 | |
| 31 | #endif /* SYNQUACER_PLAT_LD_S__ */ |