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git01.mediatek.com / filogic / atf / 64e01a36a2277039dd79d2751d940b974e904fbe / . / include / plat / arm / common / arm_tzc_dram.ld.S
blob: c790bb927276cc7183283892274bcb4c2f00aedb [file] [log] [blame]
Soby Mathew3b5156e2017-10-05 12:27:33 +0100[diff] [blame]1/*
Chris Kay33bfc5e2023-02-14 11:30:04 +0000[diff] [blame]2 * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
Soby Mathew3b5156e2017-10-05 12:27:33 +0100[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]6#ifndef ARM_TZC_DRAM_LD_S
7#define ARM_TZC_DRAM_LD_S
Soby Mathew3b5156e2017-10-05 12:27:33 +0100[diff] [blame]8
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]9#include <lib/xlat_tables/xlat_tables_defs.h>
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000[diff] [blame]10
Soby Mathew3b5156e2017-10-05 12:27:33 +0100[diff] [blame]11MEMORY {
12 EL3_SEC_DRAM (rw): ORIGIN = ARM_EL3_TZC_DRAM1_BASE, LENGTH = ARM_EL3_TZC_DRAM1_SIZE
13}
14
15SECTIONS
16{
17 . = ARM_EL3_TZC_DRAM1_BASE;
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000[diff] [blame]18 ASSERT(. == ALIGN(PAGE_SIZE),
Soby Mathew3b5156e2017-10-05 12:27:33 +0100[diff] [blame]19 "ARM_EL3_TZC_DRAM_BASE address is not aligned on a page boundary.")
Chris Kay33bfc5e2023-02-14 11:30:04 +0000[diff] [blame]20 .el3_tzc_dram (NOLOAD) : ALIGN(PAGE_SIZE) {
Soby Mathew3b5156e2017-10-05 12:27:33 +0100[diff] [blame]21 __EL3_SEC_DRAM_START__ = .;
Chris Kay33bfc5e2023-02-14 11:30:04 +0000[diff] [blame]22 *(.arm_el3_tzc_dram)
Soby Mathew3b5156e2017-10-05 12:27:33 +0100[diff] [blame]23 __EL3_SEC_DRAM_UNALIGNED_END__ = .;
24
Roberto Vargasd93fde32018-04-11 11:53:31 +0100[diff] [blame]25 . = ALIGN(PAGE_SIZE);
Soby Mathew3b5156e2017-10-05 12:27:33 +0100[diff] [blame]26 __EL3_SEC_DRAM_END__ = .;
27 } >EL3_SEC_DRAM
28}
29
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]30#endif /* ARM_TZC_DRAM_LD_S */