Anson Huang | 73b1853 | 2018-06-05 16:13:45 +0800 | [diff] [blame] | 1 | /* |
Deepika Bhavnani | 92efb23 | 2019-12-13 10:47:06 -0600 | [diff] [blame] | 2 | * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. |
Anson Huang | 73b1853 | 2018-06-05 16:13:45 +0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <lib/utils_def.h> |
Anson Huang | 73b1853 | 2018-06-05 16:13:45 +0800 | [diff] [blame] | 11 | |
| 12 | #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" |
| 13 | #define PLATFORM_LINKER_ARCH aarch64 |
| 14 | |
| 15 | #define PLATFORM_STACK_SIZE 0x400 |
| 16 | #define CACHE_WRITEBACK_GRANULE 64 |
| 17 | |
Deepika Bhavnani | 92efb23 | 2019-12-13 10:47:06 -0600 | [diff] [blame] | 18 | #define PLAT_PRIMARY_CPU U(0x0) |
| 19 | #define PLATFORM_MAX_CPU_PER_CLUSTER U(4) |
| 20 | #define PLATFORM_CLUSTER_COUNT U(1) |
| 21 | #define PLATFORM_CORE_COUNT U(4) |
| 22 | #define PLATFORM_CLUSTER0_CORE_COUNT U(4) |
| 23 | #define PLATFORM_CLUSTER1_CORE_COUNT U(0) |
Anson Huang | 73b1853 | 2018-06-05 16:13:45 +0800 | [diff] [blame] | 24 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 25 | #define PWR_DOMAIN_AT_MAX_LVL U(1) |
| 26 | #define PLAT_MAX_PWR_LVL U(2) |
| 27 | #define PLAT_MAX_OFF_STATE U(2) |
| 28 | #define PLAT_MAX_RET_STATE U(1) |
Anson Huang | 73b1853 | 2018-06-05 16:13:45 +0800 | [diff] [blame] | 29 | |
| 30 | #define BL31_BASE 0x80000000 |
| 31 | #define BL31_LIMIT 0x80020000 |
| 32 | |
| 33 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) |
| 34 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) |
| 35 | |
| 36 | #define MAX_XLAT_TABLES 8 |
| 37 | #define MAX_MMAP_REGIONS 8 |
| 38 | |
| 39 | #define PLAT_GICD_BASE 0x51a00000 |
Anson Huang | 73b1853 | 2018-06-05 16:13:45 +0800 | [diff] [blame] | 40 | #define PLAT_GICR_BASE 0x51b00000 |
Igor Opaniuk | 72d8608 | 2020-03-23 17:21:05 +0200 | [diff] [blame] | 41 | |
| 42 | #if defined(IMX_USE_UART0) |
Anson Huang | 73b1853 | 2018-06-05 16:13:45 +0800 | [diff] [blame] | 43 | #define IMX_BOOT_UART_BASE 0x5a060000 |
Markus Niebel | ce82709 | 2021-03-02 18:44:25 +0100 | [diff] [blame] | 44 | #elif defined(IMX_USE_UART1) |
| 45 | #define IMX_BOOT_UART_BASE 0x5a070000 |
Igor Opaniuk | 72d8608 | 2020-03-23 17:21:05 +0200 | [diff] [blame] | 46 | #elif defined(IMX_USE_UART3) |
| 47 | #define IMX_BOOT_UART_BASE 0x5a090000 |
| 48 | #else |
| 49 | #error "Provide proper UART configuration in IMX_DEBUG_UART" |
| 50 | #endif |
| 51 | |
Anson Huang | 73b1853 | 2018-06-05 16:13:45 +0800 | [diff] [blame] | 52 | #define IMX_BOOT_UART_BAUDRATE 115200 |
| 53 | #define IMX_BOOT_UART_CLK_IN_HZ 24000000 |
| 54 | #define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE |
| 55 | #define PLAT__CRASH_UART_CLK_IN_HZ 24000000 |
| 56 | #define IMX_CONSOLE_BAUDRATE 115200 |
| 57 | #define SC_IPC_BASE 0x5d1b0000 |
Anson Huang | 3f2f3da | 2019-01-24 16:50:02 +0800 | [diff] [blame] | 58 | #define IMX_GPT0_LPCG_BASE 0x5d540000 |
| 59 | #define IMX_GPT0_BASE 0x5d140000 |
| 60 | #define IMX_WUP_IRQSTR_BASE 0x51090000 |
| 61 | #define IMX_REG_BASE 0x50000000 |
| 62 | #define IMX_REG_SIZE 0x10000000 |
Anson Huang | 73b1853 | 2018-06-05 16:13:45 +0800 | [diff] [blame] | 63 | |
| 64 | #define COUNTER_FREQUENCY 8000000 |
| 65 | |
| 66 | /* non-secure u-boot base */ |
| 67 | #define PLAT_NS_IMAGE_OFFSET 0x80020000 |
Igor Opaniuk | 72d8608 | 2020-03-23 17:21:05 +0200 | [diff] [blame] | 68 | #define DEBUG_CONSOLE_A35 DEBUG_CONSOLE |
Anson Huang | 73b1853 | 2018-06-05 16:13:45 +0800 | [diff] [blame] | 69 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 70 | #endif /* PLATFORM_DEF_H */ |