Heiko Stuebner | 9dc2833 | 2019-03-14 22:11:34 +0100 | [diff] [blame] | 1 | /* |
Julius Werner | f1d230c | 2019-05-30 16:57:15 -0700 | [diff] [blame] | 2 | * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. |
Heiko Stuebner | 9dc2833 | 2019-03-14 22:11:34 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
| 8 | |
| 9 | #include <platform_def.h> |
| 10 | |
| 11 | #include <arch_helpers.h> |
| 12 | #include <common/bl_common.h> |
| 13 | #include <common/debug.h> |
Julius Werner | f1d230c | 2019-05-30 16:57:15 -0700 | [diff] [blame] | 14 | #include <common/desc_image_load.h> |
Heiko Stuebner | 9dc2833 | 2019-03-14 22:11:34 +0100 | [diff] [blame] | 15 | #include <drivers/console.h> |
| 16 | #include <drivers/generic_delay_timer.h> |
| 17 | #include <drivers/ti/uart/uart_16550.h> |
| 18 | #include <lib/coreboot.h> |
| 19 | #include <lib/mmio.h> |
| 20 | #include <plat_private.h> |
| 21 | #include <plat/common/platform.h> |
| 22 | |
| 23 | static entry_point_info_t bl33_ep_info; |
| 24 | |
| 25 | /******************************************************************************* |
| 26 | * Return a pointer to the 'entry_point_info' structure of the next image for |
| 27 | * the security state specified. BL33 corresponds to the non-secure image type. |
| 28 | * A NULL pointer is returned if the image does not exist. |
| 29 | ******************************************************************************/ |
| 30 | entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) |
| 31 | { |
| 32 | entry_point_info_t *next_image_info; |
| 33 | |
| 34 | next_image_info = &bl33_ep_info; |
| 35 | |
| 36 | if (next_image_info->pc == 0U) { |
| 37 | return NULL; |
| 38 | } |
| 39 | |
| 40 | return next_image_info; |
| 41 | } |
| 42 | |
| 43 | #pragma weak params_early_setup |
Julius Werner | 65d5267 | 2019-05-24 20:37:58 -0700 | [diff] [blame] | 44 | void params_early_setup(u_register_t plat_param_from_bl2) |
Heiko Stuebner | 9dc2833 | 2019-03-14 22:11:34 +0100 | [diff] [blame] | 45 | { |
| 46 | } |
| 47 | |
| 48 | unsigned int plat_is_my_cpu_primary(void); |
| 49 | |
| 50 | /******************************************************************************* |
| 51 | * Perform any BL32 specific platform actions. |
| 52 | ******************************************************************************/ |
| 53 | void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, |
| 54 | u_register_t arg2, u_register_t arg3) |
| 55 | { |
| 56 | static console_16550_t console; |
Heiko Stuebner | 9dc2833 | 2019-03-14 22:11:34 +0100 | [diff] [blame] | 57 | |
Julius Werner | 65d5267 | 2019-05-24 20:37:58 -0700 | [diff] [blame] | 58 | params_early_setup(arg1); |
Heiko Stuebner | 9dc2833 | 2019-03-14 22:11:34 +0100 | [diff] [blame] | 59 | |
| 60 | #if COREBOOT |
| 61 | if (coreboot_serial.type) |
| 62 | console_16550_register(coreboot_serial.baseaddr, |
| 63 | coreboot_serial.input_hertz, |
| 64 | coreboot_serial.baud, |
| 65 | &console); |
| 66 | #else |
Christoph Müllner | cb9204a | 2019-04-19 14:16:27 +0200 | [diff] [blame] | 67 | console_16550_register(rockchip_get_uart_base(), PLAT_RK_UART_CLOCK, |
Heiko Stuebner | 9dc2833 | 2019-03-14 22:11:34 +0100 | [diff] [blame] | 68 | PLAT_RK_UART_BAUDRATE, &console); |
| 69 | #endif |
| 70 | VERBOSE("sp_min_setup\n"); |
| 71 | |
Julius Werner | f1d230c | 2019-05-30 16:57:15 -0700 | [diff] [blame] | 72 | bl31_params_parse_helper(arg0, NULL, &bl33_ep_info); |
Heiko Stuebner | 9dc2833 | 2019-03-14 22:11:34 +0100 | [diff] [blame] | 73 | } |
| 74 | |
| 75 | /******************************************************************************* |
| 76 | * Perform any sp_min platform setup code |
| 77 | ******************************************************************************/ |
| 78 | void sp_min_platform_setup(void) |
| 79 | { |
| 80 | generic_delay_timer_init(); |
| 81 | plat_rockchip_soc_init(); |
| 82 | |
| 83 | /* Initialize the gic cpu and distributor interfaces */ |
| 84 | plat_rockchip_gic_driver_init(); |
| 85 | plat_rockchip_gic_init(); |
| 86 | plat_rockchip_pmu_init(); |
| 87 | } |
| 88 | |
| 89 | /******************************************************************************* |
| 90 | * Perform the very early platform specific architectural setup here. At the |
| 91 | * moment this is only intializes the mmu in a quick and dirty way. |
| 92 | ******************************************************************************/ |
| 93 | void sp_min_plat_arch_setup(void) |
| 94 | { |
| 95 | plat_cci_init(); |
| 96 | plat_cci_enable(); |
| 97 | |
| 98 | plat_configure_mmu_svc_mon(BL_CODE_BASE, |
| 99 | BL_COHERENT_RAM_END - BL_CODE_BASE, |
| 100 | BL_CODE_BASE, |
| 101 | BL_CODE_END, |
| 102 | BL_COHERENT_RAM_BASE, |
| 103 | BL_COHERENT_RAM_END); |
| 104 | } |
| 105 | |
| 106 | void sp_min_plat_fiq_handler(uint32_t id) |
| 107 | { |
| 108 | VERBOSE("[sp_min] interrupt #%d\n", id); |
| 109 | } |