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Andre Przywara452b2b62018-09-28 00:37:19 +01001#
Samuel Holland1dad2652019-10-20 21:34:38 -05002# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
Andre Przywara452b2b62018-09-28 00:37:19 +01003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7include lib/xlat_tables_v2/xlat_tables.mk
8
9AW_PLAT := plat/allwinner
10
Samuel Holland4a024712019-11-27 13:09:40 -060011PLAT_INCLUDES := -Iinclude/plat/arm/common/aarch64 \
Andre Przywara452b2b62018-09-28 00:37:19 +010012 -I${AW_PLAT}/common/include \
13 -I${AW_PLAT}/${PLAT}/include
14
Andre Przywaraea5fa472018-09-16 02:08:06 +010015include lib/libfdt/libfdt.mk
16
Julius Werner6b88b652018-11-27 17:50:28 -080017PLAT_BL_COMMON_SOURCES := drivers/ti/uart/${ARCH}/16550_console.S \
Andre Przywara452b2b62018-09-28 00:37:19 +010018 ${XLAT_TABLES_LIB_SRCS} \
19 ${AW_PLAT}/common/plat_helpers.S \
20 ${AW_PLAT}/common/sunxi_common.c
21
Samuel Holland1dad2652019-10-20 21:34:38 -050022BL31_SOURCES += drivers/allwinner/axp/common.c \
Samuel Holland74703702018-10-21 12:24:16 -050023 drivers/allwinner/sunxi_msgbox.c \
Samuel Holland103ee9b2018-10-21 12:41:03 -050024 drivers/arm/css/scpi/css_scpi.c \
Samuel Holland1dad2652019-10-20 21:34:38 -050025 drivers/arm/gic/common/gic_common.c \
Andre Przywara452b2b62018-09-28 00:37:19 +010026 drivers/arm/gic/v2/gicv2_helpers.c \
27 drivers/arm/gic/v2/gicv2_main.c \
28 drivers/delay_timer/delay_timer.c \
29 drivers/delay_timer/generic_delay_timer.c \
30 lib/cpus/${ARCH}/cortex_a53.S \
31 plat/common/plat_gicv2.c \
32 plat/common/plat_psci_common.c \
33 ${AW_PLAT}/common/sunxi_bl31_setup.c \
34 ${AW_PLAT}/common/sunxi_cpu_ops.c \
35 ${AW_PLAT}/common/sunxi_pm.c \
36 ${AW_PLAT}/${PLAT}/sunxi_power.c \
37 ${AW_PLAT}/common/sunxi_security.c \
38 ${AW_PLAT}/common/sunxi_topology.c
39
40# The bootloader is guaranteed to only run on CPU 0 by the boot ROM.
41COLD_BOOT_SINGLE_CPU := 1
42
Samuel Hollandc47f00e2019-06-08 16:03:32 -050043# Do not enable SPE (not supported on ARM v8.0).
44ENABLE_SPE_FOR_LOWER_ELS := 0
45
46# Do not enable SVE (not supported on ARM v8.0).
47ENABLE_SVE_FOR_NS := 0
48
Andre Przywara452b2b62018-09-28 00:37:19 +010049# Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4.
50ERRATA_A53_835769 := 1
51ERRATA_A53_843419 := 1
52ERRATA_A53_855873 := 1
53
Andre Przywara452b2b62018-09-28 00:37:19 +010054# The reset vector can be changed for each CPU.
55PROGRAMMABLE_RESET_ADDRESS := 1
56
57# Allow mapping read-only data as execute-never.
58SEPARATE_CODE_AND_RODATA := 1
59
Samuel Hollandd00eaa22019-10-27 14:07:52 -050060# Put NOBITS memory in SRAM A1, overwriting U-Boot's SPL.
61SEPARATE_NOBITS_REGION := 1
62
Andre Przywara452b2b62018-09-28 00:37:19 +010063# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL
64RESET_TO_BL31 := 1
Andre Przywara647a2e12018-10-11 22:14:30 +010065
Samuel Hollandc47f00e2019-06-08 16:03:32 -050066# This platform is single-cluster and does not require coherency setup.
67WARMBOOT_ENABLE_DCACHE_EARLY := 1