| Sheetal Tigadoli | ad0943e | 2019-12-18 19:44:43 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017 - 2020, Broadcom |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef SWREG_H |
| 8 | #define SWREG_H |
| 9 | |
| 10 | /* default voltage if no valid OTP */ |
| 11 | #define VDDC_CORE_DEF_VOLT 910000 /* 0.91v */ |
| 12 | #define IHOST_DEF_VOLT 940000 /* 0.94v */ |
| 13 | |
| 14 | #define B0_VDDC_CORE_DEF_VOLT 950000 /* 0.95v */ |
| 15 | #define B0_IHOST_DEF_VOLT 950000 /* 0.95v */ |
| 16 | #define B0_DDR_VDDC_DEF_VOLT 1000000 /* 1v */ |
| 17 | |
| 18 | #define SWREG_IHOST1_DIS 4 |
| 19 | #define SWREG_IHOST1_REG_RESETB 5 |
| 20 | #define SWREG_IHOST1_PMU_STABLE 2 |
| 21 | |
| 22 | enum sw_reg { |
| 23 | DDR_VDDC = 1, |
| 24 | IHOST03, |
| 25 | IHOST12, |
| 26 | IHOST_ARRAY, |
| 27 | DDRIO_SLAVE, |
| 28 | VDDC_CORE, |
| 29 | VDDC1, |
| 30 | DDRIO_MASTER |
| 31 | }; |
| 32 | |
| 33 | int set_swreg(enum sw_reg reg_id, uint32_t micro_volts); |
| 34 | int swreg_firmware_update(void); |
| 35 | |
| 36 | #endif |