| Chandni Cherukuri | f781323 | 2018-09-16 21:06:29 +0530 | [diff] [blame] | 1 | /* |
| Rohit Mathew | a0dd307 | 2024-02-03 17:22:54 +0000 | [diff] [blame] | 2 | * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved. |
| Chandni Cherukuri | f781323 | 2018-09-16 21:06:29 +0530 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <lib/utils_def.h> |
| 11 | |
| Rohit Mathew | a0dd307 | 2024-02-03 17:22:54 +0000 | [diff] [blame] | 12 | #include <nrd_sdei.h> |
| 13 | #include <nrd_soc_platform_def.h> |
| Chandni Cherukuri | f781323 | 2018-09-16 21:06:29 +0530 | [diff] [blame] | 14 | |
| Deepika Bhavnani | 4287c0c | 2019-12-13 10:23:18 -0600 | [diff] [blame] | 15 | #define PLAT_ARM_CLUSTER_COUNT U(2) |
| 16 | #define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4) |
| 17 | #define CSS_SGI_MAX_PE_PER_CPU U(1) |
| Chandni Cherukuri | f781323 | 2018-09-16 21:06:29 +0530 | [diff] [blame] | 18 | |
| Vijayenthiran Subramaniam | 22141b6 | 2018-10-25 22:20:24 +0530 | [diff] [blame] | 19 | #define PLAT_CSS_MHU_BASE UL(0x45400000) |
| 20 | |
| 21 | /* Base address of DMC-620 instances */ |
| Chandni Cherukuri | 15ec1e5 | 2019-02-22 13:41:03 +0530 | [diff] [blame] | 22 | #define RDN1EDGE_DMC620_BASE0 UL(0x4e000000) |
| 23 | #define RDN1EDGE_DMC620_BASE1 UL(0x4e100000) |
| Chandni Cherukuri | f781323 | 2018-09-16 21:06:29 +0530 | [diff] [blame] | 24 | |
| Chandni Cherukuri | 0fdcbc0 | 2018-10-16 15:19:54 +0530 | [diff] [blame] | 25 | /* System power domain level */ |
| 26 | #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 |
| 27 | |
| Chandni Cherukuri | 504c05d | 2018-10-16 14:11:34 +0530 | [diff] [blame] | 28 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 |
| 29 | |
| Vijayenthiran Subramaniam | c4e68a4 | 2019-10-28 14:49:48 +0530 | [diff] [blame] | 30 | /* Virtual address used by dynamic mem_protect for chunk_base */ |
| 31 | #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) |
| 32 | |
| Vijayenthiran Subramaniam | 00cd080 | 2022-01-25 20:37:20 +0530 | [diff] [blame] | 33 | /* Maximum number of address bits used per chip */ |
| 34 | #define CSS_SGI_ADDR_BITS_PER_CHIP U(42) |
| 35 | |
| Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 36 | /* |
| 37 | * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes |
| 38 | */ |
| Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 39 | #ifdef __aarch64__ |
| Vijayenthiran Subramaniam | 00cd080 | 2022-01-25 20:37:20 +0530 | [diff] [blame] | 40 | #define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ |
| Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame^] | 41 | NRD_CHIP_COUNT) |
| Vijayenthiran Subramaniam | 00cd080 | 2022-01-25 20:37:20 +0530 | [diff] [blame] | 42 | #define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ |
| Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame^] | 43 | NRD_CHIP_COUNT) |
| Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 44 | #else |
| 45 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 46 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
| 47 | #endif |
| 48 | |
| Vijayenthiran Subramaniam | 64c9645 | 2020-02-03 12:14:01 +0530 | [diff] [blame] | 49 | /* GIC related constants */ |
| 50 | #define PLAT_ARM_GICD_BASE UL(0x30000000) |
| 51 | #define PLAT_ARM_GICC_BASE UL(0x2C000000) |
| 52 | #define PLAT_ARM_GICR_BASE UL(0x300C0000) |
| 53 | |
| Rohit Mathew | 0029868 | 2024-02-10 22:12:12 +0000 | [diff] [blame] | 54 | #define RDN1E1_CHIP0_SPI_START U(32) |
| 55 | #define RDN1E1_CHIP0_SPI_END U(991) |
| 56 | |
| Chandni Cherukuri | f781323 | 2018-09-16 21:06:29 +0530 | [diff] [blame] | 57 | #endif /* PLATFORM_DEF_H */ |