Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <asm_macros.S> |
| 33 | #include <bl_common.h> |
| 34 | #include <cortex_a57.h> |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 35 | #include <v2m_def.h> |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 36 | #include "../juno_def.h" |
| 37 | |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 38 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 39 | .globl plat_reset_handler |
David Wang | 323ebe8 | 2015-10-22 13:30:50 +0800 | [diff] [blame] | 40 | .globl plat_arm_calc_core_pos |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 41 | |
Sandrine Bailleux | fd8f898 | 2015-02-04 14:06:10 +0000 | [diff] [blame] | 42 | /* -------------------------------------------------------------------- |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 43 | * void plat_reset_handler(void); |
| 44 | * |
Sandrine Bailleux | fd8f898 | 2015-02-04 14:06:10 +0000 | [diff] [blame] | 45 | * For Juno r0: |
| 46 | * - Implement workaround for defect id 831273 by enabling an event |
| 47 | * stream every 65536 cycles. |
| 48 | * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 |
| 49 | * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 |
| 50 | * |
| 51 | * For Juno r1: |
| 52 | * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 |
| 53 | * Note that: |
| 54 | * - The default value for the L2 Tag RAM latency for Cortex-A57 is |
| 55 | * suitable. |
| 56 | * - Defect #831273 doesn't affect Juno r1. |
Sandrine Bailleux | fd8f898 | 2015-02-04 14:06:10 +0000 | [diff] [blame] | 57 | * -------------------------------------------------------------------- |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 58 | */ |
| 59 | func plat_reset_handler |
Sandrine Bailleux | fd8f898 | 2015-02-04 14:06:10 +0000 | [diff] [blame] | 60 | /* -------------------------------------------------------------------- |
| 61 | * Determine whether this code is running on Juno r0 or Juno r1. |
| 62 | * Keep this information in x2. |
| 63 | * -------------------------------------------------------------------- |
| 64 | */ |
| 65 | /* Read the V2M SYS_ID register */ |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 66 | mov_imm x0, (V2M_SYSREGS_BASE + V2M_SYS_ID) |
Sandrine Bailleux | fd8f898 | 2015-02-04 14:06:10 +0000 | [diff] [blame] | 67 | ldr w1, [x0] |
| 68 | /* Extract board revision from the SYS_ID */ |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 69 | ubfx x1, x1, #V2M_SYS_ID_REV_SHIFT, #4 |
Sandrine Bailleux | fd8f898 | 2015-02-04 14:06:10 +0000 | [diff] [blame] | 70 | /* |
| 71 | * On Juno R0: x2 := REV_JUNO_R0 - 1 = 0 |
| 72 | * On Juno R1: x2 := REV_JUNO_R1 - 1 = 1 |
| 73 | */ |
| 74 | sub x2, x1, #1 |
| 75 | |
| 76 | /* -------------------------------------------------------------------- |
| 77 | * Determine whether this code is executed on a Cortex-A53 or on a |
| 78 | * Cortex-A57 core. |
| 79 | * -------------------------------------------------------------------- |
| 80 | */ |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 81 | mrs x0, midr_el1 |
| 82 | ubfx x1, x0, MIDR_PN_SHIFT, #12 |
| 83 | cmp w1, #((CORTEX_A57_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK) |
Sandrine Bailleux | fd8f898 | 2015-02-04 14:06:10 +0000 | [diff] [blame] | 84 | b.eq A57 |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 85 | |
Sandrine Bailleux | fd8f898 | 2015-02-04 14:06:10 +0000 | [diff] [blame] | 86 | /* Nothing needs to be done for the Cortex-A53 on Juno r1 */ |
| 87 | cbz x2, apply_831273 |
| 88 | ret |
| 89 | |
| 90 | A57: |
| 91 | /* -------------------------------------------------------------------- |
| 92 | * Cortex-A57 specific settings |
| 93 | * -------------------------------------------------------------------- |
| 94 | */ |
| 95 | |
| 96 | /* Change the L2 Data RAM latency to 3 cycles */ |
| 97 | mov x0, #L2_DATA_RAM_LATENCY_3_CYCLES |
| 98 | cbnz x2, apply_l2_ram_latencies |
| 99 | /* On Juno r0, also change the L2 Tag RAM latency to 3 cycles */ |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 100 | orr x0, x0, #(L2_TAG_RAM_LATENCY_3_CYCLES << \ |
| 101 | L2CTLR_TAG_RAM_LATENCY_SHIFT) |
Sandrine Bailleux | fd8f898 | 2015-02-04 14:06:10 +0000 | [diff] [blame] | 102 | apply_l2_ram_latencies: |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 103 | msr L2CTLR_EL1, x0 |
| 104 | |
Sandrine Bailleux | fd8f898 | 2015-02-04 14:06:10 +0000 | [diff] [blame] | 105 | /* Juno r1 doesn't suffer from defect #831273 */ |
| 106 | cbnz x2, ret |
| 107 | |
| 108 | apply_831273: |
| 109 | /* -------------------------------------------------------------------- |
| 110 | * On Juno r0, enable the event stream every 65536 cycles |
| 111 | * -------------------------------------------------------------------- |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 112 | */ |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 113 | mov x0, #(0xf << EVNTI_SHIFT) |
| 114 | orr x0, x0, #EVNTEN_BIT |
| 115 | msr CNTKCTL_EL1, x0 |
Sandrine Bailleux | fd8f898 | 2015-02-04 14:06:10 +0000 | [diff] [blame] | 116 | ret: |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 117 | isb |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 118 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 119 | endfunc plat_reset_handler |
David Wang | 323ebe8 | 2015-10-22 13:30:50 +0800 | [diff] [blame] | 120 | |
| 121 | /* ----------------------------------------------------- |
| 122 | * unsigned int plat_arm_calc_core_pos(uint64_t mpidr) |
| 123 | * Helper function to calculate the core position. |
| 124 | * ----------------------------------------------------- |
| 125 | */ |
| 126 | func plat_arm_calc_core_pos |
| 127 | b css_calc_core_pos_swap_cluster |
| 128 | endfunc plat_arm_calc_core_pos |