blob: f6a40a587f1ba85d705d00c15ba7ba3c29628f5c [file] [log] [blame]
Konstantin Porotchkinede192d2018-10-08 16:48:52 +03001/*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
Konstantin Porotchkinede192d2018-10-08 16:48:52 +03008#include <errno.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <common/debug.h>
11#include <drivers/delay_timer.h>
12#include <lib/mmio.h>
13#include <lib/spinlock.h>
14
Konstantin Porotchkinede192d2018-10-08 16:48:52 +030015#include <mvebu.h>
16#include <mvebu_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017
Konstantin Porotchkinede192d2018-10-08 16:48:52 +030018#include "phy-comphy-3700.h"
19#include "phy-comphy-common.h"
20
21/*
22 * COMPHY_INDIRECT_REG points to ahci address space but the ahci region used in
23 * Linux is up to 0x178 so none will access it from Linux in runtime
24 * concurrently.
25 */
26#define COMPHY_INDIRECT_REG (MVEBU_REGS_BASE + 0xE0178)
27
28/* The USB3_GBE1_PHY range is above USB3 registers used in dts */
29#define USB3_GBE1_PHY (MVEBU_REGS_BASE + 0x5C000)
30#define COMPHY_SD_ADDR (MVEBU_REGS_BASE + 0x1F000)
31
32/*
33 * Below address in used only for reading, therefore no problem with concurrent
34 * Linux access.
35 */
36#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8)
37 #define MVEBU_XTAL_MODE_MASK BIT(9)
38 #define MVEBU_XTAL_MODE_OFFS 9
39 #define MVEBU_XTAL_CLOCK_25MHZ 0x0
40
41struct sgmii_phy_init_data_fix {
42 uint16_t addr;
43 uint16_t value;
44};
45
46/* Changes to 40M1G25 mode data required for running 40M3G125 init mode */
47static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = {
48 {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000},
49 {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030},
50 {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC},
51 {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA},
52 {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550},
53 {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0},
54 {0x104, 0x0C10}
55};
56
57/* 40M1G25 mode init data */
58static uint16_t sgmii_phy_init[512] = {
59 /* 0 1 2 3 4 5 6 7 */
60 /*-----------------------------------------------------------*/
61 /* 8 9 A B C D E F */
62 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */
63 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */
64 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */
65 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */
66 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */
67 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */
68 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
69 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */
70 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */
71 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */
72 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */
73 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */
74 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */
75 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */
76 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */
77 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */
78 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */
79 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */
80 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */
81 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */
82 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */
83 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */
84 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */
85 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */
86 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */
87 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */
88 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */
89 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */
90 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */
91 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */
92 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */
93 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */
94 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */
95 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */
96 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */
97 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */
98 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */
99 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */
100 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */
101 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */
102 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */
103 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */
104 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */
105 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */
106 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */
107 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */
108 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */
109 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */
110 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */
111 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */
112 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */
113 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */
114 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */
115 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */
116 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */
117 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */
118 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */
119 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */
120 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */
121 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */
122 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */
123 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */
124 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */
125 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */
126};
127
128/* returns reference clock in MHz (25 or 40) */
129static uint32_t get_ref_clk(void)
130{
131 uint32_t val;
132
133 val = (mmio_read_32(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
134 MVEBU_XTAL_MODE_OFFS;
135
136 if (val == MVEBU_XTAL_CLOCK_25MHZ)
137 return 25;
138 else
139 return 40;
140}
141
142/* PHY selector configures with corresponding modes */
143static void mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index,
144 uint32_t comphy_mode)
145{
146 uint32_t reg;
147 int mode = COMPHY_GET_MODE(comphy_mode);
148
149 reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG);
150 switch (mode) {
151 case (COMPHY_SATA_MODE):
152 /* SATA must be in Lane2 */
153 if (comphy_index == COMPHY_LANE2)
154 reg &= ~COMPHY_SELECTOR_USB3_PHY_SEL_BIT;
155 else
156 goto error;
157 break;
158
159 case (COMPHY_SGMII_MODE):
160 case (COMPHY_HS_SGMII_MODE):
161 if (comphy_index == COMPHY_LANE0)
162 reg &= ~COMPHY_SELECTOR_USB3_GBE1_SEL_BIT;
163 else if (comphy_index == COMPHY_LANE1)
164 reg &= ~COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT;
165 else
166 goto error;
167 break;
168
169 case (COMPHY_USB3H_MODE):
170 case (COMPHY_USB3D_MODE):
171 case (COMPHY_USB3_MODE):
172 if (comphy_index == COMPHY_LANE2)
173 reg |= COMPHY_SELECTOR_USB3_PHY_SEL_BIT;
174 else if (comphy_index == COMPHY_LANE0)
175 reg |= COMPHY_SELECTOR_USB3_GBE1_SEL_BIT;
176 else
177 goto error;
178 break;
179
180 case (COMPHY_PCIE_MODE):
181 /* PCIE must be in Lane1 */
182 if (comphy_index == COMPHY_LANE1)
183 reg |= COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT;
184 else
185 goto error;
186 break;
187
188 default:
189 goto error;
190 }
191
192 mmio_write_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG, reg);
193 return;
194error:
195 ERROR("COMPHY[%d] mode[%d] is invalid\n", comphy_index, mode);
196}
197
Marek BehĂșn4f94cbc2019-11-05 15:21:54 +0100198/*
199 * This is something like the inverse of the previous function: for given
200 * lane it returns COMPHY_*_MODE.
201 *
202 * It is useful when powering the phy off.
203 *
204 * This function returns COMPHY_USB3_MODE even if the phy was configured
205 * with COMPHY_USB3D_MODE or COMPHY_USB3H_MODE. (The usb3 phy initialization
206 * code does not differentiate between these modes.)
207 * Also it returns COMPHY_SGMII_MODE even if the phy was configures with
208 * COMPHY_HS_SGMII_MODE. (The sgmii phy initialization code does differentiate
209 * between these modes, but it is irrelevant when powering the phy off.)
210 */
211static int mvebu_a3700_comphy_get_mode(uint8_t comphy_index)
212{
213 uint32_t reg;
214
215 reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG);
216 switch (comphy_index) {
217 case COMPHY_LANE0:
218 if ((reg & COMPHY_SELECTOR_USB3_GBE1_SEL_BIT) != 0)
219 return COMPHY_USB3_MODE;
220 else
221 return COMPHY_SGMII_MODE;
222 case COMPHY_LANE1:
223 if ((reg & COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT) != 0)
224 return COMPHY_PCIE_MODE;
225 else
226 return COMPHY_SGMII_MODE;
227 case COMPHY_LANE2:
228 if ((reg & COMPHY_SELECTOR_USB3_PHY_SEL_BIT) != 0)
229 return COMPHY_USB3_MODE;
230 else
231 return COMPHY_SATA_MODE;
232 }
233
234 return COMPHY_UNUSED;
235}
236
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300237/* It is only used for SATA and USB3 on comphy lane2. */
238static void comphy_set_indirect(uintptr_t addr, uint32_t offset, uint16_t data,
239 uint16_t mask, int mode)
240{
241 /*
242 * When Lane 2 PHY is for USB3, access the PHY registers
243 * through indirect Address and Data registers:
244 * INDIR_ACC_PHY_ADDR (RD00E0178h [31:0]),
245 * INDIR_ACC_PHY_DATA (RD00E017Ch [31:0]),
246 * within the SATA Host Controller registers, Lane 2 base register
247 * offset is 0x200
248 */
249 if (mode == COMPHY_UNUSED)
250 return;
251
252 if (mode == COMPHY_SATA_MODE)
253 mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, offset);
254 else
255 mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET,
256 offset + USB3PHY_LANE2_REG_BASE_OFFSET);
257
258 reg_set(addr + COMPHY_LANE2_INDIR_DATA_OFFSET, data, mask);
259}
260
261/* It is only used USB3 direct access not on comphy lane2. */
262static void comphy_usb3_set_direct(uintptr_t addr, uint32_t reg_offset,
263 uint16_t data, uint16_t mask, int mode)
264{
265 reg_set16((reg_offset * PHY_SHFT(USB3) + addr), data, mask);
266}
267
268static void comphy_sgmii_phy_init(uint32_t comphy_index, uint32_t mode,
269 uintptr_t sd_ip_addr)
270{
271 const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix);
272 int addr, fix_idx;
273 uint16_t val;
274
275 fix_idx = 0;
276 for (addr = 0; addr < 512; addr++) {
277 /*
278 * All PHY register values are defined in full for 3.125Gbps
279 * SERDES speed. The values required for 1.25 Gbps are almost
280 * the same and only few registers should be "fixed" in
281 * comparison to 3.125 Gbps values. These register values are
282 * stored in "sgmii_phy_init_fix" array.
283 */
284 if ((mode != COMPHY_SGMII_MODE) &&
285 (sgmii_phy_init_fix[fix_idx].addr == addr)) {
286 /* Use new value */
287 val = sgmii_phy_init_fix[fix_idx].value;
288 if (fix_idx < fix_arr_sz)
289 fix_idx++;
290 } else {
291 val = sgmii_phy_init[addr];
292 }
293
294 reg_set16(SGMIIPHY_ADDR(addr, sd_ip_addr), val, 0xFFFF);
295 }
296}
297
298static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index,
299 uint32_t comphy_mode)
300{
301 int ret = 0;
302 uint32_t offset, data = 0, ref_clk;
303 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG;
304 int mode = COMPHY_GET_MODE(comphy_mode);
305 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode);
306
307 debug_enter();
308
309 /* Configure phy selector for SATA */
310 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode);
311
312 /* Clear phy isolation mode to make it work in normal mode */
313 offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET;
314 comphy_set_indirect(comphy_indir_regs, offset, 0, PHY_ISOLATE_MODE,
315 mode);
316
317 /* 0. Check the Polarity invert bits */
318 if (invert & COMPHY_POLARITY_TXD_INVERT)
319 data |= TXD_INVERT_BIT;
320 if (invert & COMPHY_POLARITY_RXD_INVERT)
321 data |= RXD_INVERT_BIT;
322
323 offset = COMPHY_SYNC_PATTERN_REG + SATAPHY_LANE2_REG_BASE_OFFSET;
324 comphy_set_indirect(comphy_indir_regs, offset, data, TXD_INVERT_BIT |
325 RXD_INVERT_BIT, mode);
326
327 /* 1. Select 40-bit data width width */
328 offset = COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET;
329 comphy_set_indirect(comphy_indir_regs, offset, DATA_WIDTH_40BIT,
330 SEL_DATA_WIDTH_MASK, mode);
331
332 /* 2. Select reference clock(25M) and PHY mode (SATA) */
333 offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
334 if (get_ref_clk() == 40)
335 ref_clk = REF_CLOCK_SPEED_40M;
336 else
337 ref_clk = REF_CLOCK_SPEED_25M;
338
339 comphy_set_indirect(comphy_indir_regs, offset, ref_clk | PHY_MODE_SATA,
340 REF_FREF_SEL_MASK | PHY_MODE_MASK, mode);
341
342 /* 3. Use maximum PLL rate (no power save) */
343 offset = COMPHY_KVCO_CAL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
344 comphy_set_indirect(comphy_indir_regs, offset, USE_MAX_PLL_RATE_BIT,
345 USE_MAX_PLL_RATE_BIT, mode);
346
347 /* 4. Reset reserved bit */
348 comphy_set_indirect(comphy_indir_regs, COMPHY_RESERVED_REG, 0,
349 PHYCTRL_FRM_PIN_BIT, mode);
350
351 /* 5. Set vendor-specific configuration (It is done in sata driver) */
352 /* XXX: in U-Boot below sequence was executed in this place, in Linux
353 * not. Now it is done only in U-Boot before this comphy
354 * initialization - tests shows that it works ok, but in case of any
355 * future problem it is left for reference.
356 * reg_set(MVEBU_REGS_BASE + 0xe00a0, 0, 0xffffffff);
357 * reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6));
358 */
359
360 /* Wait for > 55 us to allow PLL be enabled */
361 udelay(PLL_SET_DELAY_US);
362
363 /* Polling status */
364 mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET,
365 COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET);
366
367 ret = polling_with_timeout(comphy_indir_regs +
368 COMPHY_LANE2_INDIR_DATA_OFFSET,
369 PLL_READY_TX_BIT, PLL_READY_TX_BIT,
370 COMPHY_PLL_TIMEOUT, REG_32BIT);
371
372 debug_exit();
373
374 return ret;
375}
376
377static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index,
378 uint32_t comphy_mode)
379{
380 int ret = 0;
381 uint32_t mask, data, offset;
382 uintptr_t sd_ip_addr;
383 int mode = COMPHY_GET_MODE(comphy_mode);
384 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode);
385
386 debug_enter();
387
388 /* Set selector */
389 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode);
390
391 /* Serdes IP Base address
392 * COMPHY Lane0 -- USB3/GBE1
393 * COMPHY Lane1 -- PCIe/GBE0
394 */
395 if (comphy_index == COMPHY_LANE0) {
396 /* Get usb3 and gbe */
397 sd_ip_addr = USB3_GBE1_PHY;
398 } else
399 sd_ip_addr = COMPHY_SD_ADDR;
400
401 /*
402 * 1. Reset PHY by setting PHY input port PIN_RESET=1.
403 * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep
404 * PHY TXP/TXN output to idle state during PHY initialization
405 * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0.
406 */
407 data = PIN_PU_IVEREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT;
408 mask = PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT |
409 PIN_PU_TX_BIT;
410 offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index);
411 reg_set(offset, data, mask);
412
413 /* 4. Release reset to the PHY by setting PIN_RESET=0. */
414 data = 0;
415 mask = PIN_RESET_COMPHY_BIT;
416 reg_set(offset, data, mask);
417
418 /*
419 * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY
420 * bit rate
421 */
422 if (mode == COMPHY_SGMII_MODE) {
423 /* SGMII 1G, SerDes speed 1.25G */
424 data |= SD_SPEED_1_25_G << GEN_RX_SEL_OFFSET;
425 data |= SD_SPEED_1_25_G << GEN_TX_SEL_OFFSET;
426 } else if (mode == COMPHY_HS_SGMII_MODE) {
427 /* HS SGMII (2.5G), SerDes speed 3.125G */
428 data |= SD_SPEED_2_5_G << GEN_RX_SEL_OFFSET;
429 data |= SD_SPEED_2_5_G << GEN_TX_SEL_OFFSET;
430 } else {
431 /* Other rates are not supported */
432 ERROR("unsupported SGMII speed on comphy lane%d\n",
433 comphy_index);
434 return -EINVAL;
435 }
436 mask = GEN_RX_SEL_MASK | GEN_TX_SEL_MASK;
437 reg_set(offset, data, mask);
438
439 /*
440 * 6. Wait 10mS for bandgap and reference clocks to stabilize; then
441 * start SW programming.
442 */
443 mdelay(10);
444
445 /* 7. Program COMPHY register PHY_MODE */
446 data = PHY_MODE_SGMII;
447 mask = PHY_MODE_MASK;
448 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask);
449
450 /*
451 * 8. Set COMPHY register REFCLK_SEL to select the correct REFCLK
452 * source
453 */
454 data = 0;
455 mask = PHY_REF_CLK_SEL;
456 reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_REG0_ADDR, sd_ip_addr), data, mask);
457
458 /*
459 * 9. Set correct reference clock frequency in COMPHY register
460 * REF_FREF_SEL.
461 */
462 if (get_ref_clk() == 40)
463 data = REF_CLOCK_SPEED_50M;
464 else
465 data = REF_CLOCK_SPEED_25M;
466
467 mask = REF_FREF_SEL_MASK;
468 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask);
469
470 /* 10. Program COMPHY register PHY_GEN_MAX[1:0]
471 * This step is mentioned in the flow received from verification team.
472 * However the PHY_GEN_MAX value is only meaningful for other interfaces
473 * (not SGMII). For instance, it selects SATA speed 1.5/3/6 Gbps or PCIe
474 * speed 2.5/5 Gbps
475 */
476
477 /*
478 * 11. Program COMPHY register SEL_BITS to set correct parallel data
479 * bus width
480 */
481 data = DATA_WIDTH_10BIT;
482 mask = SEL_DATA_WIDTH_MASK;
483 reg_set16(SGMIIPHY_ADDR(COMPHY_LOOPBACK_REG0, sd_ip_addr), data, mask);
484
485 /*
486 * 12. As long as DFE function needs to be enabled in any mode,
487 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F
488 * for real chip during COMPHY power on.
489 * The step 14 exists (and empty) in the original initialization flow
490 * obtained from the verification team. According to the functional
491 * specification DFE_UPDATE_EN already has the default value 0x3F
492 */
493
494 /*
495 * 13. Program COMPHY GEN registers.
496 * These registers should be programmed based on the lab testing result
497 * to achieve optimal performance. Please contact the CEA group to get
498 * the related GEN table during real chip bring-up. We only required to
499 * run though the entire registers programming flow defined by
500 * "comphy_sgmii_phy_init" when the REF clock is 40 MHz. For REF clock
501 * 25 MHz the default values stored in PHY registers are OK.
502 */
503 debug("Running C-DPI phy init %s mode\n",
504 mode == COMPHY_HS_SGMII_MODE ? "2G5" : "1G");
505 if (get_ref_clk() == 40)
506 comphy_sgmii_phy_init(comphy_index, mode, sd_ip_addr);
507
508 /*
509 * 14. [Simulation Only] should not be used for real chip.
510 * By pass power up calibration by programming EXT_FORCE_CAL_DONE
511 * (R02h[9]) to 1 to shorten COMPHY simulation time.
512 */
513
514 /*
515 * 15. [Simulation Only: should not be used for real chip]
516 * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX training
517 * simulation time.
518 */
519
520 /*
521 * 16. Check the PHY Polarity invert bit
522 */
523 data = 0x0;
524 if (invert & COMPHY_POLARITY_TXD_INVERT)
525 data |= TXD_INVERT_BIT;
526 if (invert & COMPHY_POLARITY_RXD_INVERT)
527 data |= RXD_INVERT_BIT;
528 reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN_REG, sd_ip_addr), data, 0);
529
530 /*
531 * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to
532 * start PHY power up sequence. All the PHY register programming should
533 * be done before PIN_PU_PLL=1. There should be no register programming
534 * for normal PHY operation from this point.
535 */
536 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index),
537 PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT,
538 PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT);
539
540 /*
541 * 18. Wait for PHY power up sequence to finish by checking output ports
542 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1.
543 */
544 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE +
545 COMPHY_PHY_STATUS_OFFSET(comphy_index),
546 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT,
547 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT,
548 COMPHY_PLL_TIMEOUT, REG_32BIT);
549 if (ret)
550 ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index);
551
552 /*
553 * 19. Set COMPHY input port PIN_TX_IDLE=0
554 */
555 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index),
556 0x0, PIN_TX_IDLE_BIT);
557
558 /*
559 * 20. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To
560 * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the
561 * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to
562 * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please
563 * refer to RX initialization part for details.
564 */
565 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index),
566 PHY_RX_INIT_BIT, 0x0);
567
568 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE +
569 COMPHY_PHY_STATUS_OFFSET(comphy_index),
570 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT,
571 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT,
572 COMPHY_PLL_TIMEOUT, REG_32BIT);
573 if (ret)
574 ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index);
575
576
577 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE +
578 COMPHY_PHY_STATUS_OFFSET(comphy_index),
579 PHY_RX_INIT_DONE_BIT, PHY_RX_INIT_DONE_BIT,
580 COMPHY_PLL_TIMEOUT, REG_32BIT);
581 if (ret)
582 ERROR("Failed to init RX of SGMII PHY %d\n", comphy_index);
583
584 debug_exit();
585
586 return ret;
587}
588
Marek BehĂșn4f94cbc2019-11-05 15:21:54 +0100589static int mvebu_a3700_comphy_sgmii_power_off(uint8_t comphy_index)
590{
591 int ret = 0;
592 uint32_t mask, data, offset;
593
594 debug_enter();
595
596 data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT;
597 mask = 0;
598 offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index);
599 reg_set(offset, data, mask);
600
601 debug_exit();
602
603 return ret;
604}
605
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300606static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
607 uint32_t comphy_mode)
608{
609 int ret = 0;
610 uintptr_t reg_base = 0;
611 uint32_t mask, data, addr, cfg, ref_clk;
612 void (*usb3_reg_set)(uintptr_t addr, uint32_t reg_offset, uint16_t data,
613 uint16_t mask, int mode);
614 int mode = COMPHY_GET_MODE(comphy_mode);
615 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode);
616
617 debug_enter();
618
619 /* Set phy seclector */
620 mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode);
621
622 /* Set usb3 reg access func, Lane2 is indirect access */
623 if (comphy_index == COMPHY_LANE2) {
624 usb3_reg_set = &comphy_set_indirect;
625 reg_base = COMPHY_INDIRECT_REG;
626 } else {
627 /* Get the direct access register resource and map */
628 usb3_reg_set = &comphy_usb3_set_direct;
629 reg_base = USB3_GBE1_PHY;
630 }
631
632 /*
633 * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The
634 * register belong to UTMI module, so it is set in UTMI phy driver.
635 */
636
637 /*
638 * 1. Set PRD_TXDEEMPH (3.5db de-emph)
639 */
640 mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK |
641 CFG_TX_ALIGN_POS_MASK;
642 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG0_ADDR, PRD_TXDEEMPH0_MASK,
643 mask, mode);
644
645 /*
646 * 2. Set BIT0: enable transmitter in high impedance mode
647 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency
648 * Set BIT6: Tx detect Rx at HiZ mode
649 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db
650 * together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR register
651 */
652 mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK |
653 TX_ELEC_IDLE_MODE_EN;
654 data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN;
655 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG1_ADDR, data, mask, mode);
656
657 /*
658 * 3. Set Spread Spectrum Clock Enabled
659 */
660 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG4_ADDR,
661 SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN, mode);
662
663 /*
664 * 4. Set Override Margining Controls From the MAC:
665 * Use margining signals from lane configuration
666 */
667 usb3_reg_set(reg_base, COMPHY_REG_TEST_MODE_CTRL_ADDR,
668 MODE_MARGIN_OVERRIDE, REG_16_BIT_MASK, mode);
669
670 /*
671 * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles
672 * set Mode Clock Source = PCLK is generated from REFCLK
673 */
674 usb3_reg_set(reg_base, COMPHY_REG_GLOB_CLK_SRC_LO_ADDR, 0x0,
675 (MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE |
676 BUNDLE_SAMPLE_CTRL | PLL_READY_DLY), mode);
677
678 /*
679 * 6. Set G2 Spread Spectrum Clock Amplitude at 4K
680 */
681 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_2,
682 G2_TX_SSC_AMP_VALUE_20, G2_TX_SSC_AMP_MASK, mode);
683
684 /*
685 * 7. Unset G3 Spread Spectrum Clock Amplitude
686 * set G3 TX and RX Register Master Current Select
687 */
688 mask = G3_TX_SSC_AMP_MASK | G3_VREG_RXTX_MAS_ISET_MASK |
689 RSVD_PH03FH_6_0_MASK;
690 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_3,
691 G3_VREG_RXTX_MAS_ISET_60U, mask, mode);
692
693 /*
694 * 8. Check crystal jumper setting and program the Power and PLL Control
695 * accordingly Change RX wait
696 */
697 if (get_ref_clk() == 40) {
698 ref_clk = REF_CLOCK_SPEED_40M;
699 cfg = CFG_PM_RXDLOZ_WAIT_12_UNIT;
700
701 } else {
702 /* 25 MHz */
703 ref_clk = USB3_REF_CLOCK_SPEED_25M;
704 cfg = CFG_PM_RXDLOZ_WAIT_7_UNIT;
705 }
706
707 mask = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |
708 PU_TX_INTP_BIT | PU_DFE_BIT | PLL_LOCK_BIT | PHY_MODE_MASK |
709 REF_FREF_SEL_MASK;
710 data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |
711 PU_TX_INTP_BIT | PU_DFE_BIT | PHY_MODE_USB3 | ref_clk;
712 usb3_reg_set(reg_base, COMPHY_POWER_PLL_CTRL, data, mask, mode);
713
714 mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK |
715 CFG_PM_RXDLOZ_WAIT_MASK;
716 data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg;
717 usb3_reg_set(reg_base, COMPHY_REG_PWR_MGM_TIM1_ADDR, data, mask, mode);
718
719 /*
720 * 9. Enable idle sync
721 */
722 data = UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN;
723 usb3_reg_set(reg_base, COMPHY_REG_UNIT_CTRL_ADDR, data, REG_16_BIT_MASK,
724 mode);
725
726 /*
727 * 10. Enable the output of 500M clock
728 */
729 data = MISC_REG0_DEFAULT_VALUE | CLK500M_EN;
730 usb3_reg_set(reg_base, COMPHY_MISC_REG0_ADDR, data, REG_16_BIT_MASK,
731 mode);
732
733 /*
734 * 11. Set 20-bit data width
735 */
736 usb3_reg_set(reg_base, COMPHY_LOOPBACK_REG0, DATA_WIDTH_20BIT,
737 REG_16_BIT_MASK, mode);
738
739 /*
740 * 12. Override Speed_PLL value and use MAC PLL
741 */
742 usb3_reg_set(reg_base, COMPHY_KVCO_CAL_CTRL,
743 (SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT),
744 REG_16_BIT_MASK, mode);
745
746 /*
747 * 13. Check the Polarity invert bit
748 */
749 if (invert & COMPHY_POLARITY_TXD_INVERT)
750 usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, TXD_INVERT_BIT,
751 TXD_INVERT_BIT, mode);
752 if (invert & COMPHY_POLARITY_RXD_INVERT)
753 usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, RXD_INVERT_BIT,
754 RXD_INVERT_BIT, mode);
755
756 /*
757 * 14. Set max speed generation to USB3.0 5Gbps
758 */
759 usb3_reg_set(reg_base, COMPHY_SYNC_MASK_GEN_REG, PHY_GEN_USB3_5G,
760 PHY_GEN_MAX_MASK, mode);
761
762 /*
763 * 15. Set capacitor value for FFE gain peaking to 0xF
764 */
765 usb3_reg_set(reg_base, COMPHY_REG_GEN3_SETTINGS_3,
766 COMPHY_GEN_FFE_CAP_SEL_VALUE, COMPHY_GEN_FFE_CAP_SEL_MASK,
767 mode);
768
769 /*
770 * 16. Release SW reset
771 */
772 data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4;
773 usb3_reg_set(reg_base, COMPHY_REG_GLOB_PHY_CTRL0_ADDR, data,
774 REG_16_BIT_MASK, mode);
775
776 /* Wait for > 55 us to allow PCLK be enabled */
777 udelay(PLL_SET_DELAY_US);
778
779 if (comphy_index == COMPHY_LANE2) {
Marek BehĂșn718e02c2019-10-08 17:36:14 +0200780 data = COMPHY_REG_LANE_STATUS1_ADDR + USB3PHY_LANE2_REG_BASE_OFFSET;
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300781 mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET,
782 data);
783
Marek BehĂșn718e02c2019-10-08 17:36:14 +0200784 addr = reg_base + COMPHY_LANE2_INDIR_DATA_OFFSET;
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300785 ret = polling_with_timeout(addr, TXDCLK_PCLK_EN, TXDCLK_PCLK_EN,
786 COMPHY_PLL_TIMEOUT, REG_32BIT);
787 } else {
788 ret = polling_with_timeout(LANE_STATUS1_ADDR(USB3) + reg_base,
789 TXDCLK_PCLK_EN, TXDCLK_PCLK_EN,
790 COMPHY_PLL_TIMEOUT, REG_16BIT);
791 }
792 if (ret)
793 ERROR("Failed to lock USB3 PLL\n");
794
795 debug_exit();
796
797 return ret;
798}
799
800static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index,
801 uint32_t comphy_mode)
802{
803 int ret;
804 uint32_t ref_clk;
805 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode);
806
807 debug_enter();
808
809 /* 1. Enable max PLL. */
810 reg_set16(LANE_CFG1_ADDR(PCIE) + COMPHY_SD_ADDR,
811 USE_MAX_PLL_RATE_EN, 0x0);
812
813 /* 2. Select 20 bit SERDES interface. */
814 reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR,
815 CFG_SEL_20B, 0);
816
817 /* 3. Force to use reg setting for PCIe mode */
818 reg_set16(MISC_REG1_ADDR(PCIE) + COMPHY_SD_ADDR,
819 SEL_BITS_PCIE_FORCE, 0);
820
821 /* 4. Change RX wait */
822 reg_set16(PWR_MGM_TIM1_ADDR(PCIE) + COMPHY_SD_ADDR,
823 CFG_PM_RXDEN_WAIT_1_UNIT | CFG_PM_RXDLOZ_WAIT_12_UNIT,
824 (CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK |
825 CFG_PM_RXDLOZ_WAIT_MASK));
826
827 /* 5. Enable idle sync */
828 reg_set16(UNIT_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR,
829 UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN, REG_16_BIT_MASK);
830
831 /* 6. Enable the output of 100M/125M/500M clock */
832 reg_set16(MISC_REG0_ADDR(PCIE) + COMPHY_SD_ADDR,
833 MISC_REG0_DEFAULT_VALUE | CLK500M_EN | CLK100M_125M_EN,
834 REG_16_BIT_MASK);
835
836 /*
837 * 7. Enable TX, PCIE global register, 0xd0074814, it is done in
838 * PCI-E driver
839 */
840
841 /*
842 * 8. Check crystal jumper setting and program the Power and PLL
843 * Control accordingly
844 */
845
846 if (get_ref_clk() == 40)
847 ref_clk = REF_CLOCK_SPEED_40M;
848 else
849 ref_clk = PCIE_REF_CLOCK_SPEED_25M;
850
851 reg_set16(PWR_PLL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR,
852 (PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |
853 PU_TX_INTP_BIT | PU_DFE_BIT | ref_clk | PHY_MODE_PCIE),
854 REG_16_BIT_MASK);
855
856 /* 9. Override Speed_PLL value and use MAC PLL */
857 reg_set16(KVCO_CAL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR,
858 SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT, REG_16_BIT_MASK);
859
860 /* 10. Check the Polarity invert bit */
861 if (invert & COMPHY_POLARITY_TXD_INVERT)
862 reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR,
863 TXD_INVERT_BIT, 0x0);
864
865 if (invert & COMPHY_POLARITY_RXD_INVERT)
866 reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR,
867 RXD_INVERT_BIT, 0x0);
868
869 /* 11. Release SW reset */
870 reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR,
871 MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32,
872 SOFT_RESET | MODE_REFDIV);
873
874 /* Wait for > 55 us to allow PCLK be enabled */
875 udelay(PLL_SET_DELAY_US);
876
877 ret = polling_with_timeout(LANE_STATUS1_ADDR(PCIE) + COMPHY_SD_ADDR,
878 TXDCLK_PCLK_EN, TXDCLK_PCLK_EN,
879 COMPHY_PLL_TIMEOUT, REG_16BIT);
880 if (ret)
881 ERROR("Failed to lock PCIE PLL\n");
882
883 debug_exit();
884
885 return ret;
886}
887
888int mvebu_3700_comphy_power_on(uint8_t comphy_index, uint32_t comphy_mode)
889{
890 int mode = COMPHY_GET_MODE(comphy_mode);
891 int ret = 0;
892
893 debug_enter();
894
895 switch (mode) {
896 case(COMPHY_SATA_MODE):
897 ret = mvebu_a3700_comphy_sata_power_on(comphy_index,
898 comphy_mode);
899 break;
900 case(COMPHY_SGMII_MODE):
901 case(COMPHY_HS_SGMII_MODE):
902 ret = mvebu_a3700_comphy_sgmii_power_on(comphy_index,
903 comphy_mode);
904 break;
905 case (COMPHY_USB3_MODE):
906 case (COMPHY_USB3H_MODE):
907 ret = mvebu_a3700_comphy_usb3_power_on(comphy_index,
908 comphy_mode);
909 break;
910 case (COMPHY_PCIE_MODE):
911 ret = mvebu_a3700_comphy_pcie_power_on(comphy_index,
912 comphy_mode);
913 break;
914 default:
915 ERROR("comphy%d: unsupported comphy mode\n", comphy_index);
916 ret = -EINVAL;
917 break;
918 }
919
920 debug_exit();
921
922 return ret;
923}
924
925static int mvebu_a3700_comphy_usb3_power_off(void)
926{
927 /*
928 * Currently the USB3 MAC will control the USB3 PHY to set it to low
929 * state, thus do not need to power off USB3 PHY again.
930 */
931 debug_enter();
932 debug_exit();
933
934 return 0;
935}
936
937static int mvebu_a3700_comphy_sata_power_off(uint32_t comphy_mode)
938{
939 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG;
940 int mode = COMPHY_GET_MODE(comphy_mode);
941 uint32_t offset;
942
943 debug_enter();
944
945 /* Set phy isolation mode */
946 offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET;
947 comphy_set_indirect(comphy_indir_regs, offset, PHY_ISOLATE_MODE,
948 PHY_ISOLATE_MODE, mode);
949
950 /* Power off PLL, Tx, Rx */
951 offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
952 comphy_set_indirect(comphy_indir_regs, offset, 0,
953 PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT, mode);
954
955 debug_exit();
956
957 return 0;
958}
959
960int mvebu_3700_comphy_power_off(uint8_t comphy_index, uint32_t comphy_mode)
961{
962 int mode = COMPHY_GET_MODE(comphy_mode);
963 int err = 0;
964
965 debug_enter();
966
Marek BehĂșn4f94cbc2019-11-05 15:21:54 +0100967 if (!mode) {
968 /*
969 * The user did not specify which mode should be powered off.
970 * In this case we can identify this by reading the phy selector
971 * register.
972 */
973 mode = mvebu_a3700_comphy_get_mode(comphy_index);
974 }
975
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300976 switch (mode) {
Marek BehĂșn4f94cbc2019-11-05 15:21:54 +0100977 case(COMPHY_SGMII_MODE):
978 case(COMPHY_HS_SGMII_MODE):
979 err = mvebu_a3700_comphy_sgmii_power_off(comphy_index);
980 break;
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300981 case (COMPHY_USB3_MODE):
982 case (COMPHY_USB3H_MODE):
983 err = mvebu_a3700_comphy_usb3_power_off();
984 break;
985 case (COMPHY_SATA_MODE):
986 err = mvebu_a3700_comphy_sata_power_off(comphy_mode);
987 break;
988
989 default:
990 debug("comphy%d: power off is not implemented for mode %d\n",
991 comphy_index, mode);
992 break;
993 }
994
995 debug_exit();
996
997 return err;
998}
999
1000static int mvebu_a3700_comphy_sata_is_pll_locked(void)
1001{
1002 uint32_t data, addr;
1003 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG;
1004 int ret = 0;
1005
1006 debug_enter();
1007
1008 /* Polling status */
1009 mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET,
1010 COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET);
1011 addr = comphy_indir_regs + COMPHY_LANE2_INDIR_DATA_OFFSET;
1012 data = polling_with_timeout(addr, PLL_READY_TX_BIT, PLL_READY_TX_BIT,
1013 COMPHY_PLL_TIMEOUT, REG_32BIT);
1014
1015 if (data != 0) {
1016 ERROR("TX PLL is not locked\n");
1017 ret = -ETIMEDOUT;
1018 }
1019
1020 debug_exit();
1021
1022 return ret;
1023}
1024
1025int mvebu_3700_comphy_is_pll_locked(uint8_t comphy_index, uint32_t comphy_mode)
1026{
1027 int mode = COMPHY_GET_MODE(comphy_mode);
1028 int ret = 0;
1029
1030 debug_enter();
1031
1032 switch (mode) {
1033 case(COMPHY_SATA_MODE):
1034 ret = mvebu_a3700_comphy_sata_is_pll_locked();
1035 break;
1036
1037 default:
1038 ERROR("comphy[%d] mode[%d] doesn't support PLL lock check\n",
1039 comphy_index, mode);
1040 ret = -EINVAL;
1041 break;
1042 }
1043
1044 debug_exit();
1045
1046 return ret;
1047}