blob: 0215290289d507add0654938c4fdffd838c68700 [file] [log] [blame]
Harry Liebel43ef4f12013-10-22 17:29:14 +01001/*
Antonio Nino Diaz430147a2016-02-22 16:44:41 +00002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Harry Liebel43ef4f12013-10-22 17:29:14 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
Antonio Nino Diaz493bf332016-12-14 14:31:32 +000014 * Neither the name of ARM nor the names of its contributors may be used
Harry Liebel43ef4f12013-10-22 17:29:14 +010015 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31/dts-v1/;
32
33/memreserve/ 0x80000000 0x00010000;
34
35/ {
36};
37
38/ {
Harry Liebelcef93392014-04-01 19:27:38 +010039 model = "FVP Foundation";
Harry Liebel43ef4f12013-10-22 17:29:14 +010040 compatible = "arm,fvp-base", "arm,vexpress";
41 interrupt-parent = <&gic>;
42 #address-cells = <2>;
43 #size-cells = <2>;
44
45 chosen { };
46
47 aliases {
48 serial0 = &v2m_serial0;
49 serial1 = &v2m_serial1;
50 serial2 = &v2m_serial2;
51 serial3 = &v2m_serial3;
52 };
53
54 psci {
Soby Mathew1df077b2015-01-15 11:49:58 +000055 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
Harry Liebel43ef4f12013-10-22 17:29:14 +010056 method = "smc";
57 cpu_suspend = <0xc4000001>;
58 cpu_off = <0x84000002>;
59 cpu_on = <0xc4000003>;
Juan Castillo4dc4a472014-08-12 11:17:06 +010060 sys_poweroff = <0x84000008>;
61 sys_reset = <0x84000009>;
Harry Liebel43ef4f12013-10-22 17:29:14 +010062 };
63
64 cpus {
65 #address-cells = <2>;
66 #size-cells = <0>;
67
Achin Gupta5ab4fe42014-08-20 17:33:09 +010068 cpu-map {
69 cluster0 {
70 core0 {
71 cpu = <&CPU0>;
72 };
73 core1 {
74 cpu = <&CPU1>;
75 };
76 core2 {
77 cpu = <&CPU2>;
78 };
79 core3 {
80 cpu = <&CPU3>;
81 };
82 };
83 };
84
85 idle-states {
86 entry-method = "arm,psci";
87
88 CPU_SLEEP_0: cpu-sleep-0 {
89 compatible = "arm,idle-state";
Juan Castillo3414f542015-04-16 14:17:49 +010090 local-timer-stop;
91 arm,psci-suspend-param = <0x0010000>;
Achin Gupta5ab4fe42014-08-20 17:33:09 +010092 entry-latency-us = <40>;
93 exit-latency-us = <100>;
94 min-residency-us = <150>;
95 };
96
97 CLUSTER_SLEEP_0: cluster-sleep-0 {
98 compatible = "arm,idle-state";
Juan Castillo3414f542015-04-16 14:17:49 +010099 local-timer-stop;
100 arm,psci-suspend-param = <0x1010000>;
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100101 entry-latency-us = <500>;
102 exit-latency-us = <1000>;
103 min-residency-us = <2500>;
104 };
105 };
106
107 CPU0:cpu@0 {
Harry Liebel43ef4f12013-10-22 17:29:14 +0100108 device_type = "cpu";
109 compatible = "arm,armv8";
110 reg = <0x0 0x0>;
111 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100112 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000113 next-level-cache = <&L2_0>;
Harry Liebel43ef4f12013-10-22 17:29:14 +0100114 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100115
116 CPU1:cpu@1 {
Harry Liebel43ef4f12013-10-22 17:29:14 +0100117 device_type = "cpu";
118 compatible = "arm,armv8";
119 reg = <0x0 0x1>;
120 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100121 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000122 next-level-cache = <&L2_0>;
Harry Liebel43ef4f12013-10-22 17:29:14 +0100123 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100124
125 CPU2:cpu@2 {
Harry Liebel43ef4f12013-10-22 17:29:14 +0100126 device_type = "cpu";
127 compatible = "arm,armv8";
128 reg = <0x0 0x2>;
129 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100130 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000131 next-level-cache = <&L2_0>;
Harry Liebel43ef4f12013-10-22 17:29:14 +0100132 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100133
134 CPU3:cpu@3 {
Harry Liebel43ef4f12013-10-22 17:29:14 +0100135 device_type = "cpu";
136 compatible = "arm,armv8";
137 reg = <0x0 0x3>;
138 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100139 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000140 next-level-cache = <&L2_0>;
141 };
142
143 L2_0: l2-cache0 {
144 compatible = "cache";
Harry Liebel43ef4f12013-10-22 17:29:14 +0100145 };
146 };
147
148 memory@80000000 {
149 device_type = "memory";
Juan Castillo7055ca42014-05-16 15:33:15 +0100150 reg = <0x00000000 0x80000000 0 0x7F000000>,
Harry Liebel43ef4f12013-10-22 17:29:14 +0100151 <0x00000008 0x80000000 0 0x80000000>;
152 };
153
154 gic: interrupt-controller@2f000000 {
155 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
156 #interrupt-cells = <3>;
157 #address-cells = <0>;
158 interrupt-controller;
159 reg = <0x0 0x2f000000 0 0x10000>,
160 <0x0 0x2c000000 0 0x2000>,
161 <0x0 0x2c010000 0 0x2000>,
162 <0x0 0x2c02F000 0 0x2000>;
163 interrupts = <1 9 0xf04>;
164 };
165
166 timer {
167 compatible = "arm,armv8-timer";
168 interrupts = <1 13 0xff01>,
169 <1 14 0xff01>,
170 <1 11 0xff01>,
171 <1 10 0xff01>;
172 clock-frequency = <100000000>;
173 };
174
175 timer@2a810000 {
176 compatible = "arm,armv7-timer-mem";
177 reg = <0x0 0x2a810000 0x0 0x10000>;
178 clock-frequency = <100000000>;
179 #address-cells = <2>;
180 #size-cells = <2>;
181 ranges;
Harry Liebelcef93392014-04-01 19:27:38 +0100182 frame@2a830000 {
183 frame-number = <1>;
184 interrupts = <0 26 4>;
185 reg = <0x0 0x2a830000 0x0 0x10000>;
Harry Liebel43ef4f12013-10-22 17:29:14 +0100186 };
187 };
188
189 pmu {
190 compatible = "arm,armv8-pmuv3";
191 interrupts = <0 60 4>,
192 <0 61 4>,
193 <0 62 4>,
194 <0 63 4>;
195 };
196
197 smb {
198 compatible = "simple-bus";
199
200 #address-cells = <2>;
201 #size-cells = <1>;
202 ranges = <0 0 0 0x08000000 0x04000000>,
203 <1 0 0 0x14000000 0x04000000>,
204 <2 0 0 0x18000000 0x04000000>,
205 <3 0 0 0x1c000000 0x04000000>,
206 <4 0 0 0x0c000000 0x04000000>,
207 <5 0 0 0x10000000 0x04000000>;
208
209 #interrupt-cells = <1>;
210 interrupt-map-mask = <0 0 63>;
211 interrupt-map = <0 0 0 &gic 0 0 4>,
212 <0 0 1 &gic 0 1 4>,
213 <0 0 2 &gic 0 2 4>,
214 <0 0 3 &gic 0 3 4>,
215 <0 0 4 &gic 0 4 4>,
216 <0 0 5 &gic 0 5 4>,
217 <0 0 6 &gic 0 6 4>,
218 <0 0 7 &gic 0 7 4>,
219 <0 0 8 &gic 0 8 4>,
220 <0 0 9 &gic 0 9 4>,
221 <0 0 10 &gic 0 10 4>,
222 <0 0 11 &gic 0 11 4>,
223 <0 0 12 &gic 0 12 4>,
224 <0 0 13 &gic 0 13 4>,
225 <0 0 14 &gic 0 14 4>,
226 <0 0 15 &gic 0 15 4>,
227 <0 0 16 &gic 0 16 4>,
228 <0 0 17 &gic 0 17 4>,
229 <0 0 18 &gic 0 18 4>,
230 <0 0 19 &gic 0 19 4>,
231 <0 0 20 &gic 0 20 4>,
232 <0 0 21 &gic 0 21 4>,
233 <0 0 22 &gic 0 22 4>,
234 <0 0 23 &gic 0 23 4>,
235 <0 0 24 &gic 0 24 4>,
236 <0 0 25 &gic 0 25 4>,
237 <0 0 26 &gic 0 26 4>,
238 <0 0 27 &gic 0 27 4>,
239 <0 0 28 &gic 0 28 4>,
240 <0 0 29 &gic 0 29 4>,
241 <0 0 30 &gic 0 30 4>,
242 <0 0 31 &gic 0 31 4>,
243 <0 0 32 &gic 0 32 4>,
244 <0 0 33 &gic 0 33 4>,
245 <0 0 34 &gic 0 34 4>,
246 <0 0 35 &gic 0 35 4>,
247 <0 0 36 &gic 0 36 4>,
248 <0 0 37 &gic 0 37 4>,
249 <0 0 38 &gic 0 38 4>,
250 <0 0 39 &gic 0 39 4>,
251 <0 0 40 &gic 0 40 4>,
252 <0 0 41 &gic 0 41 4>,
253 <0 0 42 &gic 0 42 4>;
254
255 /include/ "fvp-foundation-motherboard.dtsi"
256 };
257};