blob: b8297fd9313367608ae787f2be295924e50550f6 [file] [log] [blame]
Varun Wadekar28dcc212016-07-20 10:28:51 -07001/*
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +01002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Varun Wadekar3923f882020-05-12 14:04:10 -07003 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekar28dcc212016-07-20 10:28:51 -07004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar28dcc212016-07-20 10:28:51 -07006 */
7
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00008#ifndef TEGRA_PLATFORM_H
9#define TEGRA_PLATFORM_H
Varun Wadekar28dcc212016-07-20 10:28:51 -070010
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010011#include <cdefs.h>
Ambroise Vincentffbf32a2019-03-28 09:01:18 +000012#include <lib/utils_def.h>
Anthony Zhou70262ef2017-03-22 14:37:04 +080013#include <stdbool.h>
Marvin Hsu589a7e12017-04-12 20:40:27 +080014
15/*******************************************************************************
16 * Tegra major, minor version helper macros
17 ******************************************************************************/
18#define MAJOR_VERSION_SHIFT U(0x4)
19#define MAJOR_VERSION_MASK U(0xF)
20#define MINOR_VERSION_SHIFT U(0x10)
21#define MINOR_VERSION_MASK U(0xF)
22#define CHIP_ID_SHIFT U(8)
23#define CHIP_ID_MASK U(0xFF)
24#define PRE_SI_PLATFORM_SHIFT U(0x14)
25#define PRE_SI_PLATFORM_MASK U(0xF)
Varun Wadekar28dcc212016-07-20 10:28:51 -070026
Harvey Hsieh6dc0d762017-04-24 19:35:51 +080027/*******************************************************************************
Marvin Hsu589a7e12017-04-12 20:40:27 +080028 * Tegra chip ID values
Harvey Hsieh6dc0d762017-04-24 19:35:51 +080029 ******************************************************************************/
30#define TEGRA_CHIPID_TEGRA13 U(0x13)
31#define TEGRA_CHIPID_TEGRA21 U(0x21)
32#define TEGRA_CHIPID_TEGRA18 U(0x18)
David Pu819975f2019-08-05 17:00:31 -070033#define TEGRA_CHIPID_TEGRA19 U(0x19)
Harvey Hsieh6dc0d762017-04-24 19:35:51 +080034
Varun Wadekar3923f882020-05-12 14:04:10 -070035/*******************************************************************************
36 * JEDEC Standard Manufacturer's Identification Code and Bank ID
37 ******************************************************************************/
38#define JEDEC_NVIDIA_MFID U(0x6B)
39#define JEDEC_NVIDIA_BKID U(3)
40
Julius Werner53456fc2019-07-09 13:49:11 -070041#ifndef __ASSEMBLER__
Harvey Hsieh6dc0d762017-04-24 19:35:51 +080042
43/*
44 * Tegra chip ID major/minor identifiers
Varun Wadekarfc9b91e2017-03-10 09:53:37 -080045 */
46uint32_t tegra_get_chipid_major(void);
47uint32_t tegra_get_chipid_minor(void);
48
49/*
Marvin Hsu589a7e12017-04-12 20:40:27 +080050 * Tegra chip ID identifiers
Varun Wadekar28dcc212016-07-20 10:28:51 -070051 */
Marvin Hsu589a7e12017-04-12 20:40:27 +080052bool tegra_chipid_is_t132(void);
53bool tegra_chipid_is_t186(void);
54bool tegra_chipid_is_t210(void);
55bool tegra_chipid_is_t210_b01(void);
David Pu819975f2019-08-05 17:00:31 -070056bool tegra_chipid_is_t194(void);
Varun Wadekarfdcdfe22017-04-13 14:12:49 -070057
Varun Wadekar28dcc212016-07-20 10:28:51 -070058/*
59 * Tegra platform identifiers
60 */
Anthony Zhou70262ef2017-03-22 14:37:04 +080061bool tegra_platform_is_silicon(void);
62bool tegra_platform_is_qt(void);
63bool tegra_platform_is_emulation(void);
64bool tegra_platform_is_linsim(void);
65bool tegra_platform_is_fpga(void);
66bool tegra_platform_is_unit_fpga(void);
67bool tegra_platform_is_virt_dev_kit(void);
Varun Wadekar28dcc212016-07-20 10:28:51 -070068
Julius Werner53456fc2019-07-09 13:49:11 -070069#endif /* __ASSEMBLER__ */
Harvey Hsieh6dc0d762017-04-24 19:35:51 +080070
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000071#endif /* TEGRA_PLATFORM_H */