blob: 91e3b0ac51ee494de33ecfddeb9c5511011c18a0 [file] [log] [blame]
Loh Tien Hock59400a42019-02-04 16:17:24 +08001/*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <arch_helpers.h>
9#include <drivers/arm/gicv2.h>
10
11#include <drivers/generic_delay_timer.h>
12#include <drivers/console.h>
13#include <drivers/ti/uart/uart_16550.h>
14#include <common/bl_common.h>
15#include <common/debug.h>
16#include <common/desc_image_load.h>
17#include <errno.h>
18#include <drivers/io/io_storage.h>
19#include <common/image_decompress.h>
20#include <plat/common/platform.h>
21#include <platform_def.h>
22#include <platform_private.h>
23#include <drivers/synopsys/dw_mmc.h>
24#include <lib/mmio.h>
25#include <lib/xlat_tables/xlat_tables.h>
26
27#include "s10_memory_controller.h"
28#include "s10_reset_manager.h"
29#include "s10_clock_manager.h"
30#include "s10_handoff.h"
31#include "s10_pinmux.h"
32#include "aarch64/stratix10_private.h"
33
34const mmap_region_t plat_stratix10_mmap[] = {
35 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
36 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS),
37 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_NS),
38 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
39 MT_NON_CACHEABLE | MT_RW | MT_SECURE),
40 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
41 MT_DEVICE | MT_RW | MT_SECURE),
42 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS),
43 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS),
44 {0},
45};
46
47boot_source_type boot_source;
48
49void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
50 u_register_t x2, u_register_t x4)
51{
52 static console_16550_t console;
53 handoff reverse_handoff_ptr;
54
55 generic_delay_timer_init();
56
57 if (s10_get_handoff(&reverse_handoff_ptr))
58 return;
59 config_pinmux(&reverse_handoff_ptr);
60 boot_source = reverse_handoff_ptr.boot_source;
61
62 config_clkmgr_handoff(&reverse_handoff_ptr);
63 enable_nonsecure_access();
64 deassert_peripheral_reset();
65 config_hps_hs_before_warm_reset();
66
67 console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
68 &console);
69
70 plat_delay_timer_init();
71 init_hard_memory_controller();
72}
73
74
75void bl2_el3_plat_arch_setup(void)
76{
77
78 struct mmc_device_info info;
79 const mmap_region_t bl_regions[] = {
80 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE,
81 MT_MEMORY | MT_RW | MT_SECURE),
82 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
83 MT_CODE | MT_SECURE),
84 MAP_REGION_FLAT(BL_RO_DATA_BASE,
85 BL_RO_DATA_END - BL_RO_DATA_BASE,
86 MT_RO_DATA | MT_SECURE),
87#if USE_COHERENT_MEM_BAR
88 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
89 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
90 MT_DEVICE | MT_RW | MT_SECURE),
91#endif
92 {0},
93 };
94
95 setup_page_tables(bl_regions, plat_stratix10_mmap);
96
97 enable_mmu_el3(0);
98
Loh Tien Hock59400a42019-02-04 16:17:24 +080099 dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000);
100
101 info.mmc_dev_type = MMC_IS_SD;
102
103 switch (boot_source) {
104 case BOOT_SOURCE_SDMMC:
105 dw_mmc_init(&params, &info);
106 stratix10_io_setup();
107 break;
108 default:
109 ERROR("Unsupported boot source\n");
110 panic();
111 break;
112 }
113}
114
115uint32_t get_spsr_for_bl33_entry(void)
116{
117 unsigned long el_status;
118 unsigned int mode;
119 uint32_t spsr;
120
121 /* Figure out what mode we enter the non-secure world in */
122 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
123 el_status &= ID_AA64PFR0_ELX_MASK;
124
125 mode = (el_status) ? MODE_EL2 : MODE_EL1;
126
127 /*
128 * TODO: Consider the possibility of specifying the SPSR in
129 * the FIP ToC and allowing the platform to have a say as
130 * well.
131 */
132 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
133 return spsr;
134}
135
136
137int bl2_plat_handle_post_image_load(unsigned int image_id)
138{
139 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
140
141 switch (image_id) {
142 case BL33_IMAGE_ID:
143 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
144 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry();
145 break;
146 default:
147 break;
148 }
149
150 return 0;
151}
152
153/*******************************************************************************
154 * Perform any BL3-1 platform setup code
155 ******************************************************************************/
156void bl2_platform_setup(void)
157{
158}
159