| Edward-JW Yang | 1c7fd0b | 2021-06-28 11:29:51 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | /**************************************************************** |
| 8 | * Auto generated by DE, please DO NOT modify this file directly. |
| 9 | *****************************************************************/ |
| 10 | |
| 11 | #ifndef MT_SPM_REG |
| 12 | #define MT_SPM_REG |
| 13 | |
| 14 | #include "sleep_def.h" |
| 15 | #include <platform_def.h> |
| 16 | #include "pcm_def.h" |
| 17 | |
| 18 | /************************************** |
| 19 | * Define and Declare |
| 20 | **************************************/ |
| 21 | |
| 22 | /*******Register_SPM_CFG*************************************************/ |
| 23 | #define POWERON_CONFIG_EN (SPM_BASE + 0x000) |
| 24 | #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004) |
| 25 | #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008) |
| 26 | #define SPM_CLK_CON (SPM_BASE + 0x00C) |
| 27 | #define SPM_CLK_SETTLE (SPM_BASE + 0x010) |
| 28 | #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014) |
| 29 | #define PCM_CON0 (SPM_BASE + 0x018) |
| 30 | #define PCM_CON1 (SPM_BASE + 0x01C) |
| 31 | #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020) |
| 32 | #define SPM_POWER_ON_VAL3 (SPM_BASE + 0x024) |
| 33 | #define PCM_REG_DATA_INI (SPM_BASE + 0x028) |
| 34 | #define PCM_PWR_IO_EN (SPM_BASE + 0x02C) |
| 35 | #define PCM_TIMER_VAL (SPM_BASE + 0x030) |
| 36 | #define PCM_WDT_VAL (SPM_BASE + 0x034) |
| 37 | #define SPM_SW_RST_CON (SPM_BASE + 0x040) |
| 38 | #define SPM_SW_RST_CON_SET (SPM_BASE + 0x044) |
| 39 | #define SPM_SW_RST_CON_CLR (SPM_BASE + 0x048) |
| 40 | #define VS1_PSR_MASK_B (SPM_BASE + 0x04C) |
| 41 | #define SPM_ARBITER_EN (SPM_BASE + 0x050) |
| 42 | #define SCPSYS_CLK_CON (SPM_BASE + 0x054) |
| 43 | #define SPM_SRAM_RSV_CON (SPM_BASE + 0x058) |
| 44 | #define SPM_SWINT (SPM_BASE + 0x05C) |
| 45 | #define SPM_SWINT_SET (SPM_BASE + 0x060) |
| 46 | #define SPM_SWINT_CLR (SPM_BASE + 0x064) |
| 47 | #define SPM_SCP_MAILBOX (SPM_BASE + 0x068) |
| 48 | #define SCP_SPM_MAILBOX (SPM_BASE + 0x06C) |
| 49 | #define SPM_SCP_IRQ (SPM_BASE + 0x070) |
| 50 | #define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x074) |
| 51 | #define SPM_IRQ_MASK (SPM_BASE + 0x078) |
| 52 | #define SPM_SRC_REQ (SPM_BASE + 0x080) |
| 53 | #define SPM_SRC_MASK (SPM_BASE + 0x084) |
| 54 | #define SPM_SRC2_MASK (SPM_BASE + 0x088) |
| 55 | #define SPM_SRC3_MASK (SPM_BASE + 0x090) |
| 56 | #define SPM_SRC4_MASK (SPM_BASE + 0x094) |
| 57 | #define SPM_WAKEUP_EVENT_MASK2 (SPM_BASE + 0x098) |
| 58 | #define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x09C) |
| 59 | #define SPM_WAKEUP_EVENT_SENS (SPM_BASE + 0x0A0) |
| 60 | #define SPM_WAKEUP_EVENT_CLEAR (SPM_BASE + 0x0A4) |
| 61 | #define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0A8) |
| 62 | #define SCP_CLK_CON (SPM_BASE + 0x0AC) |
| 63 | #define PCM_DEBUG_CON (SPM_BASE + 0x0B0) |
| 64 | #define DDREN_DBC_CON (SPM_BASE + 0x0B4) |
| 65 | #define SPM_RESOURCE_ACK_CON0 (SPM_BASE + 0x0B8) |
| 66 | #define SPM_RESOURCE_ACK_CON1 (SPM_BASE + 0x0BC) |
| 67 | #define SPM_RESOURCE_ACK_CON2 (SPM_BASE + 0x0C0) |
| 68 | #define SPM_RESOURCE_ACK_CON3 (SPM_BASE + 0x0C4) |
| 69 | #define SPM_RESOURCE_ACK_CON4 (SPM_BASE + 0x0C8) |
| 70 | #define SPM_SRAM_CON (SPM_BASE + 0x0CC) |
| 71 | /*******Register_SPM_STA*************************************************/ |
| 72 | #define PCM_REG0_DATA (SPM_BASE + 0x100) |
| 73 | #define PCM_REG2_DATA (SPM_BASE + 0x104) |
| 74 | #define PCM_REG6_DATA (SPM_BASE + 0x108) |
| 75 | #define PCM_REG7_DATA (SPM_BASE + 0x10C) |
| 76 | #define PCM_REG13_DATA (SPM_BASE + 0x110) |
| 77 | #define SRC_REQ_STA_0 (SPM_BASE + 0x114) |
| 78 | #define SRC_REQ_STA_1 (SPM_BASE + 0x118) |
| 79 | #define SRC_REQ_STA_2 (SPM_BASE + 0x120) |
| 80 | #define SRC_REQ_STA_3 (SPM_BASE + 0x124) |
| 81 | #define SRC_REQ_STA_4 (SPM_BASE + 0x128) |
| 82 | #define PCM_TIMER_OUT (SPM_BASE + 0x130) |
| 83 | #define PCM_WDT_OUT (SPM_BASE + 0x134) |
| 84 | #define SPM_IRQ_STA (SPM_BASE + 0x138) |
| 85 | #define MD32PCM_WAKEUP_STA (SPM_BASE + 0x13C) |
| 86 | #define MD32PCM_EVENT_STA (SPM_BASE + 0x140) |
| 87 | #define SPM_WAKEUP_STA (SPM_BASE + 0x144) |
| 88 | #define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x148) |
| 89 | #define SPM_WAKEUP_MISC (SPM_BASE + 0x14C) |
| 90 | #define MM_DVFS_HALT (SPM_BASE + 0x150) |
| 91 | #define SUBSYS_IDLE_STA (SPM_BASE + 0x164) |
| 92 | #define PCM_STA (SPM_BASE + 0x168) |
| 93 | #define PWR_STATUS (SPM_BASE + 0x16C) |
| 94 | #define PWR_STATUS_2ND (SPM_BASE + 0x170) |
| 95 | #define CPU_PWR_STATUS (SPM_BASE + 0x174) |
| 96 | #define CPU_PWR_STATUS_2ND (SPM_BASE + 0x178) |
| 97 | #define SPM_VTCXO_EVENT_COUNT_STA (SPM_BASE + 0x17C) |
| 98 | #define SPM_INFRA_EVENT_COUNT_STA (SPM_BASE + 0x180) |
| 99 | #define SPM_VRF18_EVENT_COUNT_STA (SPM_BASE + 0x184) |
| 100 | #define SPM_APSRC_EVENT_COUNT_STA (SPM_BASE + 0x188) |
| 101 | #define SPM_DDREN_EVENT_COUNT_STA (SPM_BASE + 0x18C) |
| 102 | #define MD32PCM_STA (SPM_BASE + 0x190) |
| 103 | #define MD32PCM_PC (SPM_BASE + 0x194) |
| 104 | #define OTHER_PWR_STATUS (SPM_BASE + 0x198) |
| 105 | #define DVFSRC_EVENT_STA (SPM_BASE + 0x19C) |
| 106 | #define BUS_PROTECT_RDY (SPM_BASE + 0x1A0) |
| 107 | #define BUS_PROTECT1_RDY (SPM_BASE + 0x1A4) |
| 108 | #define BUS_PROTECT2_RDY (SPM_BASE + 0x1A8) |
| 109 | #define BUS_PROTECT3_RDY (SPM_BASE + 0x1AC) |
| 110 | #define BUS_PROTECT4_RDY (SPM_BASE + 0x1B0) |
| 111 | #define BUS_PROTECT5_RDY (SPM_BASE + 0x1B4) |
| 112 | #define BUS_PROTECT6_RDY (SPM_BASE + 0x1B8) |
| 113 | #define BUS_PROTECT7_RDY (SPM_BASE + 0x1BC) |
| 114 | #define BUS_PROTECT8_RDY (SPM_BASE + 0x1C0) |
| 115 | #define BUS_PROTECT9_RDY (SPM_BASE + 0x1C4) |
| 116 | #define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1D0) |
| 117 | #define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1D4) |
| 118 | #define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1D8) |
| 119 | #define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1DC) |
| 120 | #define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1E0) |
| 121 | #define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1E4) |
| 122 | #define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1E8) |
| 123 | #define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1EC) |
| 124 | #define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1F0) |
| 125 | #define SPM_CG_CHECK_STA (SPM_BASE + 0x1F4) |
| 126 | #define SPM_DVFS_STA (SPM_BASE + 0x1F8) |
| 127 | #define SPM_DVFS_OPP_STA (SPM_BASE + 0x1FC) |
| 128 | /*******Register_CPU_MT*************************************************/ |
| 129 | #define CPUEB_PWR_CON (SPM_BASE + 0x200) |
| 130 | #define SPM_MCUSYS_PWR_CON (SPM_BASE + 0x204) |
| 131 | #define SPM_CPUTOP_PWR_CON (SPM_BASE + 0x208) |
| 132 | #define SPM_CPU0_PWR_CON (SPM_BASE + 0x20C) |
| 133 | #define SPM_CPU1_PWR_CON (SPM_BASE + 0x210) |
| 134 | #define SPM_CPU2_PWR_CON (SPM_BASE + 0x214) |
| 135 | #define SPM_CPU3_PWR_CON (SPM_BASE + 0x218) |
| 136 | #define SPM_CPU4_PWR_CON (SPM_BASE + 0x21C) |
| 137 | #define SPM_CPU5_PWR_CON (SPM_BASE + 0x220) |
| 138 | #define SPM_CPU6_PWR_CON (SPM_BASE + 0x224) |
| 139 | #define SPM_CPU7_PWR_CON (SPM_BASE + 0x228) |
| 140 | #define ARMPLL_CLK_CON (SPM_BASE + 0x22C) |
| 141 | #define MCUSYS_IDLE_STA (SPM_BASE + 0x230) |
| 142 | #define GIC_WAKEUP_STA (SPM_BASE + 0x234) |
| 143 | #define CPU_SPARE_CON (SPM_BASE + 0x238) |
| 144 | #define CPU_SPARE_CON_SET (SPM_BASE + 0x23C) |
| 145 | #define CPU_SPARE_CON_CLR (SPM_BASE + 0x240) |
| 146 | #define ARMPLL_CLK_SEL (SPM_BASE + 0x244) |
| 147 | #define EXT_INT_WAKEUP_REQ (SPM_BASE + 0x248) |
| 148 | #define EXT_INT_WAKEUP_REQ_SET (SPM_BASE + 0x24C) |
| 149 | #define EXT_INT_WAKEUP_REQ_CLR (SPM_BASE + 0x250) |
| 150 | #define CPU0_IRQ_MASK (SPM_BASE + 0x260) |
| 151 | #define CPU_IRQ_MASK_SET (SPM_BASE + 0x264) |
| 152 | #define CPU_IRQ_MASK_CLR (SPM_BASE + 0x268) |
| 153 | #define CPU_WFI_EN (SPM_BASE + 0x280) |
| 154 | #define CPU_WFI_EN_SET (SPM_BASE + 0x284) |
| 155 | #define CPU_WFI_EN_CLR (SPM_BASE + 0x288) |
| 156 | #define SYSRAM_CON (SPM_BASE + 0x290) |
| 157 | #define SYSROM_CON (SPM_BASE + 0x294) |
| 158 | #define ROOT_CPUTOP_ADDR (SPM_BASE + 0x2A0) |
| 159 | #define ROOT_CORE_ADDR (SPM_BASE + 0x2A4) |
| 160 | #define SPM2SW_MAILBOX_0 (SPM_BASE + 0x2D0) |
| 161 | #define SPM2SW_MAILBOX_1 (SPM_BASE + 0x2D4) |
| 162 | #define SPM2SW_MAILBOX_2 (SPM_BASE + 0x2D8) |
| 163 | #define SPM2SW_MAILBOX_3 (SPM_BASE + 0x2DC) |
| 164 | #define SW2SPM_INT (SPM_BASE + 0x2E0) |
| 165 | #define SW2SPM_INT_SET (SPM_BASE + 0x2E4) |
| 166 | #define SW2SPM_INT_CLR (SPM_BASE + 0x2E8) |
| 167 | #define SW2SPM_MAILBOX_0 (SPM_BASE + 0x2EC) |
| 168 | #define SW2SPM_MAILBOX_1 (SPM_BASE + 0x2F0) |
| 169 | #define SW2SPM_MAILBOX_2 (SPM_BASE + 0x2F4) |
| 170 | #define SW2SPM_MAILBOX_3 (SPM_BASE + 0x2F8) |
| 171 | #define SW2SPM_CFG (SPM_BASE + 0x2FC) |
| 172 | /*******Register_NONCPU_MT*************************************************/ |
| 173 | #define MFG0_PWR_CON (SPM_BASE + 0x300) |
| 174 | #define MFG1_PWR_CON (SPM_BASE + 0x304) |
| 175 | #define MFG2_PWR_CON (SPM_BASE + 0x308) |
| 176 | #define MFG3_PWR_CON (SPM_BASE + 0x30C) |
| 177 | #define MFG4_PWR_CON (SPM_BASE + 0x310) |
| 178 | #define MFG5_PWR_CON (SPM_BASE + 0x314) |
| 179 | #define MFG6_PWR_CON (SPM_BASE + 0x318) |
| 180 | #define IFR_PWR_CON (SPM_BASE + 0x31C) |
| 181 | #define IFR_SUB_PWR_CON (SPM_BASE + 0x320) |
| 182 | #define PERI_PWR_CON (SPM_BASE + 0x324) |
| 183 | #define PEXTP_MAC_TOP_P0_PWR_CON (SPM_BASE + 0x328) |
| 184 | #define PEXTP_MAC_TOP_P1_PWR_CON (SPM_BASE + 0x32C) |
| 185 | #define PCIE_PHY_PWR_CON (SPM_BASE + 0x330) |
| 186 | #define SSUSB_PCIE_PHY_PWR_CON (SPM_BASE + 0x334) |
| 187 | #define SSUSB_TOP_P1_PWR_CON (SPM_BASE + 0x338) |
| 188 | #define SSUSB_TOP_P2_PWR_CON (SPM_BASE + 0x33C) |
| 189 | #define SSUSB_TOP_P3_PWR_CON (SPM_BASE + 0x340) |
| 190 | #define ETHER_PWR_CON (SPM_BASE + 0x344) |
| 191 | #define DPY0_PWR_CON (SPM_BASE + 0x348) |
| 192 | #define DPY1_PWR_CON (SPM_BASE + 0x34C) |
| 193 | #define DPM0_PWR_CON (SPM_BASE + 0x350) |
| 194 | #define DPM1_PWR_CON (SPM_BASE + 0x354) |
| 195 | #define AUDIO_PWR_CON (SPM_BASE + 0x358) |
| 196 | #define AUDIO_ASRC_PWR_CON (SPM_BASE + 0x35C) |
| 197 | #define ADSP_PWR_CON (SPM_BASE + 0x360) |
| 198 | #define VPPSYS0_PWR_CON (SPM_BASE + 0x364) |
| 199 | #define VPPSYS1_PWR_CON (SPM_BASE + 0x368) |
| 200 | #define VDOSYS0_PWR_CON (SPM_BASE + 0x36C) |
| 201 | #define VDOSYS1_PWR_CON (SPM_BASE + 0x370) |
| 202 | #define WPESYS_PWR_CON (SPM_BASE + 0x374) |
| 203 | #define DP_TX_PWR_CON (SPM_BASE + 0x378) |
| 204 | #define EDP_TX_PWR_CON (SPM_BASE + 0x37C) |
| 205 | #define HDMI_TX_PWR_CON (SPM_BASE + 0x380) |
| 206 | #define HDMI_RX_PWR_CON (SPM_BASE + 0x384) |
| 207 | #define VDE0_PWR_CON (SPM_BASE + 0x388) |
| 208 | #define VDE1_PWR_CON (SPM_BASE + 0x38C) |
| 209 | #define VDE2_PWR_CON (SPM_BASE + 0x390) |
| 210 | #define VEN_PWR_CON (SPM_BASE + 0x394) |
| 211 | #define VEN_CORE1_PWR_CON (SPM_BASE + 0x398) |
| 212 | #define CAM_PWR_CON (SPM_BASE + 0x39C) |
| 213 | #define CAM_RAWA_PWR_CON (SPM_BASE + 0x3A0) |
| 214 | #define CAM_RAWB_PWR_CON (SPM_BASE + 0x3A4) |
| 215 | #define CAM_RAWC_PWR_CON (SPM_BASE + 0x3A8) |
| 216 | #define IMG_M_PWR_CON (SPM_BASE + 0x3AC) |
| 217 | #define IMG_D_PWR_CON (SPM_BASE + 0x3B0) |
| 218 | #define IPE_PWR_CON (SPM_BASE + 0x3B4) |
| 219 | #define NNA0_PWR_CON (SPM_BASE + 0x3B8) |
| 220 | #define NNA1_PWR_CON (SPM_BASE + 0x3BC) |
| 221 | #define IPNNA_PWR_CON (SPM_BASE + 0x3C0) |
| 222 | #define CSI_RX_TOP_PWR_CON (SPM_BASE + 0x3C4) |
| 223 | #define SSPM_SRAM_CON (SPM_BASE + 0x3C4) |
| 224 | #define SCP_SRAM_CON (SPM_BASE + 0x3D0) |
| 225 | #define UFS_SRAM_CON (SPM_BASE + 0x3D4) |
| 226 | #define DEVAPC_IFR_SRAM_CON (SPM_BASE + 0x3D8) |
| 227 | #define DEVAPC_SUBIFR_SRAM_CON (SPM_BASE + 0x3DC) |
| 228 | #define DEVAPC_ACP_SRAM_CON (SPM_BASE + 0x3E0) |
| 229 | #define USB_SRAM_CON (SPM_BASE + 0x3E4) |
| 230 | #define DUMMY_SRAM_CO (SPM_BASE + 0x3E8) |
| 231 | #define EXT_BUCK_ISO (SPM_BASE + 0x3EC) |
| 232 | #define MSDC_SRAM_CON (SPM_BASE + 0x3F0) |
| 233 | #define DEBUGTOP_SRAM (SPM_BASE + 0x3F4) |
| 234 | #define DPMAIF_SRAM_C (SPM_BASE + 0x3F8) |
| 235 | #define GCPU_SRAM_CON (SPM_BASE + 0x3FC) |
| 236 | /*******Register_DIRC_IF*************************************************/ |
| 237 | #define SPM_MEM_CK_SEL (SPM_BASE + 0x400) |
| 238 | #define SPM_BUS_PROTECT_MASK_B (SPM_BASE + 0x404) |
| 239 | #define SPM_BUS_PROTECT1_MASK_B (SPM_BASE + 0x408) |
| 240 | #define SPM_BUS_PROTECT2_MASK_B (SPM_BASE + 0x40C) |
| 241 | #define SPM_BUS_PROTECT3_MASK_B (SPM_BASE + 0x410) |
| 242 | #define SPM_BUS_PROTECT4_MASK_B (SPM_BASE + 0x414) |
| 243 | #define SPM_BUS_PROTECT5_MASK_B (SPM_BASE + 0x418) |
| 244 | #define SPM_BUS_PROTECT6_MASK_B (SPM_BASE + 0x41C) |
| 245 | #define SPM_BUS_PROTECT7_MASK_B (SPM_BASE + 0x420) |
| 246 | #define SPM_BUS_PROTECT8_MASK_B (SPM_BASE + 0x424) |
| 247 | #define SPM_BUS_PROTECT9_MASK_B (SPM_BASE + 0x428) |
| 248 | #define SPM_EMI_BW_MODE (SPM_BASE + 0x42C) |
| 249 | #define SPM2MM_CON (SPM_BASE + 0x434) |
| 250 | #define SPM2CPUEB_CON (SPM_BASE + 0x438) |
| 251 | #define AP_MDSRC_REQ (SPM_BASE + 0x43C) |
| 252 | #define SPM2EMI_ENTER_ULPM (SPM_BASE + 0x440) |
| 253 | #define SPM_PLL_CON (SPM_BASE + 0x444) |
| 254 | #define RC_SPM_CTRL (SPM_BASE + 0x448) |
| 255 | #define SPM_DRAM_MCU_SW_CON_0 (SPM_BASE + 0x44C) |
| 256 | #define SPM_DRAM_MCU_SW_CON_1 (SPM_BASE + 0x450) |
| 257 | #define SPM_DRAM_MCU_SW_CON_2 (SPM_BASE + 0x454) |
| 258 | #define SPM_DRAM_MCU_SW_CON_3 (SPM_BASE + 0x458) |
| 259 | #define SPM_DRAM_MCU_SW_CON_4 (SPM_BASE + 0x45C) |
| 260 | #define SPM_DRAM_MCU_STA_0 (SPM_BASE + 0x460) |
| 261 | #define SPM_DRAM_MCU_STA_1 (SPM_BASE + 0x464) |
| 262 | #define SPM_DRAM_MCU_STA_2 (SPM_BASE + 0x468) |
| 263 | #define SPM_DRAM_MCU_SW_SEL_0 (SPM_BASE + 0x46C) |
| 264 | #define RELAY_DVFS_LEVEL (SPM_BASE + 0x470) |
| 265 | #define DRAMC_DPY_CLK_SW_CON_0 (SPM_BASE + 0x474) |
| 266 | #define DRAMC_DPY_CLK_SW_CON_1 (SPM_BASE + 0x478) |
| 267 | #define DRAMC_DPY_CLK_SW_CON_2 (SPM_BASE + 0x47C) |
| 268 | #define DRAMC_DPY_CLK_SW_CON_3 (SPM_BASE + 0x480) |
| 269 | #define DRAMC_DPY_CLK_SW_SEL_0 (SPM_BASE + 0x484) |
| 270 | #define DRAMC_DPY_CLK_SW_SEL_1 (SPM_BASE + 0x488) |
| 271 | #define DRAMC_DPY_CLK_SW_SEL_2 (SPM_BASE + 0x48C) |
| 272 | #define DRAMC_DPY_CLK_SW_SEL_3 (SPM_BASE + 0x490) |
| 273 | #define DRAMC_DPY_CLK_SPM_CON (SPM_BASE + 0x494) |
| 274 | #define SPM_DVFS_LEVEL (SPM_BASE + 0x498) |
| 275 | #define SPM_CIRQ_CON (SPM_BASE + 0x49C) |
| 276 | #define SPM_DVFS_MISC (SPM_BASE + 0x4A0) |
| 277 | #define RG_MODULE_SW_CG_0_MASK_REQ_0 (SPM_BASE + 0x4A4) |
| 278 | #define RG_MODULE_SW_CG_0_MASK_REQ_1 (SPM_BASE + 0x4A8) |
| 279 | #define RG_MODULE_SW_CG_0_MASK_REQ_2 (SPM_BASE + 0x4AC) |
| 280 | #define RG_MODULE_SW_CG_1_MASK_REQ_0 (SPM_BASE + 0x4B0) |
| 281 | #define RG_MODULE_SW_CG_1_MASK_REQ_1 (SPM_BASE + 0x4B4) |
| 282 | #define RG_MODULE_SW_CG_1_MASK_REQ_2 (SPM_BASE + 0x4B8) |
| 283 | #define RG_MODULE_SW_CG_2_MASK_REQ_0 (SPM_BASE + 0x4BC) |
| 284 | #define RG_MODULE_SW_CG_2_MASK_REQ_1 (SPM_BASE + 0x4C0) |
| 285 | #define RG_MODULE_SW_CG_2_MASK_REQ_2 (SPM_BASE + 0x4C4) |
| 286 | #define RG_MODULE_SW_CG_3_MASK_REQ_0 (SPM_BASE + 0x4C8) |
| 287 | #define RG_MODULE_SW_CG_3_MASK_REQ_1 (SPM_BASE + 0x4CC) |
| 288 | #define RG_MODULE_SW_CG_3_MASK_REQ_2 (SPM_BASE + 0x4D0) |
| 289 | #define PWR_STATUS_MASK_REQ_0 (SPM_BASE + 0x4D4) |
| 290 | #define PWR_STATUS_MASK_REQ_1 (SPM_BASE + 0x4D8) |
| 291 | #define PWR_STATUS_MASK_REQ_2 (SPM_BASE + 0x4DC) |
| 292 | #define SPM_CG_CHECK_CON (SPM_BASE + 0x4E0) |
| 293 | #define SPM_SRC_RDY_STA (SPM_BASE + 0x4E4) |
| 294 | #define SPM_DVS_DFS_LEVEL (SPM_BASE + 0x4E8) |
| 295 | #define SPM_FORCE_DVFS (SPM_BASE + 0x4EC) |
| 296 | #define DRAMC_MCU_SRAM_CON (SPM_BASE + 0x4F0) |
| 297 | #define DRAMC_MCU2_SRAM_CON (SPM_BASE + 0x4F4) |
| 298 | #define DPY_SHU_SRAM_CON (SPM_BASE + 0x4F8) |
| 299 | #define DPY_SHU2_SRAM_CON (SPM_BASE + 0x4FC) |
| 300 | /*******The Others*************************************************/ |
| 301 | #define SRCLKEN_RC_CFG (SPM_BASE + 0x500) |
| 302 | #define RC_CENTRAL_CFG1 (SPM_BASE + 0x504) |
| 303 | #define RC_CENTRAL_CFG2 (SPM_BASE + 0x508) |
| 304 | #define RC_CMD_ARB_CFG (SPM_BASE + 0x50C) |
| 305 | #define RC_PMIC_RCEN_ADDR (SPM_BASE + 0x510) |
| 306 | #define RC_PMIC_RCEN_SET_CLR_ADDR (SPM_BASE + 0x514) |
| 307 | #define RC_DCXO_FPM_CFG (SPM_BASE + 0x518) |
| 308 | #define RC_CENTRAL_CFG3 (SPM_BASE + 0x51C) |
| 309 | #define RC_M00_SRCLKEN_CFG (SPM_BASE + 0x520) |
| 310 | #define RC_M01_SRCLKEN_CFG (SPM_BASE + 0x524) |
| 311 | #define RC_M02_SRCLKEN_CFG (SPM_BASE + 0x528) |
| 312 | #define RC_M03_SRCLKEN_CFG (SPM_BASE + 0x52C) |
| 313 | #define RC_M04_SRCLKEN_CFG (SPM_BASE + 0x530) |
| 314 | #define RC_M05_SRCLKEN_CFG (SPM_BASE + 0x534) |
| 315 | #define RC_M06_SRCLKEN_CFG (SPM_BASE + 0x538) |
| 316 | #define RC_M07_SRCLKEN_CFG (SPM_BASE + 0x53C) |
| 317 | #define RC_M08_SRCLKEN_CFG (SPM_BASE + 0x540) |
| 318 | #define RC_M09_SRCLKEN_CFG (SPM_BASE + 0x544) |
| 319 | #define RC_M10_SRCLKEN_CFG (SPM_BASE + 0x548) |
| 320 | #define RC_M11_SRCLKEN_CFG (SPM_BASE + 0x54C) |
| 321 | #define RC_M12_SRCLKEN_CFG (SPM_BASE + 0x550) |
| 322 | #define RC_SRCLKEN_SW_CON_CFG (SPM_BASE + 0x554) |
| 323 | #define RC_CENTRAL_CFG4 (SPM_BASE + 0x558) |
| 324 | #define RC_PROTOCOL_CHK_CFG (SPM_BASE + 0x560) |
| 325 | #define RC_DEBUG_CFG (SPM_BASE + 0x564) |
| 326 | #define RC_MISC_0 (SPM_BASE + 0x5B4) |
| 327 | |
| 328 | #define SUBSYS_INTF_CFG (SPM_BASE + 0x5BC) |
| 329 | #define PCM_WDT_LATCH_25 (SPM_BASE + 0x5C0) |
| 330 | #define PCM_WDT_LATCH_26 (SPM_BASE + 0x5C4) |
| 331 | #define PCM_WDT_LATCH_27 (SPM_BASE + 0x5C8) |
| 332 | #define PCM_WDT_LATCH_28 (SPM_BASE + 0x5CC) |
| 333 | #define PCM_WDT_LATCH_29 (SPM_BASE + 0x5D0) |
| 334 | #define PCM_WDT_LATCH_30 (SPM_BASE + 0x5D4) |
| 335 | #define PCM_WDT_LATCH_31 (SPM_BASE + 0x5D8) |
| 336 | #define PCM_WDT_LATCH_32 (SPM_BASE + 0x5DC) |
| 337 | #define PCM_WDT_LATCH_33 (SPM_BASE + 0x5E0) |
| 338 | #define PCM_WDT_LATCH_34 (SPM_BASE + 0x5E4) |
| 339 | #define PCM_WDT_LATCH_35 (SPM_BASE + 0x5EC) |
| 340 | #define PCM_WDT_LATCH_36 (SPM_BASE + 0x5F0) |
| 341 | #define PCM_WDT_LATCH_37 (SPM_BASE + 0x5F4) |
| 342 | #define PCM_WDT_LATCH_38 (SPM_BASE + 0x5F8) |
| 343 | #define PCM_WDT_LATCH_39 (SPM_BASE + 0x5FC) |
| 344 | /*******Register_RSV*************************************************/ |
| 345 | #define SPM_SW_FLAG_0 (SPM_BASE + 0x600) |
| 346 | #define SPM_SW_DEBUG_0 (SPM_BASE + 0x604) |
| 347 | #define SPM_SW_FLAG_1 (SPM_BASE + 0x608) |
| 348 | #define SPM_SW_DEBUG_1 (SPM_BASE + 0x60C) |
| 349 | #define SPM_SW_RSV_0 (SPM_BASE + 0x610) |
| 350 | #define SPM_SW_RSV_1 (SPM_BASE + 0x614) |
| 351 | #define SPM_SW_RSV_2 (SPM_BASE + 0x618) |
| 352 | #define SPM_SW_RSV_3 (SPM_BASE + 0x61C) |
| 353 | #define SPM_SW_RSV_4 (SPM_BASE + 0x620) |
| 354 | #define SPM_SW_RSV_5 (SPM_BASE + 0x624) |
| 355 | #define SPM_SW_RSV_6 (SPM_BASE + 0x628) |
| 356 | #define SPM_SW_RSV_7 (SPM_BASE + 0x62C) |
| 357 | #define SPM_SW_RSV_8 (SPM_BASE + 0x630) |
| 358 | #define SPM_BK_WAKE_EVENT (SPM_BASE + 0x634) |
| 359 | #define SPM_BK_VTCXO_DUR (SPM_BASE + 0x638) |
| 360 | #define SPM_BK_WAKE_MISC (SPM_BASE + 0x63C) |
| 361 | #define SPM_BK_PCM_TIMER (SPM_BASE + 0x640) |
| 362 | #define ULPOSC_CON (SPM_BASE + 0x644) |
| 363 | #define SPM_RSV_CON_0 (SPM_BASE + 0x650) |
| 364 | #define SPM_RSV_CON_1 (SPM_BASE + 0x654) |
| 365 | #define SPM_RSV_STA_0 (SPM_BASE + 0x658) |
| 366 | #define SPM_RSV_STA_1 (SPM_BASE + 0x65C) |
| 367 | #define SPM_SPARE_CON (SPM_BASE + 0x660) |
| 368 | #define SPM_SPARE_CON_SET (SPM_BASE + 0x664) |
| 369 | #define SPM_SPARE_CON_CLR (SPM_BASE + 0x668) |
| 370 | #define SPM_CROSS_WAKE_M00_REQ (SPM_BASE + 0x66C) |
| 371 | #define SPM_CROSS_WAKE_M01_REQ (SPM_BASE + 0x670) |
| 372 | #define SPM_CROSS_WAKE_M02_REQ (SPM_BASE + 0x674) |
| 373 | #define SPM_CROSS_WAKE_M03_REQ (SPM_BASE + 0x678) |
| 374 | #define SCP_VCORE_LEVEL (SPM_BASE + 0x67C) |
| 375 | #define SC_MM_CK_SEL_CON (SPM_BASE + 0x680) |
| 376 | #define SPARE_ACK_MASK (SPM_BASE + 0x684) |
| 377 | #define SPM_DV_CON_0 (SPM_BASE + 0x68C) |
| 378 | #define SPM_DV_CON_1 (SPM_BASE + 0x690) |
| 379 | #define SPM_DV_STA (SPM_BASE + 0x694) |
| 380 | #define CONN_XOWCN_DEBUG_EN (SPM_BASE + 0x698) |
| 381 | #define SPM_SEMA_M0 (SPM_BASE + 0x69C) |
| 382 | #define SPM_SEMA_M1 (SPM_BASE + 0x6A0) |
| 383 | #define SPM_SEMA_M2 (SPM_BASE + 0x6A4) |
| 384 | #define SPM_SEMA_M3 (SPM_BASE + 0x6A8) |
| 385 | #define SPM_SEMA_M4 (SPM_BASE + 0x6AC) |
| 386 | #define SPM_SEMA_M5 (SPM_BASE + 0x6B0) |
| 387 | #define SPM_SEMA_M6 (SPM_BASE + 0x6B4) |
| 388 | #define SPM_SEMA_M7 (SPM_BASE + 0x6B8) |
| 389 | #define SPM2ADSP_MAILBOX (SPM_BASE + 0x6BC) |
| 390 | #define ADSP2SPM_MAILBOX (SPM_BASE + 0x6C0) |
| 391 | #define SPM_ADSP_IRQ (SPM_BASE + 0x6C4) |
| 392 | #define SPM_MD32_IRQ (SPM_BASE + 0x6C8) |
| 393 | #define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x6CC) |
| 394 | #define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x6D0) |
| 395 | #define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x6D4) |
| 396 | #define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x6D8) |
| 397 | #define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x6DC) |
| 398 | #define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x6E0) |
| 399 | #define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x6E4) |
| 400 | #define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x6E8) |
| 401 | #define UFS_PSRI_SW (SPM_BASE + 0x6EC) |
| 402 | #define UFS_PSRI_SW_SET (SPM_BASE + 0x6F0) |
| 403 | #define UFS_PSRI_SW_CLR (SPM_BASE + 0x6F4) |
| 404 | #define SPM_AP_SEMA (SPM_BASE + 0x6F8) |
| 405 | #define SPM_SPM_SEMA (SPM_BASE + 0x6FC) |
| 406 | /*******Register_DVFS_TAB*************************************************/ |
| 407 | #define SPM_DVFS_CON (SPM_BASE + 0x700) |
| 408 | #define SPM_DVFS_CON_STA (SPM_BASE + 0x704) |
| 409 | #define SPM_PMIC_SPMI_CON (SPM_BASE + 0x708) |
| 410 | #define SPM_DVFS_CMD0 (SPM_BASE + 0x710) |
| 411 | #define SPM_DVFS_CMD1 (SPM_BASE + 0x714) |
| 412 | #define SPM_DVFS_CMD2 (SPM_BASE + 0x718) |
| 413 | #define SPM_DVFS_CMD3 (SPM_BASE + 0x71C) |
| 414 | #define SPM_DVFS_CMD4 (SPM_BASE + 0x720) |
| 415 | #define SPM_DVFS_CMD5 (SPM_BASE + 0x724) |
| 416 | #define SPM_DVFS_CMD6 (SPM_BASE + 0x728) |
| 417 | #define SPM_DVFS_CMD7 (SPM_BASE + 0x72C) |
| 418 | #define SPM_DVFS_CMD8 (SPM_BASE + 0x730) |
| 419 | #define SPM_DVFS_CMD9 (SPM_BASE + 0x734) |
| 420 | #define SPM_DVFS_CMD10 (SPM_BASE + 0x738) |
| 421 | #define SPM_DVFS_CMD11 (SPM_BASE + 0x73C) |
| 422 | #define SPM_DVFS_CMD12 (SPM_BASE + 0x740) |
| 423 | #define SPM_DVFS_CMD13 (SPM_BASE + 0x744) |
| 424 | #define SPM_DVFS_CMD14 (SPM_BASE + 0x748) |
| 425 | #define SPM_DVFS_CMD15 (SPM_BASE + 0x74C) |
| 426 | #define SPM_DVFS_CMD16 (SPM_BASE + 0x750) |
| 427 | #define SPM_DVFS_CMD17 (SPM_BASE + 0x754) |
| 428 | #define SPM_DVFS_CMD18 (SPM_BASE + 0x758) |
| 429 | #define SPM_DVFS_CMD19 (SPM_BASE + 0x75C) |
| 430 | #define SPM_DVFS_CMD20 (SPM_BASE + 0x760) |
| 431 | #define SPM_DVFS_CMD21 (SPM_BASE + 0x764) |
| 432 | #define SPM_DVFS_CMD22 (SPM_BASE + 0x768) |
| 433 | #define SPM_DVFS_CMD23 (SPM_BASE + 0x76C) |
| 434 | #define SYS_TIMER_VALUE_L (SPM_BASE + 0x770) |
| 435 | #define SYS_TIMER_VALUE_H (SPM_BASE + 0x774) |
| 436 | #define SYS_TIMER_START_L (SPM_BASE + 0x778) |
| 437 | #define SYS_TIMER_START_H (SPM_BASE + 0x77C) |
| 438 | #define SYS_TIMER_LATCH_L_00 (SPM_BASE + 0x780) |
| 439 | #define SYS_TIMER_LATCH_H_00 (SPM_BASE + 0x784) |
| 440 | #define SYS_TIMER_LATCH_L_01 (SPM_BASE + 0x788) |
| 441 | #define SYS_TIMER_LATCH_H_01 (SPM_BASE + 0x78C) |
| 442 | #define SYS_TIMER_LATCH_L_02 (SPM_BASE + 0x790) |
| 443 | #define SYS_TIMER_LATCH_H_02 (SPM_BASE + 0x794) |
| 444 | #define SYS_TIMER_LATCH_L_03 (SPM_BASE + 0x798) |
| 445 | #define SYS_TIMER_LATCH_H_03 (SPM_BASE + 0x79C) |
| 446 | #define SYS_TIMER_LATCH_L_04 (SPM_BASE + 0x7A0) |
| 447 | #define SYS_TIMER_LATCH_H_04 (SPM_BASE + 0x7A4) |
| 448 | #define SYS_TIMER_LATCH_L_05 (SPM_BASE + 0x7A8) |
| 449 | #define SYS_TIMER_LATCH_H_05 (SPM_BASE + 0x7AC) |
| 450 | #define SYS_TIMER_LATCH_L_06 (SPM_BASE + 0x7B0) |
| 451 | #define SYS_TIMER_LATCH_H_06 (SPM_BASE + 0x7B4) |
| 452 | #define SYS_TIMER_LATCH_L_07 (SPM_BASE + 0x7B8) |
| 453 | #define SYS_TIMER_LATCH_H_07 (SPM_BASE + 0x7BC) |
| 454 | #define SYS_TIMER_LATCH_L_08 (SPM_BASE + 0x7C0) |
| 455 | #define SYS_TIMER_LATCH_H_08 (SPM_BASE + 0x7C4) |
| 456 | #define SYS_TIMER_LATCH_L_09 (SPM_BASE + 0x7C8) |
| 457 | #define SYS_TIMER_LATCH_H_09 (SPM_BASE + 0x7CC) |
| 458 | #define SYS_TIMER_LATCH_L_10 (SPM_BASE + 0x7D0) |
| 459 | #define SYS_TIMER_LATCH_H_10 (SPM_BASE + 0x7D4) |
| 460 | #define SYS_TIMER_LATCH_L_11 (SPM_BASE + 0x7D8) |
| 461 | #define SYS_TIMER_LATCH_H_11 (SPM_BASE + 0x7DC) |
| 462 | #define SYS_TIMER_LATCH_L_12 (SPM_BASE + 0x7E0) |
| 463 | #define SYS_TIMER_LATCH_H_12 (SPM_BASE + 0x7E4) |
| 464 | #define SYS_TIMER_LATCH_L_13 (SPM_BASE + 0x7E8) |
| 465 | #define SYS_TIMER_LATCH_H_13 (SPM_BASE + 0x7EC) |
| 466 | #define SYS_TIMER_LATCH_L_14 (SPM_BASE + 0x7F0) |
| 467 | #define SYS_TIMER_LATCH_H_14 (SPM_BASE + 0x7F4) |
| 468 | #define SYS_TIMER_LATCH_L_15 (SPM_BASE + 0x7F8) |
| 469 | #define SYS_TIMER_LATCH_H_15 (SPM_BASE + 0x7FC) |
| 470 | /*******Register_LAT_STA*************************************************/ |
| 471 | #define PCM_WDT_LATCH_0 (SPM_BASE + 0x800) |
| 472 | #define PCM_WDT_LATCH_1 (SPM_BASE + 0x804) |
| 473 | #define PCM_WDT_LATCH_2 (SPM_BASE + 0x808) |
| 474 | #define PCM_WDT_LATCH_3 (SPM_BASE + 0x80C) |
| 475 | #define PCM_WDT_LATCH_4 (SPM_BASE + 0x810) |
| 476 | #define PCM_WDT_LATCH_5 (SPM_BASE + 0x814) |
| 477 | #define PCM_WDT_LATCH_6 (SPM_BASE + 0x818) |
| 478 | #define PCM_WDT_LATCH_7 (SPM_BASE + 0x81C) |
| 479 | #define PCM_WDT_LATCH_8 (SPM_BASE + 0x820) |
| 480 | #define PCM_WDT_LATCH_9 (SPM_BASE + 0x824) |
| 481 | #define PCM_WDT_LATCH_10 (SPM_BASE + 0x828) |
| 482 | #define PCM_WDT_LATCH_11 (SPM_BASE + 0x82C) |
| 483 | #define PCM_WDT_LATCH_12 (SPM_BASE + 0x830) |
| 484 | #define PCM_WDT_LATCH_13 (SPM_BASE + 0x834) |
| 485 | #define PCM_WDT_LATCH_14 (SPM_BASE + 0x838) |
| 486 | #define PCM_WDT_LATCH_15 (SPM_BASE + 0x83C) |
| 487 | #define PCM_WDT_LATCH_16 (SPM_BASE + 0x840) |
| 488 | #define PCM_WDT_LATCH_17 (SPM_BASE + 0x844) |
| 489 | #define PCM_WDT_LATCH_18 (SPM_BASE + 0x848) |
| 490 | #define PCM_WDT_LATCH_SPARE_0 (SPM_BASE + 0x84C) |
| 491 | #define PCM_WDT_LATCH_SPARE_1 (SPM_BASE + 0x850) |
| 492 | #define PCM_WDT_LATCH_SPARE_2 (SPM_BASE + 0x854) |
| 493 | #define PCM_WDT_LATCH_CONN_0 (SPM_BASE + 0x870) |
| 494 | #define PCM_WDT_LATCH_CONN_1 (SPM_BASE + 0x874) |
| 495 | #define PCM_WDT_LATCH_CONN_2 (SPM_BASE + 0x878) |
| 496 | #define DRAMC_GATING_ERR_LATCH_CH0_0 (SPM_BASE + 0x8A0) |
| 497 | #define DRAMC_GATING_ERR_LATCH_CH0_1 (SPM_BASE + 0x8A4) |
| 498 | #define DRAMC_GATING_ERR_LATCH_CH0_2 (SPM_BASE + 0x8A8) |
| 499 | #define DRAMC_GATING_ERR_LATCH_CH0_3 (SPM_BASE + 0x8AC) |
| 500 | #define DRAMC_GATING_ERR_LATCH_CH0_4 (SPM_BASE + 0x8B0) |
| 501 | #define DRAMC_GATING_ERR_LATCH_CH0_5 (SPM_BASE + 0x8B4) |
| 502 | #define DRAMC_GATING_ERR_LATCH_CH0_6 (SPM_BASE + 0x8B8) |
| 503 | #define DRAMC_GATING_ERR_LATCH_SPARE_0 (SPM_BASE + 0x8F4) |
| 504 | /*******Register_SPM_ACK_CHK*************************************************/ |
| 505 | #define SPM_ACK_CHK_CON_0 (SPM_BASE + 0x900) |
| 506 | #define SPM_ACK_CHK_PC_0 (SPM_BASE + 0x904) |
| 507 | #define SPM_ACK_CHK_SEL_0 (SPM_BASE + 0x908) |
| 508 | #define SPM_ACK_CHK_TIMER_0 (SPM_BASE + 0x90C) |
| 509 | #define SPM_ACK_CHK_STA_0 (SPM_BASE + 0x910) |
| 510 | #define SPM_ACK_CHK_SWINT_0 (SPM_BASE + 0x914) |
| 511 | #define SPM_ACK_CHK_CON_1 (SPM_BASE + 0x920) |
| 512 | #define SPM_ACK_CHK_PC_1 (SPM_BASE + 0x924) |
| 513 | #define SPM_ACK_CHK_SEL_1 (SPM_BASE + 0x928) |
| 514 | #define SPM_ACK_CHK_TIMER_1 (SPM_BASE + 0x92C) |
| 515 | #define SPM_ACK_CHK_STA_1 (SPM_BASE + 0x930) |
| 516 | #define SPM_ACK_CHK_SWINT_1 (SPM_BASE + 0x934) |
| 517 | #define SPM_ACK_CHK_CON_2 (SPM_BASE + 0x940) |
| 518 | #define SPM_ACK_CHK_PC_2 (SPM_BASE + 0x944) |
| 519 | #define SPM_ACK_CHK_SEL_2 (SPM_BASE + 0x948) |
| 520 | #define SPM_ACK_CHK_TIMER_2 (SPM_BASE + 0x94C) |
| 521 | #define SPM_ACK_CHK_STA_2 (SPM_BASE + 0x950) |
| 522 | #define SPM_ACK_CHK_SWINT_2 (SPM_BASE + 0x954) |
| 523 | #define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x960) |
| 524 | #define SPM_ACK_CHK_PC_3 (SPM_BASE + 0x964) |
| 525 | #define SPM_ACK_CHK_SEL_3 (SPM_BASE + 0x968) |
| 526 | #define SPM_ACK_CHK_TIMER_3 (SPM_BASE + 0x96C) |
| 527 | #define SPM_ACK_CHK_STA_3 (SPM_BASE + 0x970) |
| 528 | #define SPM_ACK_CHK_SWINT_3 (SPM_BASE + 0x974) |
| 529 | #define SPM_COUNTER_0 (SPM_BASE + 0x978) |
| 530 | #define SPM_COUNTER_1 (SPM_BASE + 0x97C) |
| 531 | #define SPM_COUNTER_2 (SPM_BASE + 0x980) |
| 532 | #define SYS_TIMER_CON (SPM_BASE + 0x98C) |
| 533 | #define SPM_TWAM_CON (SPM_BASE + 0x990) |
| 534 | #define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x994) |
| 535 | #define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x998) |
| 536 | #define SPM_TWAM_EVENT_CLEAR (SPM_BASE + 0x99C) |
| 537 | /*******The OTHERS*************************************************/ |
| 538 | #define RC_FSM_STA_0 (SPM_BASE + 0xE00) |
| 539 | #define RC_CMD_STA_0 (SPM_BASE + 0xE04) |
| 540 | #define RC_CMD_STA_1 (SPM_BASE + 0xE08) |
| 541 | #define RC_SPI_STA_0 (SPM_BASE + 0xE0C) |
| 542 | #define RC_PI_PO_STA_0 (SPM_BASE + 0xE10) |
| 543 | #define RC_M00_REQ_STA_0 (SPM_BASE + 0xE14) |
| 544 | #define RC_M01_REQ_STA_0 (SPM_BASE + 0xE1C) |
| 545 | #define RC_M02_REQ_STA_0 (SPM_BASE + 0xE20) |
| 546 | #define RC_M03_REQ_STA_0 (SPM_BASE + 0xE24) |
| 547 | #define RC_M04_REQ_STA_0 (SPM_BASE + 0xE28) |
| 548 | #define RC_M05_REQ_STA_0 (SPM_BASE + 0xE2C) |
| 549 | #define RC_M06_REQ_STA_0 (SPM_BASE + 0xE30) |
| 550 | #define RC_M07_REQ_STA_0 (SPM_BASE + 0xE34) |
| 551 | #define RC_M08_REQ_STA_0 (SPM_BASE + 0xE38) |
| 552 | #define RC_M09_REQ_STA_0 (SPM_BASE + 0xE3C) |
| 553 | #define RC_M10_REQ_STA_0 (SPM_BASE + 0xE40) |
| 554 | #define RC_M11_REQ_STA_0 (SPM_BASE + 0xE44) |
| 555 | #define RC_M12_REQ_STA_0 (SPM_BASE + 0xE48) |
| 556 | #define RC_DEBUG_STA_0 (SPM_BASE + 0xE4C) |
| 557 | #define RC_DEBUG_TRACE_0_LSB (SPM_BASE + 0xE50) |
| 558 | #define RC_DEBUG_TRACE_0_MSB (SPM_BASE + 0xE54) |
| 559 | #define RC_DEBUG_TRACE_1_LSB (SPM_BASE + 0xE5C) |
| 560 | #define RC_DEBUG_TRACE_1_MSB (SPM_BASE + 0xE60) |
| 561 | #define RC_DEBUG_TRACE_2_LSB (SPM_BASE + 0xE64) |
| 562 | #define RC_DEBUG_TRACE_2_MSB (SPM_BASE + 0xE6C) |
| 563 | #define RC_DEBUG_TRACE_3_LSB (SPM_BASE + 0xE70) |
| 564 | #define RC_DEBUG_TRACE_3_MSB (SPM_BASE + 0xE74) |
| 565 | #define RC_DEBUG_TRACE_4_LSB (SPM_BASE + 0xE78) |
| 566 | #define RC_DEBUG_TRACE_4_MSB (SPM_BASE + 0xE7C) |
| 567 | #define RC_DEBUG_TRACE_5_LSB (SPM_BASE + 0xE80) |
| 568 | #define RC_DEBUG_TRACE_5_MSB (SPM_BASE + 0xE84) |
| 569 | #define RC_DEBUG_TRACE_6_LSB (SPM_BASE + 0xE88) |
| 570 | #define RC_DEBUG_TRACE_6_MSB (SPM_BASE + 0xE8C) |
| 571 | #define RC_DEBUG_TRACE_7_LSB (SPM_BASE + 0xE90) |
| 572 | #define RC_DEBUG_TRACE_7_MSB (SPM_BASE + 0xE94) |
| 573 | #define RC_SYS_TIMER_LATCH_0_LSB (SPM_BASE + 0xE98) |
| 574 | #define RC_SYS_TIMER_LATCH_0_MSB (SPM_BASE + 0xE9C) |
| 575 | #define RC_SYS_TIMER_LATCH_1_LSB (SPM_BASE + 0xEA0) |
| 576 | #define RC_SYS_TIMER_LATCH_1_MSB (SPM_BASE + 0xEA4) |
| 577 | #define RC_SYS_TIMER_LATCH_2_LSB (SPM_BASE + 0xEA8) |
| 578 | #define RC_SYS_TIMER_LATCH_2_MSB (SPM_BASE + 0xEAC) |
| 579 | #define RC_SYS_TIMER_LATCH_3_LSB (SPM_BASE + 0xEB0) |
| 580 | #define RC_SYS_TIMER_LATCH_3_MSB (SPM_BASE + 0xEB4) |
| 581 | #define RC_SYS_TIMER_LATCH_4_LSB (SPM_BASE + 0xEB8) |
| 582 | #define RC_SYS_TIMER_LATCH_4_MSB (SPM_BASE + 0xEBC) |
| 583 | #define RC_SYS_TIMER_LATCH_5_LSB (SPM_BASE + 0xEC0) |
| 584 | #define RC_SYS_TIMER_LATCH_5_MSB (SPM_BASE + 0xEC4) |
| 585 | #define RC_SYS_TIMER_LATCH_6_LSB (SPM_BASE + 0xEC8) |
| 586 | #define RC_SYS_TIMER_LATCH_6_MSB (SPM_BASE + 0xECC) |
| 587 | #define RC_SYS_TIMER_LATCH_7_LSB (SPM_BASE + 0xED0) |
| 588 | #define RC_SYS_TIMER_LATCH_7_MSB (SPM_BASE + 0xED4) |
| 589 | #define PCM_WDT_LATCH_19 (SPM_BASE + 0xED8) |
| 590 | #define PCM_WDT_LATCH_20 (SPM_BASE + 0xEDC) |
| 591 | #define PCM_WDT_LATCH_21 (SPM_BASE + 0xEE0) |
| 592 | #define PCM_WDT_LATCH_22 (SPM_BASE + 0xEE4) |
| 593 | #define PCM_WDT_LATCH_23 (SPM_BASE + 0xEE8) |
| 594 | #define PCM_WDT_LATCH_24 (SPM_BASE + 0xEEC) |
| 595 | /*******Register_PMSR*************************************************/ |
| 596 | #define PMSR_LAST_DAT (SPM_BASE + 0xF00) |
| 597 | #define PMSR_LAST_CNT (SPM_BASE + 0xF04) |
| 598 | #define PMSR_LAST_ACK (SPM_BASE + 0xF08) |
| 599 | #define SPM_PMSR_SEL_CON0 (SPM_BASE + 0xF10) |
| 600 | #define SPM_PMSR_SEL_CON1 (SPM_BASE + 0xF14) |
| 601 | #define SPM_PMSR_SEL_CON2 (SPM_BASE + 0xF18) |
| 602 | #define SPM_PMSR_SEL_CON3 (SPM_BASE + 0xF1C) |
| 603 | #define SPM_PMSR_SEL_CON4 (SPM_BASE + 0xF20) |
| 604 | #define SPM_PMSR_SEL_CON5 (SPM_BASE + 0xF24) |
| 605 | #define SPM_PMSR_SEL_CON6 (SPM_BASE + 0xF28) |
| 606 | #define SPM_PMSR_SEL_CON7 (SPM_BASE + 0xF2C) |
| 607 | #define SPM_PMSR_SEL_CON8 (SPM_BASE + 0xF30) |
| 608 | #define SPM_PMSR_SEL_CON9 (SPM_BASE + 0xF34) |
| 609 | #define SPM_PMSR_SEL_CON10 (SPM_BASE + 0xF3C) |
| 610 | #define SPM_PMSR_SEL_CON11 (SPM_BASE + 0xF40) |
| 611 | #define SPM_PMSR_TIEMR_STA0 (SPM_BASE + 0xFB8) |
| 612 | #define SPM_PMSR_TIEMR_STA1 (SPM_BASE + 0xFBC) |
| 613 | #define SPM_PMSR_TIEMR_STA2 (SPM_BASE + 0xFC0) |
| 614 | #define SPM_PMSR_GENERAL_CON0 (SPM_BASE + 0xFC4) |
| 615 | #define SPM_PMSR_GENERAL_CON1 (SPM_BASE + 0xFC8) |
| 616 | #define SPM_PMSR_GENERAL_CON2 (SPM_BASE + 0xFCC) |
| 617 | #define SPM_PMSR_GENERAL_CON3 (SPM_BASE + 0xFD0) |
| 618 | #define SPM_PMSR_GENERAL_CON4 (SPM_BASE + 0xFD4) |
| 619 | #define SPM_PMSR_GENERAL_CON5 (SPM_BASE + 0xFD8) |
| 620 | #define SPM_PMSR_SW_RESET (SPM_BASE + 0xFDC) |
| 621 | #define SPM_PMSR_MON_CON0 (SPM_BASE + 0xFE0) |
| 622 | #define SPM_PMSR_MON_CON1 (SPM_BASE + 0xFE4) |
| 623 | #define SPM_PMSR_MON_CON2 (SPM_BASE + 0xFE8) |
| 624 | #define SPM_PMSR_LEN_CON0 (SPM_BASE + 0xFEC) |
| 625 | #define SPM_PMSR_LEN_CON1 (SPM_BASE + 0xFF0) |
| 626 | #define SPM_PMSR_LEN_CON2 (SPM_BASE + 0xFF4) |
| 627 | /*******Register End*************************************************/ |
| 628 | |
| 629 | /* POWERON_CONFIG_EN (0x10006000+0x000) */ |
| 630 | #define BCLK_CG_EN_LSB (1U << 0) /* 1b */ |
| 631 | #define PROJECT_CODE_LSB (1U << 16) /* 16b */ |
| 632 | /* SPM_POWER_ON_VAL0 (0x10006000+0x004) */ |
| 633 | #define POWER_ON_VAL0_LSB (1U << 0) /* 32b */ |
| 634 | /* SPM_POWER_ON_VAL1 (0x10006000+0x008) */ |
| 635 | #define POWER_ON_VAL1_LSB (1U << 0) /* 32b */ |
| 636 | /* SPM_CLK_CON (0x10006000+0x00C) */ |
| 637 | #define REG_SRCCLKEN0_CTL_LSB (1U << 0) /* 2b */ |
| 638 | #define REG_SRCCLKEN1_CTL_LSB (1U << 2) /* 2b */ |
| 639 | #define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */ |
| 640 | #define REG_SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */ |
| 641 | #define REG_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */ |
| 642 | #define REG_MD1_C32RM_EN_LSB (1U << 9) /* 1b */ |
| 643 | #define REG_MD2_C32RM_EN_LSB (1U << 10) /* 1b */ |
| 644 | #define REG_CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */ |
| 645 | #define REG_CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */ |
| 646 | #define REG_SRCCLKEN0_EN_LSB (1U << 13) /* 1b */ |
| 647 | #define REG_SRCCLKEN1_EN_LSB (1U << 14) /* 1b */ |
| 648 | #define SCP_DCM_EN_LSB (1U << 15) /* 1b */ |
| 649 | #define REG_SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 8b */ |
| 650 | #define REG_SYSCLK1_SRC_MASK_B_LSB (1U << 24) /* 8b */ |
| 651 | /* SPM_CLK_SETTLE (0x10006000+0x010) */ |
| 652 | #define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */ |
| 653 | /* SPM_AP_STANDBY_CON (0x10006000+0x014) */ |
| 654 | #define REG_WFI_OP_LSB (1U << 0) /* 1b */ |
| 655 | #define REG_WFI_TYPE_LSB (1U << 1) /* 1b */ |
| 656 | #define REG_MP0_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */ |
| 657 | #define REG_MP1_CPUTOP_IDLE_MASK_LSB (1U << 3) /* 1b */ |
| 658 | #define REG_MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */ |
| 659 | #define REG_MD_APSRC_1_SEL_LSB (1U << 25) /* 1b */ |
| 660 | #define REG_MD_APSRC_0_SEL_LSB (1U << 26) /* 1b */ |
| 661 | #define REG_CONN_APSRC_SEL_LSB (1U << 29) /* 1b */ |
| 662 | /* PCM_CON0 (0x10006000+0x018) */ |
| 663 | #define PCM_CK_EN_LSB (1U << 2) /* 1b */ |
| 664 | #define RG_EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */ |
| 665 | #define PCM_CK_FROM_CKSYS_LSB (1U << 4) /* 1b */ |
| 666 | #define PCM_SW_RESET_LSB (1U << 15) /* 1b */ |
| 667 | #define PCM_CON0_PROJECT_CODE_LSB (1U << 16) /* 16b */ |
| 668 | /* PCM_CON1 (0x10006000+0x01C) */ |
| 669 | #define RG_IM_SLAVE_LSB (1U << 0) /* 1b */ |
| 670 | #define RG_IM_SLEEP_LSB (1U << 1) /* 1b */ |
| 671 | #define REG_SPM_SRAM_CTRL_MUX_LSB (1U << 2) /* 1b */ |
| 672 | #define RG_AHBMIF_APBEN_LSB (1U << 3) /* 1b */ |
| 673 | #define RG_IM_PDN_LSB (1U << 4) /* 1b */ |
| 674 | #define RG_PCM_TIMER_EN_LSB (1U << 5) /* 1b */ |
| 675 | #define SPM_EVENT_COUNTER_CLR_LSB (1U << 6) /* 1b */ |
| 676 | #define RG_DIS_MIF_PROT_LSB (1U << 7) /* 1b */ |
| 677 | #define RG_PCM_WDT_EN_LSB (1U << 8) /* 1b */ |
| 678 | #define RG_PCM_WDT_WAKE_LSB (1U << 9) /* 1b */ |
| 679 | #define REG_SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */ |
| 680 | #define REG_SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */ |
| 681 | #define REG_EVENT_LOCK_EN_LSB (1U << 12) /* 1b */ |
| 682 | #define REG_SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */ |
| 683 | #define REG_MD32_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ |
| 684 | #define RG_PCM_IRQ_MSK_LSB (1U << 15) /* 1b */ |
| 685 | #define PCM_CON1_PROJECT_CODE_LSB (1U << 16) /* 16b */ |
| 686 | /* SPM_POWER_ON_VAL2 (0x10006000+0x020) */ |
| 687 | #define POWER_ON_VAL2_LSB (1U << 0) /* 32b */ |
| 688 | /* SPM_POWER_ON_VAL3 (0x10006000+0x024) */ |
| 689 | #define POWER_ON_VAL3_LSB (1U << 0) /* 32b */ |
| 690 | /* PCM_REG_DATA_INI (0x10006000+0x028) */ |
| 691 | #define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */ |
| 692 | /* PCM_PWR_IO_EN (0x10006000+0x02C) */ |
| 693 | #define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */ |
| 694 | #define RG_RF_SYNC_EN_LSB (1U << 16) /* 8b */ |
| 695 | /* PCM_TIMER_VAL (0x10006000+0x030) */ |
| 696 | #define REG_PCM_TIMER_VAL_LSB (1U << 0) /* 32b */ |
| 697 | /* PCM_WDT_VAL (0x10006000+0x034) */ |
| 698 | #define RG_PCM_WDT_VAL_LSB (1U << 0) /* 32b */ |
| 699 | /* SPM_SW_RST_CON (0x10006000+0x040) */ |
| 700 | #define SPM_SW_RST_CON_LSB (1U << 0) /* 16b */ |
| 701 | #define SPM_SW_RST_CON_PROJECT_CODE_LSB (1U << 16) /* 16b */ |
| 702 | /* SPM_SW_RST_CON_SET (0x10006000+0x044) */ |
| 703 | #define SPM_SW_RST_CON_SET_LSB (1U << 0) /* 16b */ |
| 704 | #define SPM_SW_RST_CON_SET_PROJECT_CODE_LSB (1U << 16) /* 16b */ |
| 705 | /* SPM_SW_RST_CON_CLR (0x10006000+0x048) */ |
| 706 | #define SPM_SW_RST_CON_CLR_LSB (1U << 0) /* 16b */ |
| 707 | #define SPM_SW_RST_CON_CLR_PROJECT_CODE_LSB (1U << 16) /* 16b */ |
| 708 | /* VS1_PSR_MASK_B (0x10006000+0x04C) */ |
| 709 | #define VS1_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */ |
| 710 | #define VS1_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */ |
| 711 | /* VS2_PSR_MASK_B (0x10006000+0x050) */ |
| 712 | #define VS2_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */ |
| 713 | #define VS2_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */ |
| 714 | #define VS2_OPP2_PSR_MASK_B_LSB (1U << 16) /* 8b */ |
| 715 | /* MD32_CLK_CON (0x10006000+0x084) */ |
| 716 | #define REG_MD32_26M_CK_SEL_LSB (1U << 0) /* 1b */ |
| 717 | #define REG_MD32_DCM_EN_LSB (1U << 1) /* 1b */ |
| 718 | /* SPM_SRAM_RSV_CON (0x10006000+0x088) */ |
| 719 | #define SPM_SRAM_SLEEP_B_ECO_EN_LSB (1U << 0) /* 1b */ |
| 720 | /* SPM_SWINT (0x10006000+0x08C) */ |
| 721 | #define SPM_SWINT_LSB (1U << 0) /* 32b */ |
| 722 | /* SPM_SWINT_SET (0x10006000+0x090) */ |
| 723 | #define SPM_SWINT_SET_LSB (1U << 0) /* 32b */ |
| 724 | /* SPM_SWINT_CLR (0x10006000+0x094) */ |
| 725 | #define SPM_SWINT_CLR_LSB (1U << 0) /* 32b */ |
| 726 | /* SPM_SCP_MAILBOX (0x10006000+0x098) */ |
| 727 | #define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */ |
| 728 | /* SCP_SPM_MAILBOX (0x10006000+0x09C) */ |
| 729 | #define SCP_SPM_MAILBOX_LSB (1U << 0) /* 32b */ |
| 730 | /* SPM_TWAM_CON (0x10006000+0x0A0) */ |
| 731 | #define REG_TWAM_ENABLE_LSB (1U << 0) /* 1b */ |
| 732 | #define REG_TWAM_SPEED_MODE_EN_LSB (1U << 1) /* 1b */ |
| 733 | #define REG_TWAM_SW_RST_LSB (1U << 2) /* 1b */ |
| 734 | #define REG_TWAM_IRQ_MASK_LSB (1U << 3) /* 1b */ |
| 735 | #define REG_TWAM_MON_TYPE_0_LSB (1U << 4) /* 2b */ |
| 736 | #define REG_TWAM_MON_TYPE_1_LSB (1U << 6) /* 2b */ |
| 737 | #define REG_TWAM_MON_TYPE_2_LSB (1U << 8) /* 2b */ |
| 738 | #define REG_TWAM_MON_TYPE_3_LSB (1U << 10) /* 2b */ |
| 739 | /* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */ |
| 740 | #define REG_TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */ |
| 741 | /* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */ |
| 742 | #define REG_TWAM_SIG_SEL_0_LSB (1U << 0) /* 7b */ |
| 743 | #define REG_TWAM_SIG_SEL_1_LSB (1U << 8) /* 7b */ |
| 744 | #define REG_TWAM_SIG_SEL_2_LSB (1U << 16) /* 7b */ |
| 745 | #define REG_TWAM_SIG_SEL_3_LSB (1U << 24) /* 7b */ |
| 746 | /* SPM_SCP_IRQ (0x10006000+0x0AC) */ |
| 747 | #define SC_SPM2SCP_WAKEUP_LSB (1U << 0) /* 1b */ |
| 748 | #define SC_SCP2SPM_WAKEUP_LSB (1U << 4) /* 1b */ |
| 749 | /* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */ |
| 750 | #define REG_CPU_WAKEUP_LSB (1U << 0) /* 1b */ |
| 751 | /* SPM_IRQ_MASK (0x10006000+0x0B4) */ |
| 752 | #define REG_SPM_IRQ_MASK_LSB (1U << 0) /* 32b */ |
| 753 | /* DDR_EN_DBC (0x10006000+0x0B4) */ |
| 754 | #define REG_ALL_DDR_EN_DBC_EN_LSB (1U << 16) /* 1b */ |
| 755 | /* SPM_SRC_REQ (0x10006000+0x0B8) */ |
| 756 | #define REG_SPM_APSRC_REQ_LSB (1U << 0) /* 1b */ |
| 757 | #define REG_SPM_F26M_REQ_LSB (1U << 1) /* 1b */ |
| 758 | #define REG_SPM_INFRA_REQ_LSB (1U << 3) /* 1b */ |
| 759 | #define REG_SPM_VRF18_REQ_LSB (1U << 4) /* 1b */ |
| 760 | #define REG_SPM_DDR_EN_REQ_LSB (1U << 7) /* 1b */ |
| 761 | #define REG_SPM_DVFS_REQ_LSB (1U << 8) /* 1b */ |
| 762 | #define REG_SPM_SW_MAILBOX_REQ_LSB (1U << 9) /* 1b */ |
| 763 | #define REG_SPM_SSPM_MAILBOX_REQ_LSB (1U << 10) /* 1b */ |
| 764 | #define REG_SPM_ADSP_MAILBOX_REQ_LSB (1U << 11) /* 1b */ |
| 765 | #define REG_SPM_SCP_MAILBOX_REQ_LSB (1U << 12) /* 1b */ |
| 766 | /* SPM_SRC_MASK (0x10006000+0x0BC) */ |
| 767 | #define REG_MD_SRCCLKENA_0_MASK_B_LSB (1U << 0) /* 1b */ |
| 768 | #define REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B_LSB (1U << 1) /* 1b */ |
| 769 | #define REG_MD_APSRC2INFRA_REQ_0_MASK_B_LSB (1U << 2) /* 1b */ |
| 770 | #define REG_MD_APSRC_REQ_0_MASK_B_LSB (1U << 3) /* 1b */ |
| 771 | #define REG_MD_VRF18_REQ_0_MASK_B_LSB (1U << 4) /* 1b */ |
| 772 | #define REG_MD_DDR_EN_0_MASK_B_LSB (1U << 5) /* 1b */ |
| 773 | #define REG_MD_SRCCLKENA_1_MASK_B_LSB (1U << 6) /* 1b */ |
| 774 | #define REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B_LSB (1U << 7) /* 1b */ |
| 775 | #define REG_MD_APSRC2INFRA_REQ_1_MASK_B_LSB (1U << 8) /* 1b */ |
| 776 | #define REG_MD_APSRC_REQ_1_MASK_B_LSB (1U << 9) /* 1b */ |
| 777 | #define REG_MD_VRF18_REQ_1_MASK_B_LSB (1U << 10) /* 1b */ |
| 778 | #define REG_MD_DDR_EN_1_MASK_B_LSB (1U << 11) /* 1b */ |
| 779 | #define REG_CONN_SRCCLKENA_MASK_B_LSB (1U << 12) /* 1b */ |
| 780 | #define REG_CONN_SRCCLKENB_MASK_B_LSB (1U << 13) /* 1b */ |
| 781 | #define REG_CONN_INFRA_REQ_MASK_B_LSB (1U << 14) /* 1b */ |
| 782 | #define REG_CONN_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */ |
| 783 | #define REG_CONN_VRF18_REQ_MASK_B_LSB (1U << 16) /* 1b */ |
| 784 | #define REG_CONN_DDR_EN_MASK_B_LSB (1U << 17) /* 1b */ |
| 785 | #define REG_CONN_VFE28_MASK_B_LSB (1U << 18) /* 1b */ |
| 786 | #define REG_SRCCLKENI0_SRCCLKENA_MASK_B_LSB (1U << 19) /* 1b */ |
| 787 | #define REG_SRCCLKENI0_INFRA_REQ_MASK_B_LSB (1U << 20) /* 1b */ |
| 788 | #define REG_SRCCLKENI1_SRCCLKENA_MASK_B_LSB (1U << 21) /* 1b */ |
| 789 | #define REG_SRCCLKENI1_INFRA_REQ_MASK_B_LSB (1U << 22) /* 1b */ |
| 790 | #define REG_SRCCLKENI2_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */ |
| 791 | #define REG_SRCCLKENI2_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */ |
| 792 | #define REG_INFRASYS_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ |
| 793 | #define REG_INFRASYS_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */ |
| 794 | #define REG_MD32_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */ |
| 795 | #define REG_MD32_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */ |
| 796 | #define REG_MD32_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ |
| 797 | #define REG_MD32_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ |
| 798 | #define REG_MD32_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */ |
| 799 | /* SPM_SRC2_MASK (0x10006000+0x0C0) */ |
| 800 | #define REG_SCP_SRCCLKENA_MASK_B_LSB (1U << 0) /* 1b */ |
| 801 | #define REG_SCP_INFRA_REQ_MASK_B_LSB (1U << 1) /* 1b */ |
| 802 | #define REG_SCP_APSRC_REQ_MASK_B_LSB (1U << 2) /* 1b */ |
| 803 | #define REG_SCP_VRF18_REQ_MASK_B_LSB (1U << 3) /* 1b */ |
| 804 | #define REG_SCP_DDR_EN_MASK_B_LSB (1U << 4) /* 1b */ |
| 805 | #define REG_AUDIO_DSP_SRCCLKENA_MASK_B_LSB (1U << 5) /* 1b */ |
| 806 | #define REG_AUDIO_DSP_INFRA_REQ_MASK_B_LSB (1U << 6) /* 1b */ |
| 807 | #define REG_AUDIO_DSP_APSRC_REQ_MASK_B_LSB (1U << 7) /* 1b */ |
| 808 | #define REG_AUDIO_DSP_VRF18_REQ_MASK_B_LSB (1U << 8) /* 1b */ |
| 809 | #define REG_AUDIO_DSP_DDR_EN_MASK_B_LSB (1U << 9) /* 1b */ |
| 810 | #define REG_UFS_SRCCLKENA_MASK_B_LSB (1U << 10) /* 1b */ |
| 811 | #define REG_UFS_INFRA_REQ_MASK_B_LSB (1U << 11) /* 1b */ |
| 812 | #define REG_UFS_APSRC_REQ_MASK_B_LSB (1U << 12) /* 1b */ |
| 813 | #define REG_UFS_VRF18_REQ_MASK_B_LSB (1U << 13) /* 1b */ |
| 814 | #define REG_UFS_DDR_EN_MASK_B_LSB (1U << 14) /* 1b */ |
| 815 | #define REG_DISP0_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */ |
| 816 | #define REG_DISP0_DDR_EN_MASK_B_LSB (1U << 16) /* 1b */ |
| 817 | #define REG_DISP1_APSRC_REQ_MASK_B_LSB (1U << 17) /* 1b */ |
| 818 | #define REG_DISP1_DDR_EN_MASK_B_LSB (1U << 18) /* 1b */ |
| 819 | #define REG_GCE_INFRA_REQ_MASK_B_LSB (1U << 19) /* 1b */ |
| 820 | #define REG_GCE_APSRC_REQ_MASK_B_LSB (1U << 20) /* 1b */ |
| 821 | #define REG_GCE_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */ |
| 822 | #define REG_GCE_DDR_EN_MASK_B_LSB (1U << 22) /* 1b */ |
| 823 | #define REG_APU_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */ |
| 824 | #define REG_APU_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */ |
| 825 | #define REG_APU_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ |
| 826 | #define REG_APU_VRF18_REQ_MASK_B_LSB (1U << 26) /* 1b */ |
| 827 | #define REG_APU_DDR_EN_MASK_B_LSB (1U << 27) /* 1b */ |
| 828 | #define REG_CG_CHECK_SRCCLKENA_MASK_B_LSB (1U << 28) /* 1b */ |
| 829 | #define REG_CG_CHECK_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ |
| 830 | #define REG_CG_CHECK_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ |
| 831 | #define REG_CG_CHECK_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */ |
| 832 | /* SPM_SRC3_MASK (0x10006000+0x0C4) */ |
| 833 | #define REG_DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 0) /* 1b */ |
| 834 | #define REG_SW2SPM_INT0_MASK_B_LSB (1U << 1) /* 1b */ |
| 835 | #define REG_SW2SPM_INT1_MASK_B_LSB (1U << 2) /* 1b */ |
| 836 | #define REG_SW2SPM_INT2_MASK_B_LSB (1U << 3) /* 1b */ |
| 837 | #define REG_SW2SPM_INT3_MASK_B_LSB (1U << 4) /* 1b */ |
| 838 | #define REG_SC_ADSP2SPM_WAKEUP_MASK_B_LSB (1U << 5) /* 1b */ |
| 839 | #define REG_SC_SSPM2SPM_WAKEUP_MASK_B_LSB (1U << 6) /* 4b */ |
| 840 | #define REG_SC_SCP2SPM_WAKEUP_MASK_B_LSB (1U << 10) /* 1b */ |
| 841 | #define REG_CSYSPWRREQ_MASK_LSB (1U << 11) /* 1b */ |
| 842 | #define REG_SPM_SRCCLKENA_RESERVED_MASK_B_LSB (1U << 12) /* 1b */ |
| 843 | #define REG_SPM_INFRA_REQ_RESERVED_MASK_B_LSB (1U << 13) /* 1b */ |
| 844 | #define REG_SPM_APSRC_REQ_RESERVED_MASK_B_LSB (1U << 14) /* 1b */ |
| 845 | #define REG_SPM_VRF18_REQ_RESERVED_MASK_B_LSB (1U << 15) /* 1b */ |
| 846 | #define REG_SPM_DDR_EN_RESERVED_MASK_B_LSB (1U << 16) /* 1b */ |
| 847 | #define REG_MCUPM_SRCCLKENA_MASK_B_LSB (1U << 17) /* 1b */ |
| 848 | #define REG_MCUPM_INFRA_REQ_MASK_B_LSB (1U << 18) /* 1b */ |
| 849 | #define REG_MCUPM_APSRC_REQ_MASK_B_LSB (1U << 19) /* 1b */ |
| 850 | #define REG_MCUPM_VRF18_REQ_MASK_B_LSB (1U << 20) /* 1b */ |
| 851 | #define REG_MCUPM_DDR_EN_MASK_B_LSB (1U << 21) /* 1b */ |
| 852 | #define REG_MSDC0_SRCCLKENA_MASK_B_LSB (1U << 22) /* 1b */ |
| 853 | #define REG_MSDC0_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */ |
| 854 | #define REG_MSDC0_APSRC_REQ_MASK_B_LSB (1U << 24) /* 1b */ |
| 855 | #define REG_MSDC0_VRF18_REQ_MASK_B_LSB (1U << 25) /* 1b */ |
| 856 | #define REG_MSDC0_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */ |
| 857 | #define REG_MSDC1_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */ |
| 858 | #define REG_MSDC1_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */ |
| 859 | #define REG_MSDC1_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ |
| 860 | #define REG_MSDC1_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ |
| 861 | #define REG_MSDC1_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */ |
| 862 | /* SPM_SRC4_MASK (0x10006000+0x0C8) */ |
| 863 | #define CCIF_EVENT_MASK_B_LSB (1U << 0) /* 16b */ |
| 864 | #define REG_BAK_PSRI_SRCCLKENA_MASK_B_LSB (1U << 16) /* 1b */ |
| 865 | #define REG_BAK_PSRI_INFRA_REQ_MASK_B_LSB (1U << 17) /* 1b */ |
| 866 | #define REG_BAK_PSRI_APSRC_REQ_MASK_B_LSB (1U << 18) /* 1b */ |
| 867 | #define REG_BAK_PSRI_VRF18_REQ_MASK_B_LSB (1U << 19) /* 1b */ |
| 868 | #define REG_BAK_PSRI_DDR_EN_MASK_B_LSB (1U << 20) /* 1b */ |
| 869 | #define REG_DRAMC0_MD32_INFRA_REQ_MASK_B_LSB (1U << 21) /* 1b */ |
| 870 | #define REG_DRAMC0_MD32_VRF18_REQ_MASK_B_LSB (1U << 22) /* 1b */ |
| 871 | #define REG_DRAMC1_MD32_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */ |
| 872 | #define REG_DRAMC1_MD32_VRF18_REQ_MASK_B_LSB (1U << 24) /* 1b */ |
| 873 | #define REG_CONN_SRCCLKENB2PWRAP_MASK_B_LSB (1U << 25) /* 1b */ |
| 874 | #define REG_DRAMC0_MD32_WAKEUP_MASK_LSB (1U << 26) /* 1b */ |
| 875 | #define REG_DRAMC1_MD32_WAKEUP_MASK_LSB (1U << 27) /* 1b */ |
| 876 | /* SPM_SRC5_MASK (0x10006000+0x0CC) */ |
| 877 | #define REG_MCUSYS_MERGE_APSRC_REQ_MASK_B_LSB (1U << 0) /* 9b */ |
| 878 | #define REG_MCUSYS_MERGE_DDR_EN_MASK_B_LSB (1U << 9) /* 9b */ |
| 879 | /* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */ |
| 880 | #define REG_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ |
| 881 | /* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0D4) */ |
| 882 | #define REG_EXT_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ |
| 883 | /* SPM_TWAM_EVENT_CLEAR (0x10006000+0x0D8) */ |
| 884 | #define SPM_TWAM_EVENT_CLEAR_LSB (1U << 0) /* 1b */ |
| 885 | /* SCP_CLK_CON (0x10006000+0x0DC) */ |
| 886 | #define REG_SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */ |
| 887 | #define REG_SCP_DCM_EN_LSB (1U << 1) /* 1b */ |
| 888 | #define SCP_SECURE_V_REQ_MASK_LSB (1U << 2) /* 1b */ |
| 889 | #define SCP_SLP_REQ_LSB (1U << 3) /* 1b */ |
| 890 | #define SCP_SLP_ACK_LSB (1U << 4) /* 1b */ |
| 891 | /* SPM_RESOURCE_ACK_CON0 (0x10006000+0x0F0) */ |
| 892 | #define REG_MD_SRCCLKENA_ACK_0_MASK_LSB (1U << 0) /* 1b */ |
| 893 | #define REG_MD_INFRA_ACK_0_MASK_LSB (1U << 1) /* 1b */ |
| 894 | #define REG_MD_APSRC_ACK_0_MASK_LSB (1U << 2) /* 1b */ |
| 895 | #define REG_MD_VRF18_ACK_0_MASK_LSB (1U << 3) /* 1b */ |
| 896 | #define REG_MD_DDR_EN_ACK_0_MASK_LSB (1U << 4) /* 1b */ |
| 897 | #define REG_MD_SRCCLKENA_ACK_1_MASK_LSB (1U << 5) /* 1b */ |
| 898 | #define REG_MD_INFRA_ACK_1_MASK_LSB (1U << 6) /* 1b */ |
| 899 | #define REG_MD_APSRC_ACK_1_MASK_LSB (1U << 7) /* 1b */ |
| 900 | #define REG_MD_VRF18_ACK_1_MASK_LSB (1U << 8) /* 1b */ |
| 901 | #define REG_MD_DDR_EN_ACK_1_MASK_LSB (1U << 9) /* 1b */ |
| 902 | #define REG_CONN_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */ |
| 903 | #define REG_CONN_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */ |
| 904 | #define REG_CONN_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */ |
| 905 | #define REG_CONN_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */ |
| 906 | #define REG_CONN_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */ |
| 907 | #define REG_MD32_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */ |
| 908 | #define REG_MD32_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */ |
| 909 | #define REG_MD32_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */ |
| 910 | #define REG_MD32_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */ |
| 911 | #define REG_MD32_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */ |
| 912 | #define REG_SCP_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */ |
| 913 | #define REG_SCP_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */ |
| 914 | #define REG_SCP_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */ |
| 915 | #define REG_SCP_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */ |
| 916 | #define REG_SCP_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */ |
| 917 | #define REG_AUDIO_DSP_SRCCLKENA_ACK_MASK_LSB (1U << 25) /* 1b */ |
| 918 | #define REG_AUDIO_DSP_INFRA_ACK_MASK_LSB (1U << 26) /* 1b */ |
| 919 | #define REG_AUDIO_DSP_APSRC_ACK_MASK_LSB (1U << 27) /* 1b */ |
| 920 | #define REG_AUDIO_DSP_VRF18_ACK_MASK_LSB (1U << 28) /* 1b */ |
| 921 | #define REG_AUDIO_DSP_DDR_EN_ACK_MASK_LSB (1U << 29) /* 1b */ |
| 922 | #define REG_DISP0_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */ |
| 923 | #define REG_DISP1_APSRC_ACK_MASK_LSB (1U << 31) /* 1b */ |
| 924 | /* SPM_RESOURCE_ACK_CON1 (0x10006000+0x0F4) */ |
| 925 | #define REG_UFS_SRCCLKENA_ACK_MASK_LSB (1U << 0) /* 1b */ |
| 926 | #define REG_UFS_INFRA_ACK_MASK_LSB (1U << 1) /* 1b */ |
| 927 | #define REG_UFS_APSRC_ACK_MASK_LSB (1U << 2) /* 1b */ |
| 928 | #define REG_UFS_VRF18_ACK_MASK_LSB (1U << 3) /* 1b */ |
| 929 | #define REG_UFS_DDR_EN_ACK_MASK_LSB (1U << 4) /* 1b */ |
| 930 | #define REG_APU_SRCCLKENA_ACK_MASK_LSB (1U << 5) /* 1b */ |
| 931 | #define REG_APU_INFRA_ACK_MASK_LSB (1U << 6) /* 1b */ |
| 932 | #define REG_APU_APSRC_ACK_MASK_LSB (1U << 7) /* 1b */ |
| 933 | #define REG_APU_VRF18_ACK_MASK_LSB (1U << 8) /* 1b */ |
| 934 | #define REG_APU_DDR_EN_ACK_MASK_LSB (1U << 9) /* 1b */ |
| 935 | #define REG_MCUPM_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */ |
| 936 | #define REG_MCUPM_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */ |
| 937 | #define REG_MCUPM_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */ |
| 938 | #define REG_MCUPM_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */ |
| 939 | #define REG_MCUPM_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */ |
| 940 | #define REG_MSDC0_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */ |
| 941 | #define REG_MSDC0_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */ |
| 942 | #define REG_MSDC0_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */ |
| 943 | #define REG_MSDC0_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */ |
| 944 | #define REG_MSDC0_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */ |
| 945 | #define REG_MSDC1_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */ |
| 946 | #define REG_MSDC1_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */ |
| 947 | #define REG_MSDC1_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */ |
| 948 | #define REG_MSDC1_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */ |
| 949 | #define REG_MSDC1_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */ |
| 950 | #define REG_DISP0_APSRC_ACK_MASK_LSB (1U << 25) /* 1b */ |
| 951 | #define REG_DISP1_DDR_EN_ACK_MASK_LSB (1U << 26) /* 1b */ |
| 952 | #define REG_GCE_INFRA_ACK_MASK_LSB (1U << 27) /* 1b */ |
| 953 | #define REG_GCE_APSRC_ACK_MASK_LSB (1U << 28) /* 1b */ |
| 954 | #define REG_GCE_VRF18_ACK_MASK_LSB (1U << 29) /* 1b */ |
| 955 | #define REG_GCE_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */ |
| 956 | /* SPM_RESOURCE_ACK_CON2 (0x10006000+0x0F8) */ |
| 957 | #define SPM_F26M_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */ |
| 958 | #define SPM_INFRA_ACK_WAIT_CYCLE_LSB (1U << 8) /* 8b */ |
| 959 | #define SPM_APSRC_ACK_WAIT_CYCLE_LSB (1U << 16) /* 8b */ |
| 960 | #define SPM_VRF18_ACK_WAIT_CYCLE_LSB (1U << 24) /* 8b */ |
| 961 | /* SPM_RESOURCE_ACK_CON3 (0x10006000+0x0FC) */ |
| 962 | #define SPM_DDR_EN_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */ |
| 963 | #define REG_BAK_PSRI_SRCCLKENA_ACK_MASK_LSB (1U << 8) /* 1b */ |
| 964 | #define REG_BAK_PSRI_INFRA_ACK_MASK_LSB (1U << 9) /* 1b */ |
| 965 | #define REG_BAK_PSRI_APSRC_ACK_MASK_LSB (1U << 10) /* 1b */ |
| 966 | #define REG_BAK_PSRI_VRF18_ACK_MASK_LSB (1U << 11) /* 1b */ |
| 967 | #define REG_BAK_PSRI_DDR_EN_ACK_MASK_LSB (1U << 12) /* 1b */ |
| 968 | /* PCM_REG0_DATA (0x10006000+0x100) */ |
| 969 | #define PCM_REG0_RF_LSB (1U << 0) /* 32b */ |
| 970 | /* PCM_REG2_DATA (0x10006000+0x104) */ |
| 971 | #define PCM_REG2_RF_LSB (1U << 0) /* 32b */ |
| 972 | /* PCM_REG6_DATA (0x10006000+0x108) */ |
| 973 | #define PCM_REG6_RF_LSB (1U << 0) /* 32b */ |
| 974 | /* PCM_REG7_DATA (0x10006000+0x10C) */ |
| 975 | #define PCM_REG7_RF_LSB (1U << 0) /* 32b */ |
| 976 | /* PCM_REG13_DATA (0x10006000+0x110) */ |
| 977 | #define PCM_REG13_RF_LSB (1U << 0) /* 32b */ |
| 978 | /* SRC_REQ_STA_0 (0x10006000+0x114) */ |
| 979 | #define MD_SRCCLKENA_0_LSB (1U << 0) /* 1b */ |
| 980 | #define MD_SRCCLKENA2INFRA_REQ_0_LSB (1U << 1) /* 1b */ |
| 981 | #define MD_APSRC2INFRA_REQ_0_LSB (1U << 2) /* 1b */ |
| 982 | #define MD_APSRC_REQ_0_LSB (1U << 3) /* 1b */ |
| 983 | #define MD_VRF18_REQ_0_LSB (1U << 4) /* 1b */ |
| 984 | #define MD_DDR_EN_0_LSB (1U << 5) /* 1b */ |
| 985 | #define MD_SRCCLKENA_1_LSB (1U << 6) /* 1b */ |
| 986 | #define MD_SRCCLKENA2INFRA_REQ_1_LSB (1U << 7) /* 1b */ |
| 987 | #define MD_APSRC2INFRA_REQ_1_LSB (1U << 8) /* 1b */ |
| 988 | #define MD_APSRC_REQ_1_LSB (1U << 9) /* 1b */ |
| 989 | #define MD_VRF18_REQ_1_LSB (1U << 10) /* 1b */ |
| 990 | #define MD_DDR_EN_1_LSB (1U << 11) /* 1b */ |
| 991 | #define CONN_SRCCLKENA_LSB (1U << 12) /* 1b */ |
| 992 | #define CONN_SRCCLKENB_LSB (1U << 13) /* 1b */ |
| 993 | #define CONN_INFRA_REQ_LSB (1U << 14) /* 1b */ |
| 994 | #define CONN_APSRC_REQ_LSB (1U << 15) /* 1b */ |
| 995 | #define CONN_VRF18_REQ_LSB (1U << 16) /* 1b */ |
| 996 | #define CONN_DDR_EN_LSB (1U << 17) /* 1b */ |
| 997 | #define SRCCLKENI_LSB (1U << 18) /* 3b */ |
| 998 | #define MD32_SRCCLKENA_LSB (1U << 21) /* 1b */ |
| 999 | #define MD32_INFRA_REQ_LSB (1U << 22) /* 1b */ |
| 1000 | #define MD32_APSRC_REQ_LSB (1U << 23) /* 1b */ |
| 1001 | #define MD32_VRF18_REQ_LSB (1U << 24) /* 1b */ |
| 1002 | #define MD32_DDR_EN_LSB (1U << 25) /* 1b */ |
| 1003 | #define DISP0_APSRC_REQ_LSB (1U << 26) /* 1b */ |
| 1004 | #define DISP0_DDR_EN_LSB (1U << 27) /* 1b */ |
| 1005 | #define DISP1_APSRC_REQ_LSB (1U << 28) /* 1b */ |
| 1006 | #define DISP1_DDR_EN_LSB (1U << 29) /* 1b */ |
| 1007 | #define DVFSRC_EVENT_TRIGGER_LSB (1U << 30) /* 1b */ |
| 1008 | /* SRC_REQ_STA_1 (0x10006000+0x118) */ |
| 1009 | #define SCP_SRCCLKENA_LSB (1U << 0) /* 1b */ |
| 1010 | #define SCP_INFRA_REQ_LSB (1U << 1) /* 1b */ |
| 1011 | #define SCP_APSRC_REQ_LSB (1U << 2) /* 1b */ |
| 1012 | #define SCP_VRF18_REQ_LSB (1U << 3) /* 1b */ |
| 1013 | #define SCP_DDR_EN_LSB (1U << 4) /* 1b */ |
| 1014 | #define AUDIO_DSP_SRCCLKENA_LSB (1U << 5) /* 1b */ |
| 1015 | #define AUDIO_DSP_INFRA_REQ_LSB (1U << 6) /* 1b */ |
| 1016 | #define AUDIO_DSP_APSRC_REQ_LSB (1U << 7) /* 1b */ |
| 1017 | #define AUDIO_DSP_VRF18_REQ_LSB (1U << 8) /* 1b */ |
| 1018 | #define AUDIO_DSP_DDR_EN_LSB (1U << 9) /* 1b */ |
| 1019 | #define UFS_SRCCLKENA_LSB (1U << 10) /* 1b */ |
| 1020 | #define UFS_INFRA_REQ_LSB (1U << 11) /* 1b */ |
| 1021 | #define UFS_APSRC_REQ_LSB (1U << 12) /* 1b */ |
| 1022 | #define UFS_VRF18_REQ_LSB (1U << 13) /* 1b */ |
| 1023 | #define UFS_DDR_EN_LSB (1U << 14) /* 1b */ |
| 1024 | #define GCE_INFRA_REQ_LSB (1U << 15) /* 1b */ |
| 1025 | #define GCE_APSRC_REQ_LSB (1U << 16) /* 1b */ |
| 1026 | #define GCE_VRF18_REQ_LSB (1U << 17) /* 1b */ |
| 1027 | #define GCE_DDR_EN_LSB (1U << 18) /* 1b */ |
| 1028 | #define INFRASYS_APSRC_REQ_LSB (1U << 19) /* 1b */ |
| 1029 | #define INFRASYS_DDR_EN_LSB (1U << 20) /* 1b */ |
| 1030 | #define MSDC0_SRCCLKENA_LSB (1U << 21) /* 1b */ |
| 1031 | #define MSDC0_INFRA_REQ_LSB (1U << 22) /* 1b */ |
| 1032 | #define MSDC0_APSRC_REQ_LSB (1U << 23) /* 1b */ |
| 1033 | #define MSDC0_VRF18_REQ_LSB (1U << 24) /* 1b */ |
| 1034 | #define MSDC0_DDR_EN_LSB (1U << 25) /* 1b */ |
| 1035 | #define MSDC1_SRCCLKENA_LSB (1U << 26) /* 1b */ |
| 1036 | #define MSDC1_INFRA_REQ_LSB (1U << 27) /* 1b */ |
| 1037 | #define MSDC1_APSRC_REQ_LSB (1U << 28) /* 1b */ |
| 1038 | #define MSDC1_VRF18_REQ_LSB (1U << 29) /* 1b */ |
| 1039 | #define MSDC1_DDR_EN_LSB (1U << 30) /* 1b */ |
| 1040 | /* SRC_REQ_STA_2 (0x10006000+0x11C) */ |
| 1041 | #define MCUSYS_MERGE_DDR_EN_LSB (1U << 0) /* 9b */ |
| 1042 | #define EMI_SELF_REFRESH_CH_LSB (1U << 9) /* 2b */ |
| 1043 | #define SW2SPM_INT_LSB (1U << 11) /* 4b */ |
| 1044 | #define SC_ADSP2SPM_WAKEUP_LSB (1U << 15) /* 1b */ |
| 1045 | #define SC_SSPM2SPM_WAKEUP_LSB (1U << 16) /* 4b */ |
| 1046 | #define SRC_REQ_STA_2_SC_SCP2SPM_WAKEUP_LSB (1U << 20) /* 1b */ |
| 1047 | #define SPM_SRCCLKENA_RESERVED_LSB (1U << 21) /* 1b */ |
| 1048 | #define SPM_INFRA_REQ_RESERVED_LSB (1U << 22) /* 1b */ |
| 1049 | #define SPM_APSRC_REQ_RESERVED_LSB (1U << 23) /* 1b */ |
| 1050 | #define SPM_VRF18_REQ_RESERVED_LSB (1U << 24) /* 1b */ |
| 1051 | #define SPM_DDR_EN_RESERVED_LSB (1U << 25) /* 1b */ |
| 1052 | #define MCUPM_SRCCLKENA_LSB (1U << 26) /* 1b */ |
| 1053 | #define MCUPM_INFRA_REQ_LSB (1U << 27) /* 1b */ |
| 1054 | #define MCUPM_APSRC_REQ_LSB (1U << 28) /* 1b */ |
| 1055 | #define MCUPM_VRF18_REQ_LSB (1U << 29) /* 1b */ |
| 1056 | #define MCUPM_DDR_EN_LSB (1U << 30) /* 1b */ |
| 1057 | /* PCM_TIMER_OUT (0x10006000+0x120) */ |
| 1058 | #define PCM_TIMER_LSB (1U << 0) /* 32b */ |
| 1059 | /* PCM_WDT_OUT (0x10006000+0x124) */ |
| 1060 | #define PCM_WDT_TIMER_VAL_OUT_LSB (1U << 0) /* 32b */ |
| 1061 | /* SPM_IRQ_STA (0x10006000+0x128) */ |
| 1062 | #define TWAM_IRQ_LSB (1U << 2) /* 1b */ |
| 1063 | #define PCM_IRQ_LSB (1U << 3) /* 1b */ |
| 1064 | /* SRC_REQ_STA_4 (0x10006000+0x12C) */ |
| 1065 | #define APU_SRCCLKENA_LSB (1U << 0) /* 1b */ |
| 1066 | #define APU_INFRA_REQ_LSB (1U << 1) /* 1b */ |
| 1067 | #define APU_APSRC_REQ_LSB (1U << 2) /* 1b */ |
| 1068 | #define APU_VRF18_REQ_LSB (1U << 3) /* 1b */ |
| 1069 | #define APU_DDR_EN_LSB (1U << 4) /* 1b */ |
| 1070 | #define BAK_PSRI_SRCCLKENA_LSB (1U << 5) /* 1b */ |
| 1071 | #define BAK_PSRI_INFRA_REQ_LSB (1U << 6) /* 1b */ |
| 1072 | #define BAK_PSRI_APSRC_REQ_LSB (1U << 7) /* 1b */ |
| 1073 | #define BAK_PSRI_VRF18_REQ_LSB (1U << 8) /* 1b */ |
| 1074 | #define BAK_PSRI_DDR_EN_LSB (1U << 9) /* 1b */ |
| 1075 | /* MD32PCM_WAKEUP_STA (0x10006000+0x130) */ |
| 1076 | #define MD32PCM_WAKEUP_STA_LSB (1U << 0) /* 32b */ |
| 1077 | /* MD32PCM_EVENT_STA (0x10006000+0x134) */ |
| 1078 | #define MD32PCM_EVENT_STA_LSB (1U << 0) /* 32b */ |
| 1079 | /* SPM_WAKEUP_STA (0x10006000+0x138) */ |
| 1080 | #define F32K_WAKEUP_EVENT_L_LSB (1U << 0) /* 16b */ |
| 1081 | #define ASYN_WAKEUP_EVENT_L_LSB (1U << 16) /* 16b */ |
| 1082 | /* SPM_WAKEUP_EXT_STA (0x10006000+0x13C) */ |
| 1083 | #define EXT_WAKEUP_EVENT_LSB (1U << 0) /* 32b */ |
| 1084 | /* SPM_WAKEUP_MISC (0x10006000+0x140) */ |
| 1085 | #define GIC_WAKEUP_LSB (1U << 0) /* 10b */ |
| 1086 | #define DVFSRC_IRQ_LSB (1U << 16) /* 1b */ |
| 1087 | #define SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB (1U << 17) /* 1b */ |
| 1088 | #define PCM_TIMER_EVENT_LSB (1U << 18) /* 1b */ |
| 1089 | #define PMIC_EINT_OUT_B_LSB (1U << 19) /* 2b */ |
| 1090 | #define TWAM_IRQ_B_LSB (1U << 21) /* 1b */ |
| 1091 | #define PMSR_IRQ_B_SET0_LSB (1U << 22) /* 1b */ |
| 1092 | #define PMSR_IRQ_B_SET1_LSB (1U << 23) /* 1b */ |
| 1093 | #define PMSR_IRQ_B_SET2_LSB (1U << 24) /* 1b */ |
| 1094 | #define SPM_ACK_CHK_WAKEUP_0_LSB (1U << 25) /* 1b */ |
| 1095 | #define SPM_ACK_CHK_WAKEUP_1_LSB (1U << 26) /* 1b */ |
| 1096 | #define SPM_ACK_CHK_WAKEUP_2_LSB (1U << 27) /* 1b */ |
| 1097 | #define SPM_ACK_CHK_WAKEUP_3_LSB (1U << 28) /* 1b */ |
| 1098 | #define SPM_ACK_CHK_WAKEUP_ALL_LSB (1U << 29) /* 1b */ |
| 1099 | #define PMIC_IRQ_ACK_LSB (1U << 30) /* 1b */ |
| 1100 | #define PMIC_SCP_IRQ_LSB (1U << 31) /* 1b */ |
| 1101 | /* MM_DVFS_HALT (0x10006000+0x144) */ |
| 1102 | #define MM_DVFS_HALT_LSB (1U << 0) /* 5b */ |
| 1103 | /* BUS_PROTECT_RDY (0x10006000+0x150) */ |
| 1104 | #define PROTECT_READY_LSB (1U << 0) /* 32b */ |
| 1105 | /* BUS_PROTECT1_RDY (0x10006000+0x154) */ |
| 1106 | #define PROTECT1_READY_LSB (1U << 0) /* 32b */ |
| 1107 | /* BUS_PROTECT2_RDY (0x10006000+0x158) */ |
| 1108 | #define PROTECT2_READY_LSB (1U << 0) /* 32b */ |
| 1109 | /* BUS_PROTECT3_RDY (0x10006000+0x15C) */ |
| 1110 | #define PROTECT3_READY_LSB (1U << 0) /* 32b */ |
| 1111 | /* SUBSYS_IDLE_STA (0x10006000+0x160) */ |
| 1112 | #define SUBSYS_IDLE_SIGNALS_LSB (1U << 0) /* 32b */ |
| 1113 | /* PCM_STA (0x10006000+0x164) */ |
| 1114 | #define PCM_CK_SEL_O_LSB (1U << 0) /* 4b */ |
| 1115 | #define EXT_SRC_STA_LSB (1U << 4) /* 3b */ |
| 1116 | /* SRC_REQ_STA_3 (0x10006000+0x168) */ |
| 1117 | #define CCIF_EVENT_RAW_STATUS_LSB (1U << 0) /* 16b */ |
| 1118 | #define F26M_STATE_LSB (1U << 16) /* 1b */ |
| 1119 | #define INFRA_STATE_LSB (1U << 17) /* 1b */ |
| 1120 | #define APSRC_STATE_LSB (1U << 18) /* 1b */ |
| 1121 | #define VRF18_STATE_LSB (1U << 19) /* 1b */ |
| 1122 | #define DDR_EN_STATE_LSB (1U << 20) /* 1b */ |
| 1123 | #define DVFS_STATE_LSB (1U << 21) /* 1b */ |
| 1124 | #define SW_MAILBOX_STATE_LSB (1U << 22) /* 1b */ |
| 1125 | #define SSPM_MAILBOX_STATE_LSB (1U << 23) /* 1b */ |
| 1126 | #define ADSP_MAILBOX_STATE_LSB (1U << 24) /* 1b */ |
| 1127 | #define SCP_MAILBOX_STATE_LSB (1U << 25) /* 1b */ |
| 1128 | /* PWR_STATUS (0x10006000+0x16C) */ |
| 1129 | #define PWR_STATUS_LSB (1U << 0) /* 32b */ |
| 1130 | /* PWR_STATUS_2ND (0x10006000+0x170) */ |
| 1131 | #define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ |
| 1132 | /* CPU_PWR_STATUS (0x10006000+0x174) */ |
| 1133 | #define MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 0) /* 1b */ |
| 1134 | #define MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 1) /* 1b */ |
| 1135 | #define MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 2) /* 1b */ |
| 1136 | #define MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 3) /* 1b */ |
| 1137 | #define MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 4) /* 1b */ |
| 1138 | #define MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 5) /* 1b */ |
| 1139 | #define MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 6) /* 1b */ |
| 1140 | #define MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 7) /* 1b */ |
| 1141 | #define MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 8) /* 1b */ |
| 1142 | #define MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 9) /* 1b */ |
| 1143 | /* OTHER_PWR_STATUS (0x10006000+0x178) */ |
| 1144 | #define OTHER_PWR_STATUS_LSB (1U << 0) /* 32b */ |
| 1145 | /* SPM_VTCXO_EVENT_COUNT_STA (0x10006000+0x17C) */ |
| 1146 | #define SPM_VTCXO_SLEEP_COUNT_LSB (1U << 0) /* 16b */ |
| 1147 | #define SPM_VTCXO_WAKE_COUNT_LSB (1U << 16) /* 16b */ |
| 1148 | /* SPM_INFRA_EVENT_COUNT_STA (0x10006000+0x180) */ |
| 1149 | #define SPM_INFRA_SLEEP_COUNT_LSB (1U << 0) /* 16b */ |
| 1150 | #define SPM_INFRA_WAKE_COUNT_LSB (1U << 16) /* 16b */ |
| 1151 | /* SPM_VRF18_EVENT_COUNT_STA (0x10006000+0x184) */ |
| 1152 | #define SPM_VRF18_SLEEP_COUNT_LSB (1U << 0) /* 16b */ |
| 1153 | #define SPM_VRF18_WAKE_COUNT_LSB (1U << 16) /* 16b */ |
| 1154 | /* SPM_APSRC_EVENT_COUNT_STA (0x10006000+0x188) */ |
| 1155 | #define SPM_APSRC_SLEEP_COUNT_LSB (1U << 0) /* 16b */ |
| 1156 | #define SPM_APSRC_WAKE_COUNT_LSB (1U << 16) /* 16b */ |
| 1157 | /* SPM_DDREN_EVENT_COUNT_STA (0x10006000+0x18C) */ |
| 1158 | #define SPM_DDREN_SLEEP_COUNT_LSB (1U << 0) /* 16b */ |
| 1159 | #define SPM_DDREN_WAKE_COUNT_LSB (1U << 16) /* 16b */ |
| 1160 | /* MD32PCM_STA (0x10006000+0x190) */ |
| 1161 | #define MD32PCM_HALT_LSB (1U << 0) /* 1b */ |
| 1162 | #define MD32PCM_GATED_LSB (1U << 1) /* 1b */ |
| 1163 | /* MD32PCM_PC (0x10006000+0x194) */ |
| 1164 | #define MON_PC_LSB (1U << 0) /* 32b */ |
| 1165 | /* DVFSRC_EVENT_STA (0x10006000+0x1A4) */ |
| 1166 | #define DVFSRC_EVENT_LSB (1U << 0) /* 32b */ |
| 1167 | /* BUS_PROTECT4_RDY (0x10006000+0x1A8) */ |
| 1168 | #define PROTECT4_READY_LSB (1U << 0) /* 32b */ |
| 1169 | /* BUS_PROTECT5_RDY (0x10006000+0x1AC) */ |
| 1170 | #define PROTECT5_READY_LSB (1U << 0) /* 32b */ |
| 1171 | /* BUS_PROTECT6_RDY (0x10006000+0x1B0) */ |
| 1172 | #define PROTECT6_READY_LSB (1U << 0) /* 32b */ |
| 1173 | /* BUS_PROTECT7_RDY (0x10006000+0x1B4) */ |
| 1174 | #define PROTECT7_READY_LSB (1U << 0) /* 32b */ |
| 1175 | /* BUS_PROTECT8_RDY (0x10006000+0x1B8) */ |
| 1176 | #define PROTECT8_READY_LSB (1U << 0) /* 32b */ |
| 1177 | /* SPM_TWAM_LAST_STA0 (0x10006000+0x1D0) */ |
| 1178 | #define LAST_IDLE_CNT_0_LSB (1U << 0) /* 32b */ |
| 1179 | /* SPM_TWAM_LAST_STA1 (0x10006000+0x1D4) */ |
| 1180 | #define LAST_IDLE_CNT_1_LSB (1U << 0) /* 32b */ |
| 1181 | /* SPM_TWAM_LAST_STA2 (0x10006000+0x1D8) */ |
| 1182 | #define LAST_IDLE_CNT_2_LSB (1U << 0) /* 32b */ |
| 1183 | /* SPM_TWAM_LAST_STA3 (0x10006000+0x1DC) */ |
| 1184 | #define LAST_IDLE_CNT_3_LSB (1U << 0) /* 32b */ |
| 1185 | /* SPM_TWAM_CURR_STA0 (0x10006000+0x1E0) */ |
| 1186 | #define CURRENT_IDLE_CNT_0_LSB (1U << 0) /* 32b */ |
| 1187 | /* SPM_TWAM_CURR_STA1 (0x10006000+0x1E4) */ |
| 1188 | #define CURRENT_IDLE_CNT_1_LSB (1U << 0) /* 32b */ |
| 1189 | /* SPM_TWAM_CURR_STA2 (0x10006000+0x1E8) */ |
| 1190 | #define CURRENT_IDLE_CNT_2_LSB (1U << 0) /* 32b */ |
| 1191 | /* SPM_TWAM_CURR_STA3 (0x10006000+0x1EC) */ |
| 1192 | #define CURRENT_IDLE_CNT_3_LSB (1U << 0) /* 32b */ |
| 1193 | /* SPM_TWAM_TIMER_OUT (0x10006000+0x1F0) */ |
| 1194 | #define TWAM_TIMER_LSB (1U << 0) /* 32b */ |
| 1195 | /* SPM_CG_CHECK_STA (0x10006000+0x1F4) */ |
| 1196 | #define SPM_CG_CHECK_SLEEP_REQ_0_LSB (1U << 0) /* 1b */ |
| 1197 | #define SPM_CG_CHECK_SLEEP_REQ_1_LSB (1U << 1) /* 1b */ |
| 1198 | #define SPM_CG_CHECK_SLEEP_REQ_2_LSB (1U << 2) /* 1b */ |
| 1199 | /* SPM_DVFS_STA (0x10006000+0x1F8) */ |
| 1200 | #define TARGET_DVFS_LEVEL_LSB (1U << 0) /* 32b */ |
| 1201 | /* SPM_DVFS_OPP_STA (0x10006000+0x1FC) */ |
| 1202 | #define TARGET_DVFS_OPP_LSB (1U << 0) /* 5b */ |
| 1203 | #define CURRENT_DVFS_OPP_LSB (1U << 5) /* 5b */ |
| 1204 | #define RELAY_DVFS_OPP_LSB (1U << 10) /* 5b */ |
| 1205 | /* SPM_MCUSYS_PWR_CON (0x10006000+0x200) */ |
| 1206 | #define MCUSYS_SPMC_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1207 | #define MCUSYS_SPMC_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1208 | #define MCUSYS_SPMC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1209 | #define MCUSYS_SPMC_RESETPWRON_CONFIG_LSB (1U << 5) /* 1b */ |
| 1210 | #define MCUSYS_SPMC_DORMANT_EN_LSB (1U << 6) /* 1b */ |
| 1211 | #define MCUSYS_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */ |
| 1212 | #define SPM_MCUSYS_PWR_CON_MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 31) /* 1b */ |
| 1213 | /* SPM_CPUTOP_PWR_CON (0x10006000+0x204) */ |
| 1214 | #define MP0_SPMC_PWR_RST_B_CPUTOP_LSB (1U << 0) /* 1b */ |
| 1215 | #define MP0_SPMC_PWR_ON_CPUTOP_LSB (1U << 2) /* 1b */ |
| 1216 | #define MP0_SPMC_PWR_CLK_DIS_CPUTOP_LSB (1U << 4) /* 1b */ |
| 1217 | #define MP0_SPMC_RESETPWRON_CONFIG_CPUTOP_LSB (1U << 5) /* 1b */ |
| 1218 | #define MP0_SPMC_DORMANT_EN_CPUTOP_LSB (1U << 6) /* 1b */ |
| 1219 | #define MP0_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */ |
| 1220 | #define MP0_VSRAM_EXT_OFF_LSB (1U << 8) /* 1b */ |
| 1221 | #define SPM_CPUTOP_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 31) /* 1b */ |
| 1222 | /* SPM_CPU0_PWR_CON (0x10006000+0x208) */ |
| 1223 | #define MP0_SPMC_PWR_RST_B_CPU0_LSB (1U << 0) /* 1b */ |
| 1224 | #define MP0_SPMC_PWR_ON_CPU0_LSB (1U << 2) /* 1b */ |
| 1225 | #define MP0_SPMC_RESETPWRON_CONFIG_CPU0_LSB (1U << 5) /* 1b */ |
| 1226 | #define MP0_VPROC_EXT_OFF_CPU0_LSB (1U << 7) /* 1b */ |
| 1227 | #define SPM_CPU0_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 31) /* 1b */ |
| 1228 | /* SPM_CPU1_PWR_CON (0x10006000+0x20C) */ |
| 1229 | #define MP0_SPMC_PWR_RST_B_CPU1_LSB (1U << 0) /* 1b */ |
| 1230 | #define MP0_SPMC_PWR_ON_CPU1_LSB (1U << 2) /* 1b */ |
| 1231 | #define MP0_SPMC_RESETPWRON_CONFIG_CPU1_LSB (1U << 5) /* 1b */ |
| 1232 | #define MP0_VPROC_EXT_OFF_CPU1_LSB (1U << 7) /* 1b */ |
| 1233 | #define SPM_CPU1_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 31) /* 1b */ |
| 1234 | /* SPM_CPU2_PWR_CON (0x10006000+0x210) */ |
| 1235 | #define MP0_SPMC_PWR_RST_B_CPU2_LSB (1U << 0) /* 1b */ |
| 1236 | #define MP0_SPMC_PWR_ON_CPU2_LSB (1U << 2) /* 1b */ |
| 1237 | #define MP0_SPMC_RESETPWRON_CONFIG_CPU2_LSB (1U << 5) /* 1b */ |
| 1238 | #define MP0_VPROC_EXT_OFF_CPU2_LSB (1U << 7) /* 1b */ |
| 1239 | #define SPM_CPU2_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 31) /* 1b */ |
| 1240 | /* SPM_CPU3_PWR_CON (0x10006000+0x214) */ |
| 1241 | #define MP0_SPMC_PWR_RST_B_CPU3_LSB (1U << 0) /* 1b */ |
| 1242 | #define MP0_SPMC_PWR_ON_CPU3_LSB (1U << 2) /* 1b */ |
| 1243 | #define MP0_SPMC_RESETPWRON_CONFIG_CPU3_LSB (1U << 5) /* 1b */ |
| 1244 | #define MP0_VPROC_EXT_OFF_CPU3_LSB (1U << 7) /* 1b */ |
| 1245 | #define SPM_CPU3_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 31) /* 1b */ |
| 1246 | /* SPM_CPU4_PWR_CON (0x10006000+0x218) */ |
| 1247 | #define MP0_SPMC_PWR_RST_B_CPU4_LSB (1U << 0) /* 1b */ |
| 1248 | #define MP0_SPMC_PWR_ON_CPU4_LSB (1U << 2) /* 1b */ |
| 1249 | #define MP0_SPMC_RESETPWRON_CONFIG_CPU4_LSB (1U << 5) /* 1b */ |
| 1250 | #define MP0_VPROC_EXT_OFF_CPU4_LSB (1U << 7) /* 1b */ |
| 1251 | #define SPM_CPU4_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 31) /* 1b */ |
| 1252 | /* SPM_CPU5_PWR_CON (0x10006000+0x21C) */ |
| 1253 | #define MP0_SPMC_PWR_RST_B_CPU5_LSB (1U << 0) /* 1b */ |
| 1254 | #define MP0_SPMC_PWR_ON_CPU5_LSB (1U << 2) /* 1b */ |
| 1255 | #define MP0_SPMC_RESETPWRON_CONFIG_CPU5_LSB (1U << 5) /* 1b */ |
| 1256 | #define MP0_VPROC_EXT_OFF_CPU5_LSB (1U << 7) /* 1b */ |
| 1257 | #define SPM_CPU5_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 31) /* 1b */ |
| 1258 | /* SPM_CPU6_PWR_CON (0x10006000+0x220) */ |
| 1259 | #define MP0_SPMC_PWR_RST_B_CPU6_LSB (1U << 0) /* 1b */ |
| 1260 | #define MP0_SPMC_PWR_ON_CPU6_LSB (1U << 2) /* 1b */ |
| 1261 | #define MP0_SPMC_RESETPWRON_CONFIG_CPU6_LSB (1U << 5) /* 1b */ |
| 1262 | #define MP0_VPROC_EXT_OFF_CPU6_LSB (1U << 7) /* 1b */ |
| 1263 | #define SPM_CPU6_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 31) /* 1b */ |
| 1264 | /* SPM_CPU7_PWR_CON (0x10006000+0x224) */ |
| 1265 | #define MP0_SPMC_PWR_RST_B_CPU7_LSB (1U << 0) /* 1b */ |
| 1266 | #define MP0_SPMC_PWR_ON_CPU7_LSB (1U << 2) /* 1b */ |
| 1267 | #define MP0_SPMC_RESETPWRON_CONFIG_CPU7_LSB (1U << 5) /* 1b */ |
| 1268 | #define MP0_VPROC_EXT_OFF_CPU7_LSB (1U << 7) /* 1b */ |
| 1269 | #define SPM_CPU7_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 31) /* 1b */ |
| 1270 | /* ARMPLL_CLK_CON (0x10006000+0x22C) */ |
| 1271 | #define SC_ARM_FHC_PAUSE_LSB (1U << 0) /* 6b */ |
| 1272 | #define SC_ARM_CK_OFF_LSB (1U << 6) /* 6b */ |
| 1273 | #define SC_ARMPLL_OFF_LSB (1U << 12) /* 1b */ |
| 1274 | #define SC_ARMBPLL_OFF_LSB (1U << 13) /* 1b */ |
| 1275 | #define SC_ARMBPLL1_OFF_LSB (1U << 14) /* 1b */ |
| 1276 | #define SC_ARMBPLL2_OFF_LSB (1U << 15) /* 1b */ |
| 1277 | #define SC_ARMBPLL3_OFF_LSB (1U << 16) /* 1b */ |
| 1278 | #define SC_CCIPLL_CKOFF_LSB (1U << 17) /* 1b */ |
| 1279 | #define SC_ARMDDS_OFF_LSB (1U << 18) /* 1b */ |
| 1280 | #define SC_ARMBPLL_S_OFF_LSB (1U << 19) /* 1b */ |
| 1281 | #define SC_ARMBPLL1_S_OFF_LSB (1U << 20) /* 1b */ |
| 1282 | #define SC_ARMBPLL2_S_OFF_LSB (1U << 21) /* 1b */ |
| 1283 | #define SC_ARMBPLL3_S_OFF_LSB (1U << 22) /* 1b */ |
| 1284 | #define SC_CCIPLL_PWROFF_LSB (1U << 23) /* 1b */ |
| 1285 | #define SC_ARMPLLOUT_OFF_LSB (1U << 24) /* 1b */ |
| 1286 | #define SC_ARMBPLLOUT_OFF_LSB (1U << 25) /* 1b */ |
| 1287 | #define SC_ARMBPLLOUT1_OFF_LSB (1U << 26) /* 1b */ |
| 1288 | #define SC_ARMBPLLOUT2_OFF_LSB (1U << 27) /* 1b */ |
| 1289 | #define SC_ARMBPLLOUT3_OFF_LSB (1U << 28) /* 1b */ |
| 1290 | #define SC_CCIPLL_OUT_OFF_LSB (1U << 29) /* 1b */ |
| 1291 | /* MCUSYS_IDLE_STA (0x10006000+0x230) */ |
| 1292 | #define ARMBUS_IDLE_TO_26M_LSB (1U << 0) /* 1b */ |
| 1293 | #define MP0_CLUSTER_IDLE_TO_PWR_OFF_LSB (1U << 1) /* 1b */ |
| 1294 | #define MCUSYS_DDR_EN_0_LSB (1U << 2) /* 1b */ |
| 1295 | #define MCUSYS_DDR_EN_1_LSB (1U << 3) /* 1b */ |
| 1296 | #define MCUSYS_DDR_EN_2_LSB (1U << 4) /* 1b */ |
| 1297 | #define MCUSYS_DDR_EN_3_LSB (1U << 5) /* 1b */ |
| 1298 | #define MCUSYS_DDR_EN_4_LSB (1U << 6) /* 1b */ |
| 1299 | #define MCUSYS_DDR_EN_5_LSB (1U << 7) /* 1b */ |
| 1300 | #define MCUSYS_DDR_EN_6_LSB (1U << 8) /* 1b */ |
| 1301 | #define MCUSYS_DDR_EN_7_LSB (1U << 9) /* 1b */ |
| 1302 | #define MP0_CPU_IDLE_TO_PWR_OFF_LSB (1U << 16) /* 8b */ |
| 1303 | #define WFI_AF_SEL_LSB (1U << 24) /* 8b */ |
| 1304 | /* GIC_WAKEUP_STA (0x10006000+0x234) */ |
| 1305 | #define GIC_WAKEUP_STA_GIC_WAKEUP_LSB (1U << 10) /* 10b */ |
| 1306 | /* CPU_SPARE_CON (0x10006000+0x238) */ |
| 1307 | #define CPU_SPARE_CON_LSB (1U << 0) /* 32b */ |
| 1308 | /* CPU_SPARE_CON_SET (0x10006000+0x23C) */ |
| 1309 | #define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */ |
| 1310 | /* CPU_SPARE_CON_CLR (0x10006000+0x240) */ |
| 1311 | #define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ |
| 1312 | /* ARMPLL_CLK_SEL (0x10006000+0x244) */ |
| 1313 | #define ARMPLL_CLK_SEL_LSB (1U << 0) /* 15b */ |
| 1314 | /* EXT_INT_WAKEUP_REQ (0x10006000+0x248) */ |
| 1315 | #define EXT_INT_WAKEUP_REQ_LSB (1U << 0) /* 10b */ |
| 1316 | /* EXT_INT_WAKEUP_REQ_SET (0x10006000+0x24C) */ |
| 1317 | #define EXT_INT_WAKEUP_REQ_SET_LSB (1U << 0) /* 10b */ |
| 1318 | /* EXT_INT_WAKEUP_REQ_CLR (0x10006000+0x250) */ |
| 1319 | #define EXT_INT_WAKEUP_REQ_CLR_LSB (1U << 0) /* 10b */ |
| 1320 | /* MP0_CPU0_IRQ_MASK (0x10006000+0x260) */ |
| 1321 | #define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ |
| 1322 | #define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */ |
| 1323 | /* MP0_CPU1_IRQ_MASK (0x10006000+0x264) */ |
| 1324 | #define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ |
| 1325 | #define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */ |
| 1326 | /* MP0_CPU2_IRQ_MASK (0x10006000+0x268) */ |
| 1327 | #define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ |
| 1328 | #define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */ |
| 1329 | /* MP0_CPU3_IRQ_MASK (0x10006000+0x26C) */ |
| 1330 | #define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ |
| 1331 | #define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */ |
| 1332 | /* MP1_CPU0_IRQ_MASK (0x10006000+0x270) */ |
| 1333 | #define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ |
| 1334 | #define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */ |
| 1335 | /* MP1_CPU1_IRQ_MASK (0x10006000+0x274) */ |
| 1336 | #define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ |
| 1337 | #define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */ |
| 1338 | /* MP1_CPU2_IRQ_MASK (0x10006000+0x278) */ |
| 1339 | #define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ |
| 1340 | #define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */ |
| 1341 | /* MP1_CPU3_IRQ_MASK (0x10006000+0x27C) */ |
| 1342 | #define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ |
| 1343 | #define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */ |
| 1344 | /* MP0_CPU0_WFI_EN (0x10006000+0x280) */ |
| 1345 | #define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ |
| 1346 | /* MP0_CPU1_WFI_EN (0x10006000+0x284) */ |
| 1347 | #define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ |
| 1348 | /* MP0_CPU2_WFI_EN (0x10006000+0x288) */ |
| 1349 | #define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ |
| 1350 | /* MP0_CPU3_WFI_EN (0x10006000+0x28C) */ |
| 1351 | #define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ |
| 1352 | /* MP0_CPU4_WFI_EN (0x10006000+0x290) */ |
| 1353 | #define MP0_CPU4_WFI_EN_LSB (1U << 0) /* 1b */ |
| 1354 | /* MP0_CPU5_WFI_EN (0x10006000+0x294) */ |
| 1355 | #define MP0_CPU5_WFI_EN_LSB (1U << 0) /* 1b */ |
| 1356 | /* MP0_CPU6_WFI_EN (0x10006000+0x298) */ |
| 1357 | #define MP0_CPU6_WFI_EN_LSB (1U << 0) /* 1b */ |
| 1358 | /* MP0_CPU7_WFI_EN (0x10006000+0x29C) */ |
| 1359 | #define MP0_CPU7_WFI_EN_LSB (1U << 0) /* 1b */ |
| 1360 | /* ROOT_CPUTOP_ADDR (0x10006000+0x2A0) */ |
| 1361 | #define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */ |
| 1362 | /* ROOT_CORE_ADDR (0x10006000+0x2A4) */ |
| 1363 | #define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */ |
| 1364 | /* SPM2SW_MAILBOX_0 (0x10006000+0x2D0) */ |
| 1365 | #define SPM2SW_MAILBOX_0_LSB (1U << 0) /* 32b */ |
| 1366 | /* SPM2SW_MAILBOX_1 (0x10006000+0x2D4) */ |
| 1367 | #define SPM2SW_MAILBOX_1_LSB (1U << 0) /* 32b */ |
| 1368 | /* SPM2SW_MAILBOX_2 (0x10006000+0x2D8) */ |
| 1369 | #define SPM2SW_MAILBOX_2_LSB (1U << 0) /* 32b */ |
| 1370 | /* SPM2SW_MAILBOX_3 (0x10006000+0x2DC) */ |
| 1371 | #define SPM2SW_MAILBOX_3_LSB (1U << 0) /* 32b */ |
| 1372 | /* SW2SPM_INT (0x10006000+0x2E0) */ |
| 1373 | #define SW2SPM_INT_SW2SPM_INT_LSB (1U << 0) /* 4b */ |
| 1374 | /* SW2SPM_INT_SET (0x10006000+0x2E4) */ |
| 1375 | #define SW2SPM_INT_SET_LSB (1U << 0) /* 4b */ |
| 1376 | /* SW2SPM_INT_CLR (0x10006000+0x2E8) */ |
| 1377 | #define SW2SPM_INT_CLR_LSB (1U << 0) /* 4b */ |
| 1378 | /* SW2SPM_MAILBOX_0 (0x10006000+0x2EC) */ |
| 1379 | #define SW2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ |
| 1380 | /* SW2SPM_MAILBOX_1 (0x10006000+0x2F0) */ |
| 1381 | #define SW2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ |
| 1382 | /* SW2SPM_MAILBOX_2 (0x10006000+0x2F4) */ |
| 1383 | #define SW2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ |
| 1384 | /* SW2SPM_MAILBOX_3 (0x10006000+0x2F8) */ |
| 1385 | #define SW2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ |
| 1386 | /* SW2SPM_CFG (0x10006000+0x2FC) */ |
| 1387 | #define SWU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */ |
| 1388 | /* MD1_PWR_CON (0x10006000+0x300) */ |
| 1389 | #define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1390 | #define MD1_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1391 | #define MD1_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1392 | #define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1393 | #define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1394 | #define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1395 | #define SC_MD1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1396 | /* CONN_PWR_CON (0x10006000+0x304) */ |
| 1397 | #define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1398 | #define CONN_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1399 | #define CONN_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1400 | #define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1401 | #define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1402 | /* MFG0_PWR_CON (0x10006000+0x308) */ |
| 1403 | #define MFG0_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1404 | #define MFG0_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1405 | #define MFG0_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1406 | #define MFG0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1407 | #define MFG0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1408 | #define MFG0_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1409 | #define SC_MFG0_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1410 | /* MFG1_PWR_CON (0x10006000+0x30C) */ |
| 1411 | #define MFG1_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1412 | #define MFG1_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1413 | #define MFG1_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1414 | #define MFG1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1415 | #define MFG1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1416 | #define MFG1_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1417 | #define SC_MFG1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1418 | /* MFG2_PWR_CON (0x10006000+0x310) */ |
| 1419 | #define MFG2_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1420 | #define MFG2_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1421 | #define MFG2_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1422 | #define MFG2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1423 | #define MFG2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1424 | #define MFG2_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1425 | #define SC_MFG2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1426 | /* MFG3_PWR_CON (0x10006000+0x314) */ |
| 1427 | #define MFG3_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1428 | #define MFG3_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1429 | #define MFG3_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1430 | #define MFG3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1431 | #define MFG3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1432 | #define MFG3_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1433 | #define SC_MFG3_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1434 | /* MFG4_PWR_CON (0x10006000+0x318) */ |
| 1435 | #define MFG4_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1436 | #define MFG4_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1437 | #define MFG4_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1438 | #define MFG4_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1439 | #define MFG4_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1440 | #define MFG4_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1441 | #define SC_MFG4_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1442 | /* MFG5_PWR_CON (0x10006000+0x31C) */ |
| 1443 | #define MFG5_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1444 | #define MFG5_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1445 | #define MFG5_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1446 | #define MFG5_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1447 | #define MFG5_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1448 | #define MFG5_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1449 | #define SC_MFG5_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1450 | /* MFG6_PWR_CON (0x10006000+0x320) */ |
| 1451 | #define MFG6_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1452 | #define MFG6_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1453 | #define MFG6_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1454 | #define MFG6_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1455 | #define MFG6_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1456 | #define MFG6_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1457 | #define SC_MFG6_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1458 | /* IFR_PWR_CON (0x10006000+0x324) */ |
| 1459 | #define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1460 | #define IFR_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1461 | #define IFR_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1462 | #define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1463 | #define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1464 | #define IFR_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1465 | #define SC_IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1466 | /* IFR_SUB_PWR_CON (0x10006000+0x328) */ |
| 1467 | #define IFR_SUB_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1468 | #define IFR_SUB_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1469 | #define IFR_SUB_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1470 | #define IFR_SUB_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1471 | #define IFR_SUB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1472 | #define IFR_SUB_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1473 | #define SC_IFR_SUB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1474 | /* DPY_PWR_CON (0x10006000+0x32C) */ |
| 1475 | #define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1476 | #define DPY_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1477 | #define DPY_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1478 | #define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1479 | #define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1480 | #define DPY_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1481 | #define SC_DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1482 | /* ISP_PWR_CON (0x10006000+0x330) */ |
| 1483 | #define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1484 | #define ISP_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1485 | #define ISP_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1486 | #define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1487 | #define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1488 | #define ISP_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1489 | #define SC_ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1490 | /* ISP2_PWR_CON (0x10006000+0x334) */ |
| 1491 | #define ISP2_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1492 | #define ISP2_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1493 | #define ISP2_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1494 | #define ISP2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1495 | #define ISP2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1496 | #define ISP2_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1497 | #define SC_ISP2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1498 | /* IPE_PWR_CON (0x10006000+0x338) */ |
| 1499 | #define IPE_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1500 | #define IPE_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1501 | #define IPE_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1502 | #define IPE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1503 | #define IPE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1504 | #define IPE_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1505 | #define SC_IPE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1506 | /* VDE_PWR_CON (0x10006000+0x33C) */ |
| 1507 | #define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1508 | #define VDE_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1509 | #define VDE_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1510 | #define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1511 | #define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1512 | #define VDE_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1513 | #define SC_VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1514 | /* VDE2_PWR_CON (0x10006000+0x340) */ |
| 1515 | #define VDE2_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1516 | #define VDE2_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1517 | #define VDE2_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1518 | #define VDE2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1519 | #define VDE2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1520 | #define VDE2_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1521 | #define SC_VDE2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1522 | /* VEN_PWR_CON (0x10006000+0x344) */ |
| 1523 | #define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1524 | #define VEN_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1525 | #define VEN_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1526 | #define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1527 | #define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1528 | #define VEN_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1529 | #define SC_VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1530 | /* VEN_CORE1_PWR_CON (0x10006000+0x348) */ |
| 1531 | #define VEN_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1532 | #define VEN_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1533 | #define VEN_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1534 | #define VEN_CORE1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1535 | #define VEN_CORE1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1536 | #define VEN_CORE1_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1537 | #define SC_VEN_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1538 | /* MDP_PWR_CON (0x10006000+0x34C) */ |
| 1539 | #define MDP_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1540 | #define MDP_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1541 | #define MDP_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1542 | #define MDP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1543 | #define MDP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1544 | #define MDP_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1545 | #define SC_MDP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1546 | /* DIS_PWR_CON (0x10006000+0x350) */ |
| 1547 | #define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1548 | #define DIS_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1549 | #define DIS_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1550 | #define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1551 | #define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1552 | #define DIS_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1553 | #define SC_DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1554 | /* AUDIO_PWR_CON (0x10006000+0x354) */ |
| 1555 | #define AUDIO_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1556 | #define AUDIO_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1557 | #define AUDIO_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1558 | #define AUDIO_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1559 | #define AUDIO_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1560 | #define AUDIO_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1561 | #define SC_AUDIO_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1562 | /* ADSP_PWR_CON (0x10006000+0x358) */ |
| 1563 | #define ADSP_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1564 | #define ADSP_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1565 | #define ADSP_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1566 | #define ADSP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1567 | #define ADSP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1568 | #define ADSP_SRAM_CKISO_LSB (1U << 5) /* 1b */ |
| 1569 | #define ADSP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ |
| 1570 | #define ADSP_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1571 | #define ADSP_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */ |
| 1572 | #define SC_ADSP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1573 | #define SC_ADSP_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */ |
| 1574 | /* CAM_PWR_CON (0x10006000+0x35C) */ |
| 1575 | #define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1576 | #define CAM_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1577 | #define CAM_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1578 | #define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1579 | #define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1580 | #define CAM_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1581 | #define SC_CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1582 | /* CAM_RAWA_PWR_CON (0x10006000+0x360) */ |
| 1583 | #define CAM_RAWA_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1584 | #define CAM_RAWA_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1585 | #define CAM_RAWA_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1586 | #define CAM_RAWA_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1587 | #define CAM_RAWA_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1588 | #define CAM_RAWA_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1589 | #define SC_CAM_RAWA_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1590 | /* CAM_RAWB_PWR_CON (0x10006000+0x364) */ |
| 1591 | #define CAM_RAWB_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1592 | #define CAM_RAWB_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1593 | #define CAM_RAWB_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1594 | #define CAM_RAWB_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1595 | #define CAM_RAWB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1596 | #define CAM_RAWB_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1597 | #define SC_CAM_RAWB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1598 | /* CAM_RAWC_PWR_CON (0x10006000+0x368) */ |
| 1599 | #define CAM_RAWC_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1600 | #define CAM_RAWC_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1601 | #define CAM_RAWC_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1602 | #define CAM_RAWC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1603 | #define CAM_RAWC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1604 | #define CAM_RAWC_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1605 | #define SC_CAM_RAWC_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1606 | /* SYSRAM_CON (0x10006000+0x36C) */ |
| 1607 | #define SYSRAM_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| 1608 | #define SYSRAM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| 1609 | #define SYSRAM_SRAM_SLEEP_B_LSB (1U << 4) /* 4b */ |
| 1610 | #define SYSRAM_SRAM_PDN_LSB (1U << 16) /* 4b */ |
| 1611 | /* SYSROM_CON (0x10006000+0x370) */ |
| 1612 | #define SYSROM_SRAM_PDN_LSB (1U << 0) /* 6b */ |
| 1613 | /* SSPM_SRAM_CON (0x10006000+0x374) */ |
| 1614 | #define SSPM_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| 1615 | #define SSPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| 1616 | #define SSPM_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ |
| 1617 | #define SSPM_SRAM_PDN_LSB (1U << 16) /* 1b */ |
| 1618 | /* SCP_SRAM_CON (0x10006000+0x378) */ |
| 1619 | #define SCP_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| 1620 | #define SCP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| 1621 | #define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ |
| 1622 | #define SCP_SRAM_PDN_LSB (1U << 16) /* 1b */ |
| 1623 | /* DPY_SHU_SRAM_CON (0x10006000+0x37C) */ |
| 1624 | #define DPY_SHU_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| 1625 | #define DPY_SHU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| 1626 | #define DPY_SHU_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */ |
| 1627 | #define DPY_SHU_SRAM_PDN_LSB (1U << 16) /* 2b */ |
| 1628 | /* UFS_SRAM_CON (0x10006000+0x380) */ |
| 1629 | #define UFS_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| 1630 | #define UFS_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| 1631 | #define UFS_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */ |
| 1632 | #define UFS_SRAM_PDN_LSB (1U << 16) /* 5b */ |
| 1633 | /* DEVAPC_IFR_SRAM_CON (0x10006000+0x384) */ |
| 1634 | #define DEVAPC_IFR_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| 1635 | #define DEVAPC_IFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| 1636 | #define DEVAPC_IFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */ |
| 1637 | #define DEVAPC_IFR_SRAM_PDN_LSB (1U << 16) /* 6b */ |
| 1638 | /* DEVAPC_SUBIFR_SRAM_CON (0x10006000+0x388) */ |
| 1639 | #define DEVAPC_SUBIFR_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| 1640 | #define DEVAPC_SUBIFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| 1641 | #define DEVAPC_SUBIFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */ |
| 1642 | #define DEVAPC_SUBIFR_SRAM_PDN_LSB (1U << 16) /* 6b */ |
| 1643 | /* DEVAPC_ACP_SRAM_CON (0x10006000+0x38C) */ |
| 1644 | #define DEVAPC_ACP_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| 1645 | #define DEVAPC_ACP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| 1646 | #define DEVAPC_ACP_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */ |
| 1647 | #define DEVAPC_ACP_SRAM_PDN_LSB (1U << 16) /* 6b */ |
| 1648 | /* USB_SRAM_CON (0x10006000+0x390) */ |
| 1649 | #define USB_SRAM_PDN_LSB (1U << 0) /* 7b */ |
| 1650 | /* DUMMY_SRAM_CON (0x10006000+0x394) */ |
| 1651 | #define DUMMY_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| 1652 | #define DUMMY_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| 1653 | #define DUMMY_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ |
| 1654 | #define DUMMY_SRAM_PDN_LSB (1U << 16) /* 8b */ |
| 1655 | /* MD_EXT_BUCK_ISO_CON (0x10006000+0x398) */ |
| 1656 | #define VMODEM_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ |
| 1657 | #define VMD_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ |
| 1658 | /* EXT_BUCK_ISO (0x10006000+0x39C) */ |
| 1659 | #define VIMVO_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ |
| 1660 | #define GPU_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ |
| 1661 | #define IPU_EXT_BUCK_ISO_LSB (1U << 5) /* 3b */ |
| 1662 | /* DXCC_SRAM_CON (0x10006000+0x3A0) */ |
| 1663 | #define DXCC_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| 1664 | #define DXCC_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| 1665 | #define DXCC_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ |
| 1666 | #define DXCC_SRAM_PDN_LSB (1U << 16) /* 1b */ |
| 1667 | /* MSDC_SRAM_CON (0x10006000+0x3A4) */ |
| 1668 | #define MSDC_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| 1669 | #define MSDC_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| 1670 | #define MSDC_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */ |
| 1671 | #define MSDC_SRAM_PDN_LSB (1U << 16) /* 5b */ |
| 1672 | /* DEBUGTOP_SRAM_CON (0x10006000+0x3A8) */ |
| 1673 | #define DEBUGTOP_SRAM_PDN_LSB (1U << 0) /* 1b */ |
| 1674 | /* DP_TX_PWR_CON (0x10006000+0x3AC) */ |
| 1675 | #define DP_TX_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1676 | #define DP_TX_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1677 | #define DP_TX_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1678 | #define DP_TX_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1679 | #define DP_TX_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1680 | #define DP_TX_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1681 | #define SC_DP_TX_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1682 | /* DPMAIF_SRAM_CON (0x10006000+0x3B0) */ |
| 1683 | #define DPMAIF_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| 1684 | #define DPMAIF_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| 1685 | #define DPMAIF_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ |
| 1686 | #define DPMAIF_SRAM_PDN_LSB (1U << 16) /* 1b */ |
| 1687 | /* DPY_SHU2_SRAM_CON (0x10006000+0x3B4) */ |
| 1688 | #define DPY_SHU2_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| 1689 | #define DPY_SHU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| 1690 | #define DPY_SHU2_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */ |
| 1691 | #define DPY_SHU2_SRAM_PDN_LSB (1U << 16) /* 2b */ |
| 1692 | /* DRAMC_MCU2_SRAM_CON (0x10006000+0x3B8) */ |
| 1693 | #define DRAMC_MCU2_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| 1694 | #define DRAMC_MCU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| 1695 | #define DRAMC_MCU2_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ |
| 1696 | #define DRAMC_MCU2_SRAM_PDN_LSB (1U << 16) /* 1b */ |
| 1697 | /* DRAMC_MCU_SRAM_CON (0x10006000+0x3BC) */ |
| 1698 | #define DRAMC_MCU_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| 1699 | #define DRAMC_MCU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| 1700 | #define DRAMC_MCU_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ |
| 1701 | #define DRAMC_MCU_SRAM_PDN_LSB (1U << 16) /* 1b */ |
| 1702 | /* MCUPM_SRAM_CON (0x10006000+0x3C0) */ |
| 1703 | #define MCUPM_SRAM_CKISO_LSB (1U << 0) /* 1b */ |
| 1704 | #define MCUPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ |
| 1705 | #define MCUPM_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ |
| 1706 | #define MCUPM_SRAM_PDN_LSB (1U << 16) /* 8b */ |
| 1707 | /* DPY2_PWR_CON (0x10006000+0x3C4) */ |
| 1708 | #define DPY2_PWR_RST_B_LSB (1U << 0) /* 1b */ |
| 1709 | #define DPY2_PWR_ISO_LSB (1U << 1) /* 1b */ |
| 1710 | #define DPY2_PWR_ON_LSB (1U << 2) /* 1b */ |
| 1711 | #define DPY2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ |
| 1712 | #define DPY2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ |
| 1713 | #define DPY2_SRAM_PDN_LSB (1U << 8) /* 1b */ |
| 1714 | #define SC_DPY2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ |
| 1715 | /* SPM_MEM_CK_SEL (0x10006000+0x400) */ |
| 1716 | #define SC_MEM_CK_SEL_LSB (1U << 0) /* 1b */ |
| 1717 | #define SPM2CKSYS_MEM_CK_MUX_UPDATE_LSB (1U << 1) /* 1b */ |
| 1718 | /* SPM_BUS_PROTECT_MASK_B (0x10006000+0X404) */ |
| 1719 | #define SPM_BUS_PROTECT_MASK_B_LSB (1U << 0) /* 32b */ |
| 1720 | /* SPM_BUS_PROTECT1_MASK_B (0x10006000+0x408) */ |
| 1721 | #define SPM_BUS_PROTECT1_MASK_B_LSB (1U << 0) /* 32b */ |
| 1722 | /* SPM_BUS_PROTECT2_MASK_B (0x10006000+0x40C) */ |
| 1723 | #define SPM_BUS_PROTECT2_MASK_B_LSB (1U << 0) /* 32b */ |
| 1724 | /* SPM_BUS_PROTECT3_MASK_B (0x10006000+0x410) */ |
| 1725 | #define SPM_BUS_PROTECT3_MASK_B_LSB (1U << 0) /* 32b */ |
| 1726 | /* SPM_BUS_PROTECT4_MASK_B (0x10006000+0x414) */ |
| 1727 | #define SPM_BUS_PROTECT4_MASK_B_LSB (1U << 0) /* 32b */ |
| 1728 | /* SPM_EMI_BW_MODE (0x10006000+0x418) */ |
| 1729 | #define EMI_BW_MODE_LSB (1U << 0) /* 1b */ |
| 1730 | #define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */ |
| 1731 | #define EMI_BW_MODE_2_LSB (1U << 2) /* 1b */ |
| 1732 | #define EMI_BOOST_MODE_2_LSB (1U << 3) /* 1b */ |
| 1733 | /* AP2MD_PEER_WAKEUP (0x10006000+0x41C) */ |
| 1734 | #define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */ |
| 1735 | /* ULPOSC_CON (0x10006000+0x420) */ |
| 1736 | #define ULPOSC_EN_LSB (1U << 0) /* 1b */ |
| 1737 | #define ULPOSC_RST_LSB (1U << 1) /* 1b */ |
| 1738 | #define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */ |
| 1739 | #define ULPOSC_CLK_SEL_LSB (1U << 3) /* 1b */ |
| 1740 | /* SPM2MM_CON (0x10006000+0x424) */ |
| 1741 | #define SPM2MM_FORCE_ULTRA_LSB (1U << 0) /* 1b */ |
| 1742 | #define SPM2MM_DBL_OSTD_ACT_LSB (1U << 1) /* 1b */ |
| 1743 | #define SPM2MM_ULTRAREQ_LSB (1U << 2) /* 1b */ |
| 1744 | #define SPM2MD_ULTRAREQ_LSB (1U << 3) /* 1b */ |
| 1745 | #define SPM2ISP_ULTRAREQ_LSB (1U << 4) /* 1b */ |
| 1746 | #define MM2SPM_FORCE_ULTRA_ACK_D2T_LSB (1U << 16) /* 1b */ |
| 1747 | #define MM2SPM_DBL_OSTD_ACT_ACK_D2T_LSB (1U << 17) /* 1b */ |
| 1748 | #define SPM2ISP_ULTRAACK_D2T_LSB (1U << 18) /* 1b */ |
| 1749 | #define SPM2MM_ULTRAACK_D2T_LSB (1U << 19) /* 1b */ |
| 1750 | #define SPM2MD_ULTRAACK_D2T_LSB (1U << 20) /* 1b */ |
| 1751 | /* SPM_BUS_PROTECT5_MASK_B (0x10006000+0x428) */ |
| 1752 | #define SPM_BUS_PROTECT5_MASK_B_LSB (1U << 0) /* 32b */ |
| 1753 | /* SPM2MCUPM_CON (0x10006000+0x42C) */ |
| 1754 | #define SPM2MCUPM_SW_RST_B_LSB (1U << 0) /* 1b */ |
| 1755 | #define SPM2MCUPM_SW_INT_LSB (1U << 1) /* 1b */ |
| 1756 | /* AP_MDSRC_REQ (0x10006000+0x430) */ |
| 1757 | #define AP_MDSMSRC_REQ_LSB (1U << 0) /* 1b */ |
| 1758 | #define AP_L1SMSRC_REQ_LSB (1U << 1) /* 1b */ |
| 1759 | #define AP_MD2SRC_REQ_LSB (1U << 2) /* 1b */ |
| 1760 | #define AP_MDSMSRC_ACK_LSB (1U << 4) /* 1b */ |
| 1761 | #define AP_L1SMSRC_ACK_LSB (1U << 5) /* 1b */ |
| 1762 | #define AP_MD2SRC_ACK_LSB (1U << 6) /* 1b */ |
| 1763 | /* SPM2EMI_ENTER_ULPM (0x10006000+0x434) */ |
| 1764 | #define SPM2EMI_ENTER_ULPM_LSB (1U << 0) /* 1b */ |
| 1765 | /* SPM2MD_DVFS_CON (0x10006000+0x438) */ |
| 1766 | #define SPM2MD_DVFS_CON_LSB (1U << 0) /* 32b */ |
| 1767 | /* MD2SPM_DVFS_CON (0x10006000+0x43C) */ |
| 1768 | #define MD2SPM_DVFS_CON_LSB (1U << 0) /* 32b */ |
| 1769 | /* SPM_BUS_PROTECT6_MASK_B (0x10006000+0X440) */ |
| 1770 | #define SPM_BUS_PROTECT6_MASK_B_LSB (1U << 0) /* 32b */ |
| 1771 | /* SPM_BUS_PROTECT7_MASK_B (0x10006000+0x444) */ |
| 1772 | #define SPM_BUS_PROTECT7_MASK_B_LSB (1U << 0) /* 32b */ |
| 1773 | /* SPM_BUS_PROTECT8_MASK_B (0x10006000+0x448) */ |
| 1774 | #define SPM_BUS_PROTECT8_MASK_B_LSB (1U << 0) /* 32b */ |
| 1775 | /* SPM_PLL_CON (0x10006000+0x44C) */ |
| 1776 | #define SC_MAINPLLOUT_OFF_LSB (1U << 0) /* 1b */ |
| 1777 | #define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */ |
| 1778 | #define SC_MAINPLL_OFF_LSB (1U << 4) /* 1b */ |
| 1779 | #define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */ |
| 1780 | #define SC_MAINPLL_S_OFF_LSB (1U << 8) /* 1b */ |
| 1781 | #define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */ |
| 1782 | #define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */ |
| 1783 | #define SC_MD32K_CK_OFF_LSB (1U << 17) /* 1b */ |
| 1784 | #define SC_CKSQ1_OFF_LSB (1U << 18) /* 1b */ |
| 1785 | #define SC_AXI_MEM_CK_OFF_LSB (1U << 19) /* 1b */ |
| 1786 | /* CPU_DVFS_REQ (0x10006000+0x450) */ |
| 1787 | #define CPU_DVFS_REQ_LSB (1U << 0) /* 32b */ |
| 1788 | /* SPM_DRAM_MCU_SW_CON_0 (0x10006000+0x454) */ |
| 1789 | #define SW_DDR_PST_REQ_LSB (1U << 0) /* 2b */ |
| 1790 | #define SW_DDR_PST_ABORT_REQ_LSB (1U << 2) /* 2b */ |
| 1791 | /* SPM_DRAM_MCU_SW_CON_1 (0x10006000+0x458) */ |
| 1792 | #define SW_DDR_PST_CH0_LSB (1U << 0) /* 32b */ |
| 1793 | /* SPM_DRAM_MCU_SW_CON_2 (0x10006000+0x45C) */ |
| 1794 | #define SW_DDR_PST_CH1_LSB (1U << 0) /* 32b */ |
| 1795 | /* SPM_DRAM_MCU_SW_CON_3 (0x10006000+0x460) */ |
| 1796 | #define SW_DDR_RESERVED_CH0_LSB (1U << 0) /* 32b */ |
| 1797 | /* SPM_DRAM_MCU_SW_CON_4 (0x10006000+0x464) */ |
| 1798 | #define SW_DDR_RESERVED_CH1_LSB (1U << 0) /* 32b */ |
| 1799 | /* SPM_DRAM_MCU_STA_0 (0x10006000+0x468) */ |
| 1800 | #define SC_DDR_PST_ACK_LSB (1U << 0) /* 2b */ |
| 1801 | #define SC_DDR_PST_ABORT_ACK_LSB (1U << 2) /* 2b */ |
| 1802 | /* SPM_DRAM_MCU_STA_1 (0x10006000+0x46C) */ |
| 1803 | #define SC_DDR_CUR_PST_STA_CH0_LSB (1U << 0) /* 32b */ |
| 1804 | /* SPM_DRAM_MCU_STA_2 (0x10006000+0x470) */ |
| 1805 | #define SC_DDR_CUR_PST_STA_CH1_LSB (1U << 0) /* 32b */ |
| 1806 | /* SPM_DRAM_MCU_SW_SEL_0 (0x10006000+0x474) */ |
| 1807 | #define SW_DDR_PST_REQ_SEL_LSB (1U << 0) /* 2b */ |
| 1808 | #define SW_DDR_PST_SEL_LSB (1U << 2) /* 2b */ |
| 1809 | #define SW_DDR_PST_ABORT_REQ_SEL_LSB (1U << 4) /* 2b */ |
| 1810 | #define SW_DDR_RESERVED_SEL_LSB (1U << 6) /* 2b */ |
| 1811 | #define SW_DDR_PST_ACK_SEL_LSB (1U << 8) /* 2b */ |
| 1812 | #define SW_DDR_PST_ABORT_ACK_SEL_LSB (1U << 10) /* 2b */ |
| 1813 | /* RELAY_DVFS_LEVEL (0x10006000+0x478) */ |
| 1814 | #define RELAY_DVFS_LEVEL_LSB (1U << 0) /* 32b */ |
| 1815 | /* DRAMC_DPY_CLK_SW_CON_0 (0x10006000+0x480) */ |
| 1816 | #define SW_PHYPLL_EN_LSB (1U << 0) /* 2b */ |
| 1817 | #define SW_DPY_VREF_EN_LSB (1U << 2) /* 2b */ |
| 1818 | #define SW_DPY_DLL_CK_EN_LSB (1U << 4) /* 2b */ |
| 1819 | #define SW_DPY_DLL_EN_LSB (1U << 6) /* 2b */ |
| 1820 | #define SW_DPY_2ND_DLL_EN_LSB (1U << 8) /* 2b */ |
| 1821 | #define SW_MEM_CK_OFF_LSB (1U << 10) /* 2b */ |
| 1822 | #define SW_DMSUS_OFF_LSB (1U << 12) /* 2b */ |
| 1823 | #define SW_DPY_MODE_SW_LSB (1U << 14) /* 2b */ |
| 1824 | #define SW_EMI_CLK_OFF_LSB (1U << 16) /* 2b */ |
| 1825 | #define SW_DDRPHY_FB_CK_EN_LSB (1U << 18) /* 2b */ |
| 1826 | #define SW_DR_GATE_RETRY_EN_LSB (1U << 20) /* 2b */ |
| 1827 | #define SW_DPHY_PRECAL_UP_LSB (1U << 24) /* 2b */ |
| 1828 | #define SW_DPY_BCLK_ENABLE_LSB (1U << 26) /* 2b */ |
| 1829 | #define SW_TX_TRACKING_DIS_LSB (1U << 28) /* 2b */ |
| 1830 | #define SW_DPHY_RXDLY_TRACKING_EN_LSB (1U << 30) /* 2b */ |
| 1831 | /* DRAMC_DPY_CLK_SW_CON_1 (0x10006000+0x484) */ |
| 1832 | #define SW_SHU_RESTORE_LSB (1U << 0) /* 2b */ |
| 1833 | #define SW_DMYRD_MOD_LSB (1U << 2) /* 2b */ |
| 1834 | #define SW_DMYRD_INTV_LSB (1U << 4) /* 2b */ |
| 1835 | #define SW_DMYRD_EN_LSB (1U << 6) /* 2b */ |
| 1836 | #define SW_DRS_DIS_REQ_LSB (1U << 8) /* 2b */ |
| 1837 | #define SW_DR_SRAM_LOAD_LSB (1U << 10) /* 2b */ |
| 1838 | #define SW_DR_SRAM_RESTORE_LSB (1U << 12) /* 2b */ |
| 1839 | #define SW_DR_SHU_LEVEL_SRAM_LATCH_LSB (1U << 14) /* 2b */ |
| 1840 | #define SW_TX_TRACK_RETRY_EN_LSB (1U << 16) /* 2b */ |
| 1841 | #define SW_DPY_MIDPI_EN_LSB (1U << 18) /* 2b */ |
| 1842 | #define SW_DPY_PI_RESETB_EN_LSB (1U << 20) /* 2b */ |
| 1843 | #define SW_DPY_MCK8X_EN_LSB (1U << 22) /* 2b */ |
| 1844 | #define SW_DR_SHU_LEVEL_SRAM_CH0_LSB (1U << 24) /* 4b */ |
| 1845 | #define SW_DR_SHU_LEVEL_SRAM_CH1_LSB (1U << 28) /* 4b */ |
| 1846 | /* DRAMC_DPY_CLK_SW_CON_2 (0x10006000+0x488) */ |
| 1847 | #define SW_DR_SHU_LEVEL_LSB (1U << 0) /* 2b */ |
| 1848 | #define SW_DR_SHU_EN_LSB (1U << 2) /* 1b */ |
| 1849 | #define SW_DR_SHORT_QUEUE_LSB (1U << 3) /* 1b */ |
| 1850 | #define SW_PHYPLL_MODE_SW_LSB (1U << 4) /* 1b */ |
| 1851 | #define SW_PHYPLL2_MODE_SW_LSB (1U << 5) /* 1b */ |
| 1852 | #define SW_PHYPLL_SHU_EN_LSB (1U << 6) /* 1b */ |
| 1853 | #define SW_PHYPLL2_SHU_EN_LSB (1U << 7) /* 1b */ |
| 1854 | #define SW_DR_RESERVED_0_LSB (1U << 24) /* 2b */ |
| 1855 | #define SW_DR_RESERVED_1_LSB (1U << 26) /* 2b */ |
| 1856 | #define SW_DR_RESERVED_2_LSB (1U << 28) /* 2b */ |
| 1857 | #define SW_DR_RESERVED_3_LSB (1U << 30) /* 2b */ |
| 1858 | /* DRAMC_DPY_CLK_SW_CON_3 (0x10006000+0x48C) */ |
| 1859 | #define SC_DR_SHU_EN_ACK_LSB (1U << 0) /* 4b */ |
| 1860 | #define SC_EMI_CLK_OFF_ACK_LSB (1U << 4) /* 4b */ |
| 1861 | #define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 8) /* 4b */ |
| 1862 | #define SC_DRAMC_DFS_STA_LSB (1U << 12) /* 4b */ |
| 1863 | #define SC_DRS_DIS_ACK_LSB (1U << 16) /* 4b */ |
| 1864 | #define SC_DR_SRAM_LOAD_ACK_LSB (1U << 20) /* 4b */ |
| 1865 | #define SC_DR_SRAM_PLL_LOAD_ACK_LSB (1U << 24) /* 4b */ |
| 1866 | #define SC_DR_SRAM_RESTORE_ACK_LSB (1U << 28) /* 4b */ |
| 1867 | /* DRAMC_DPY_CLK_SW_SEL_0 (0x10006000+0x490) */ |
| 1868 | #define SW_PHYPLL_EN_SEL_LSB (1U << 0) /* 2b */ |
| 1869 | #define SW_DPY_VREF_EN_SEL_LSB (1U << 2) /* 2b */ |
| 1870 | #define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 4) /* 2b */ |
| 1871 | #define SW_DPY_DLL_EN_SEL_LSB (1U << 6) /* 2b */ |
| 1872 | #define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 8) /* 2b */ |
| 1873 | #define SW_MEM_CK_OFF_SEL_LSB (1U << 10) /* 2b */ |
| 1874 | #define SW_DMSUS_OFF_SEL_LSB (1U << 12) /* 2b */ |
| 1875 | #define SW_DPY_MODE_SW_SEL_LSB (1U << 14) /* 2b */ |
| 1876 | #define SW_EMI_CLK_OFF_SEL_LSB (1U << 16) /* 2b */ |
| 1877 | #define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 18) /* 2b */ |
| 1878 | #define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 20) /* 2b */ |
| 1879 | #define SW_DPHY_PRECAL_UP_SEL_LSB (1U << 24) /* 2b */ |
| 1880 | #define SW_DPY_BCLK_ENABLE_SEL_LSB (1U << 26) /* 2b */ |
| 1881 | #define SW_TX_TRACKING_DIS_SEL_LSB (1U << 28) /* 2b */ |
| 1882 | #define SW_DPHY_RXDLY_TRACKING_EN_SEL_LSB (1U << 30) /* 2b */ |
| 1883 | /* DRAMC_DPY_CLK_SW_SEL_1 (0x10006000+0x494) */ |
| 1884 | #define SW_SHU_RESTORE_SEL_LSB (1U << 0) /* 2b */ |
| 1885 | #define SW_DMYRD_MOD_SEL_LSB (1U << 2) /* 2b */ |
| 1886 | #define SW_DMYRD_INTV_SEL_LSB (1U << 4) /* 2b */ |
| 1887 | #define SW_DMYRD_EN_SEL_LSB (1U << 6) /* 2b */ |
| 1888 | #define SW_DRS_DIS_REQ_SEL_LSB (1U << 8) /* 2b */ |
| 1889 | #define SW_DR_SRAM_LOAD_SEL_LSB (1U << 10) /* 2b */ |
| 1890 | #define SW_DR_SRAM_RESTORE_SEL_LSB (1U << 12) /* 2b */ |
| 1891 | #define SW_DR_SHU_LEVEL_SRAM_LATCH_SEL_LSB (1U << 14) /* 2b */ |
| 1892 | #define SW_TX_TRACK_RETRY_EN_SEL_LSB (1U << 16) /* 2b */ |
| 1893 | #define SW_DPY_MIDPI_EN_SEL_LSB (1U << 18) /* 2b */ |
| 1894 | #define SW_DPY_PI_RESETB_EN_SEL_LSB (1U << 20) /* 2b */ |
| 1895 | #define SW_DPY_MCK8X_EN_SEL_LSB (1U << 22) /* 2b */ |
| 1896 | #define SW_DR_SHU_LEVEL_SRAM_SEL_LSB (1U << 24) /* 2b */ |
| 1897 | /* DRAMC_DPY_CLK_SW_SEL_2 (0x10006000+0x498) */ |
| 1898 | #define SW_DR_SHU_LEVEL_SEL_LSB (1U << 0) /* 1b */ |
| 1899 | #define SW_DR_SHU_EN_SEL_LSB (1U << 2) /* 1b */ |
| 1900 | #define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 3) /* 1b */ |
| 1901 | #define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 4) /* 1b */ |
| 1902 | #define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 5) /* 1b */ |
| 1903 | #define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 6) /* 1b */ |
| 1904 | #define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 7) /* 1b */ |
| 1905 | #define SW_DR_RESERVED_0_SEL_LSB (1U << 24) /* 2b */ |
| 1906 | #define SW_DR_RESERVED_1_SEL_LSB (1U << 26) /* 2b */ |
| 1907 | #define SW_DR_RESERVED_2_SEL_LSB (1U << 28) /* 2b */ |
| 1908 | #define SW_DR_RESERVED_3_SEL_LSB (1U << 30) /* 2b */ |
| 1909 | /* DRAMC_DPY_CLK_SW_SEL_3 (0x10006000+0x49C) */ |
| 1910 | #define SC_DR_SHU_EN_ACK_SEL_LSB (1U << 0) /* 4b */ |
| 1911 | #define SC_EMI_CLK_OFF_ACK_SEL_LSB (1U << 4) /* 4b */ |
| 1912 | #define SC_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 8) /* 4b */ |
| 1913 | #define SC_DRAMC_DFS_STA_SEL_LSB (1U << 12) /* 4b */ |
| 1914 | #define SC_DRS_DIS_ACK_SEL_LSB (1U << 16) /* 4b */ |
| 1915 | #define SC_DR_SRAM_LOAD_ACK_SEL_LSB (1U << 20) /* 4b */ |
| 1916 | #define SC_DR_SRAM_PLL_LOAD_ACK_SEL_LSB (1U << 24) /* 4b */ |
| 1917 | #define SC_DR_SRAM_RESTORE_ACK_SEL_LSB (1U << 28) /* 4b */ |
| 1918 | /* DRAMC_DPY_CLK_SPM_CON (0x10006000+0x4A0) */ |
| 1919 | #define SC_DMYRD_EN_MOD_SEL_PCM_LSB (1U << 0) /* 1b */ |
| 1920 | #define SC_DMYRD_INTV_SEL_PCM_LSB (1U << 1) /* 1b */ |
| 1921 | #define SC_DMYRD_EN_PCM_LSB (1U << 2) /* 1b */ |
| 1922 | #define SC_DRS_DIS_REQ_PCM_LSB (1U << 3) /* 1b */ |
| 1923 | #define SC_DR_SHU_LEVEL_SRAM_PCM_LSB (1U << 4) /* 4b */ |
| 1924 | #define SC_DR_GATE_RETRY_EN_PCM_LSB (1U << 8) /* 1b */ |
| 1925 | #define SC_DR_SHORT_QUEUE_PCM_LSB (1U << 9) /* 1b */ |
| 1926 | #define SC_DPY_MIDPI_EN_PCM_LSB (1U << 10) /* 1b */ |
| 1927 | #define SC_DPY_PI_RESETB_EN_PCM_LSB (1U << 11) /* 1b */ |
| 1928 | #define SC_DPY_MCK8X_EN_PCM_LSB (1U << 12) /* 1b */ |
| 1929 | #define SC_DR_RESERVED_0_PCM_LSB (1U << 13) /* 1b */ |
| 1930 | #define SC_DR_RESERVED_1_PCM_LSB (1U << 14) /* 1b */ |
| 1931 | #define SC_DR_RESERVED_2_PCM_LSB (1U << 15) /* 1b */ |
| 1932 | #define SC_DR_RESERVED_3_PCM_LSB (1U << 16) /* 1b */ |
| 1933 | #define SC_DMDRAMCSHU_ACK_ALL_LSB (1U << 24) /* 1b */ |
| 1934 | #define SC_EMI_CLK_OFF_ACK_ALL_LSB (1U << 25) /* 1b */ |
| 1935 | #define SC_DR_SHORT_QUEUE_ACK_ALL_LSB (1U << 26) /* 1b */ |
| 1936 | #define SC_DRAMC_DFS_STA_ALL_LSB (1U << 27) /* 1b */ |
| 1937 | #define SC_DRS_DIS_ACK_ALL_LSB (1U << 28) /* 1b */ |
| 1938 | #define SC_DR_SRAM_LOAD_ACK_ALL_LSB (1U << 29) /* 1b */ |
| 1939 | #define SC_DR_SRAM_PLL_LOAD_ACK_ALL_LSB (1U << 30) /* 1b */ |
| 1940 | #define SC_DR_SRAM_RESTORE_ACK_ALL_LSB (1U << 31) /* 1b */ |
| 1941 | /* SPM_DVFS_LEVEL (0x10006000+0x4A4) */ |
| 1942 | #define SPM_DVFS_LEVEL_LSB (1U << 0) /* 32b */ |
| 1943 | /* SPM_CIRQ_CON (0x10006000+0x4A8) */ |
| 1944 | #define CIRQ_CLK_SEL_LSB (1U << 0) /* 1b */ |
| 1945 | /* SPM_DVFS_MISC (0x10006000+0x4AC) */ |
| 1946 | #define MSDC_DVFS_REQUEST_LSB (1U << 0) /* 1b */ |
| 1947 | #define SPM2EMI_SLP_PROT_EN_LSB (1U << 1) /* 1b */ |
| 1948 | #define SPM_DVFS_FORCE_ENABLE_LSB (1U << 2) /* 1b */ |
| 1949 | #define FORCE_DVFS_WAKE_LSB (1U << 3) /* 1b */ |
| 1950 | #define SPM_DVFSRC_ENABLE_LSB (1U << 4) /* 1b */ |
| 1951 | #define SPM_DVFS_DONE_LSB (1U << 5) /* 1b */ |
| 1952 | #define DVFSRC_IRQ_WAKEUP_EVENT_MASK_LSB (1U << 6) /* 1b */ |
| 1953 | #define SPM2RC_EVENT_ABORT_LSB (1U << 7) /* 1b */ |
| 1954 | #define EMI_SLP_IDLE_LSB (1U << 14) /* 1b */ |
| 1955 | #define SDIO_READY_TO_SPM_LSB (1U << 15) /* 1b */ |
| 1956 | /* SPM_VS1_VS2_RC_CON (0x10006000+0x4B0) */ |
| 1957 | #define VS1_INIT_LEVEL_LSB (1U << 0) /* 2b */ |
| 1958 | #define VS1_INIT_LSB (1U << 2) /* 1b */ |
| 1959 | #define VS1_CURR_LEVEL_LSB (1U << 3) /* 2b */ |
| 1960 | #define VS1_NEXT_LEVEL_LSB (1U << 5) /* 2b */ |
| 1961 | #define VS1_VOTE_LEVEL_LSB (1U << 7) /* 2b */ |
| 1962 | #define VS1_TRIGGER_LSB (1U << 9) /* 1b */ |
| 1963 | #define VS2_INIT_LEVEL_LSB (1U << 10) /* 3b */ |
| 1964 | #define VS2_INIT_LSB (1U << 13) /* 1b */ |
| 1965 | #define VS2_CURR_LEVEL_LSB (1U << 14) /* 3b */ |
| 1966 | #define VS2_NEXT_LEVEL_LSB (1U << 17) /* 3b */ |
| 1967 | #define VS2_VOTE_LEVEL_LSB (1U << 20) /* 3b */ |
| 1968 | #define VS2_TRIGGER_LSB (1U << 23) /* 1b */ |
| 1969 | #define VS1_FORCE_LSB (1U << 24) /* 1b */ |
| 1970 | #define VS2_FORCE_LSB (1U << 25) /* 1b */ |
| 1971 | #define VS1_VOTE_LEVEL_FORCE_LSB (1U << 26) /* 2b */ |
| 1972 | #define VS2_VOTE_LEVEL_FORCE_LSB (1U << 28) /* 3b */ |
| 1973 | /* RG_MODULE_SW_CG_0_MASK_REQ_0 (0x10006000+0x4B4) */ |
| 1974 | #define RG_MODULE_SW_CG_0_MASK_REQ_0_LSB (1U << 0) /* 32b */ |
| 1975 | /* RG_MODULE_SW_CG_0_MASK_REQ_1 (0x10006000+0x4B8) */ |
| 1976 | #define RG_MODULE_SW_CG_0_MASK_REQ_1_LSB (1U << 0) /* 32b */ |
| 1977 | /* RG_MODULE_SW_CG_0_MASK_REQ_2 (0x10006000+0x4BC) */ |
| 1978 | #define RG_MODULE_SW_CG_0_MASK_REQ_2_LSB (1U << 0) /* 32b */ |
| 1979 | /* RG_MODULE_SW_CG_1_MASK_REQ_0 (0x10006000+0x4C0) */ |
| 1980 | #define RG_MODULE_SW_CG_1_MASK_REQ_0_LSB (1U << 0) /* 32b */ |
| 1981 | /* RG_MODULE_SW_CG_1_MASK_REQ_1 (0x10006000+0x4C4) */ |
| 1982 | #define RG_MODULE_SW_CG_1_MASK_REQ_1_LSB (1U << 0) /* 32b */ |
| 1983 | /* RG_MODULE_SW_CG_1_MASK_REQ_2 (0x10006000+0x4C8) */ |
| 1984 | #define RG_MODULE_SW_CG_1_MASK_REQ_2_LSB (1U << 0) /* 32b */ |
| 1985 | /* RG_MODULE_SW_CG_2_MASK_REQ_0 (0x10006000+0x4CC) */ |
| 1986 | #define RG_MODULE_SW_CG_2_MASK_REQ_0_LSB (1U << 0) /* 32b */ |
| 1987 | /* RG_MODULE_SW_CG_2_MASK_REQ_1 (0x10006000+0x4D0) */ |
| 1988 | #define RG_MODULE_SW_CG_2_MASK_REQ_1_LSB (1U << 0) /* 32b */ |
| 1989 | /* RG_MODULE_SW_CG_2_MASK_REQ_2 (0x10006000+0x4D4) */ |
| 1990 | #define RG_MODULE_SW_CG_2_MASK_REQ_2_LSB (1U << 0) /* 32b */ |
| 1991 | /* RG_MODULE_SW_CG_3_MASK_REQ_0 (0x10006000+0x4D8) */ |
| 1992 | #define RG_MODULE_SW_CG_3_MASK_REQ_0_LSB (1U << 0) /* 32b */ |
| 1993 | /* RG_MODULE_SW_CG_3_MASK_REQ_1 (0x10006000+0x4DC) */ |
| 1994 | #define RG_MODULE_SW_CG_3_MASK_REQ_1_LSB (1U << 0) /* 32b */ |
| 1995 | /* RG_MODULE_SW_CG_3_MASK_REQ_2 (0x10006000+0x4E0) */ |
| 1996 | #define RG_MODULE_SW_CG_3_MASK_REQ_2_LSB (1U << 0) /* 32b */ |
| 1997 | /* PWR_STATUS_MASK_REQ_0 (0x10006000+0x4E4) */ |
| 1998 | #define PWR_STATUS_MASK_REQ_0_LSB (1U << 0) /* 32b */ |
| 1999 | /* PWR_STATUS_MASK_REQ_1 (0x10006000+0x4E8) */ |
| 2000 | #define PWR_STATUS_MASK_REQ_1_LSB (1U << 0) /* 32b */ |
| 2001 | /* PWR_STATUS_MASK_REQ_2 (0x10006000+0x4EC) */ |
| 2002 | #define PWR_STATUS_MASK_REQ_2_LSB (1U << 0) /* 32b */ |
| 2003 | /* SPM_CG_CHECK_CON (0x10006000+0x4F0) */ |
| 2004 | #define APMIXEDSYS_BUSY_MASK_REQ_0_LSB (1U << 0) /* 5b */ |
| 2005 | #define APMIXEDSYS_BUSY_MASK_REQ_1_LSB (1U << 8) /* 5b */ |
| 2006 | #define APMIXEDSYS_BUSY_MASK_REQ_2_LSB (1U << 16) /* 5b */ |
| 2007 | #define AUDIOSYS_BUSY_MASK_REQ_0_LSB (1U << 24) /* 1b */ |
| 2008 | #define AUDIOSYS_BUSY_MASK_REQ_1_LSB (1U << 25) /* 1b */ |
| 2009 | #define AUDIOSYS_BUSY_MASK_REQ_2_LSB (1U << 26) /* 1b */ |
| 2010 | #define SSUSB_BUSY_MASK_REQ_0_LSB (1U << 27) /* 1b */ |
| 2011 | #define SSUSB_BUSY_MASK_REQ_1_LSB (1U << 28) /* 1b */ |
| 2012 | #define SSUSB_BUSY_MASK_REQ_2_LSB (1U << 29) /* 1b */ |
| 2013 | /* SPM_SRC_RDY_STA (0x10006000+0x4F4) */ |
| 2014 | #define SPM_INFRA_INTERNAL_ACK_LSB (1U << 0) /* 1b */ |
| 2015 | #define SPM_VRF18_INTERNAL_ACK_LSB (1U << 1) /* 1b */ |
| 2016 | /* SPM_DVS_DFS_LEVEL (0x10006000+0x4F8) */ |
| 2017 | #define SPM_DFS_LEVEL_LSB (1U << 0) /* 16b */ |
| 2018 | #define SPM_DVS_LEVEL_LSB (1U << 16) /* 16b */ |
| 2019 | /* SPM_FORCE_DVFS (0x10006000+0x4FC) */ |
| 2020 | #define FORCE_DVFS_LEVEL_LSB (1U << 0) /* 32b */ |
| 2021 | /* SRCLKEN_RC_CFG (0x10006000+0x500) */ |
| 2022 | #define SRCLKEN_RC_CFG_LSB (1U << 0) /* 32b */ |
| 2023 | /* RC_CENTRAL_CFG1 (0x10006000+0x504) */ |
| 2024 | #define RC_CENTRAL_CFG1_LSB (1U << 0) /* 32b */ |
| 2025 | /* RC_CENTRAL_CFG2 (0x10006000+0x508) */ |
| 2026 | #define RC_CENTRAL_CFG2_LSB (1U << 0) /* 32b */ |
| 2027 | /* RC_CMD_ARB_CFG (0x10006000+0x50C) */ |
| 2028 | #define RC_CMD_ARB_CFG_LSB (1U << 0) /* 32b */ |
| 2029 | /* RC_PMIC_RCEN_ADDR (0x10006000+0x510) */ |
| 2030 | #define RC_PMIC_RCEN_ADDR_LSB (1U << 0) /* 16b */ |
| 2031 | #define RC_PMIC_RCEN_RESERVE_LSB (1U << 16) /* 16b */ |
| 2032 | /* RC_PMIC_RCEN_SET_CLR_ADDR (0x10006000+0x514) */ |
| 2033 | #define RC_PMIC_RCEN_SET_ADDR_LSB (1U << 0) /* 16b */ |
| 2034 | #define RC_PMIC_RCEN_CLR_ADDR_LSB (1U << 16) /* 16b */ |
| 2035 | /* RC_DCXO_FPM_CFG (0x10006000+0x518) */ |
| 2036 | #define RC_DCXO_FPM_CFG_LSB (1U << 0) /* 32b */ |
| 2037 | /* RC_CENTRAL_CFG3 (0x10006000+0x51C) */ |
| 2038 | #define RC_CENTRAL_CFG3_LSB (1U << 0) /* 32b */ |
| 2039 | /* RC_M00_SRCLKEN_CFG (0x10006000+0x520) */ |
| 2040 | #define RC_M00_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| 2041 | #define RC_SW_SRCLKEN_RC (1U << 3) /* 1b */ |
| 2042 | #define RC_SW_SRCLKEN_FPM (1U << 4) /* 1b */ |
| 2043 | /* RC_M01_SRCLKEN_CFG (0x10006000+0x524) */ |
| 2044 | #define RC_M01_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| 2045 | /* RC_M02_SRCLKEN_CFG (0x10006000+0x528) */ |
| 2046 | #define RC_M02_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| 2047 | /* RC_M03_SRCLKEN_CFG (0x10006000+0x52C) */ |
| 2048 | #define RC_M03_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| 2049 | /* RC_M04_SRCLKEN_CFG (0x10006000+0x530) */ |
| 2050 | #define RC_M04_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| 2051 | /* RC_M05_SRCLKEN_CFG (0x10006000+0x534) */ |
| 2052 | #define RC_M05_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| 2053 | /* RC_M06_SRCLKEN_CFG (0x10006000+0x538) */ |
| 2054 | #define RC_M06_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| 2055 | /* RC_M07_SRCLKEN_CFG (0x10006000+0x53C) */ |
| 2056 | #define RC_M07_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| 2057 | /* RC_M08_SRCLKEN_CFG (0x10006000+0x540) */ |
| 2058 | #define RC_M08_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| 2059 | /* RC_M09_SRCLKEN_CFG (0x10006000+0x544) */ |
| 2060 | #define RC_M09_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| 2061 | /* RC_M10_SRCLKEN_CFG (0x10006000+0x548) */ |
| 2062 | #define RC_M10_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| 2063 | /* RC_M11_SRCLKEN_CFG (0x10006000+0x54C) */ |
| 2064 | #define RC_M11_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| 2065 | /* RC_M12_SRCLKEN_CFG (0x10006000+0x550) */ |
| 2066 | #define RC_M12_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ |
| 2067 | /* RC_SRCLKEN_SW_CON_CFG (0x10006000+0x554) */ |
| 2068 | #define RC_SRCLKEN_SW_CON_CFG_LSB (1U << 0) /* 32b */ |
| 2069 | /* RC_CENTRAL_CFG4 (0x10006000+0x558) */ |
| 2070 | #define RC_CENTRAL_CFG4_LSB (1U << 0) /* 32b */ |
| 2071 | /* RC_PROTOCOL_CHK_CFG (0x10006000+0x560) */ |
| 2072 | #define RC_PROTOCOL_CHK_CFG_LSB (1U << 0) /* 32b */ |
| 2073 | /* RC_DEBUG_CFG (0x10006000+0x564) */ |
| 2074 | #define RC_DEBUG_CFG_LSB (1U << 0) /* 32b */ |
| 2075 | /* RC_MISC_0 (0x10006000+0x5B4) */ |
| 2076 | #define SRCCLKENO_LSB (1U << 0) /* 2b */ |
| 2077 | #define PCM_SRCCLKENO_LSB (1U << 3) /* 2b */ |
| 2078 | #define RC_VREQ_LSB (1U << 5) /* 1b */ |
| 2079 | #define RC_SPM_SRCCLKENO_0_ACK_LSB (1U << 6) /* 1b */ |
| 2080 | /* RC_SPM_CTRL (0x10006000+0x448) */ |
| 2081 | #define SPM_AP_26M_RDY_LSB (1U << 0) /* 1b */ |
| 2082 | #define KEEP_RC_SPI_ACTIVE_LSB (1U << 1) /* 1b */ |
| 2083 | #define SPM2RC_DMY_CTRL_LSB (1U << 2) /* 6b */ |
| 2084 | /* SUBSYS_INTF_CFG (0x10006000+0x5BC) */ |
| 2085 | #define SRCLKEN_FPM_MASK_B_LSB (1U << 0) /* 13b */ |
| 2086 | #define SRCLKEN_BBLPM_MASK_B_LSB (1U << 16) /* 13b */ |
| 2087 | /* PCM_WDT_LATCH_25 (0x10006000+0x5C0) */ |
| 2088 | #define PCM_WDT_LATCH_25_LSB (1U << 0) /* 32b */ |
| 2089 | /* PCM_WDT_LATCH_26 (0x10006000+0x5C4) */ |
| 2090 | #define PCM_WDT_LATCH_26_LSB (1U << 0) /* 32b */ |
| 2091 | /* PCM_WDT_LATCH_27 (0x10006000+0x5C8) */ |
| 2092 | #define PCM_WDT_LATCH_27_LSB (1U << 0) /* 32b */ |
| 2093 | /* PCM_WDT_LATCH_28 (0x10006000+0x5CC) */ |
| 2094 | #define PCM_WDT_LATCH_28_LSB (1U << 0) /* 32b */ |
| 2095 | /* PCM_WDT_LATCH_29 (0x10006000+0x5D0) */ |
| 2096 | #define PCM_WDT_LATCH_29_LSB (1U << 0) /* 32b */ |
| 2097 | /* PCM_WDT_LATCH_30 (0x10006000+0x5D4) */ |
| 2098 | #define PCM_WDT_LATCH_30_LSB (1U << 0) /* 32b */ |
| 2099 | /* PCM_WDT_LATCH_31 (0x10006000+0x5D8) */ |
| 2100 | #define PCM_WDT_LATCH_31_LSB (1U << 0) /* 32b */ |
| 2101 | /* PCM_WDT_LATCH_32 (0x10006000+0x5DC) */ |
| 2102 | #define PCM_WDT_LATCH_32_LSB (1U << 0) /* 32b */ |
| 2103 | /* PCM_WDT_LATCH_33 (0x10006000+0x5E0) */ |
| 2104 | #define PCM_WDT_LATCH_33_LSB (1U << 0) /* 32b */ |
| 2105 | /* PCM_WDT_LATCH_34 (0x10006000+0x5E4) */ |
| 2106 | #define PCM_WDT_LATCH_34_LSB (1U << 0) /* 32b */ |
| 2107 | /* PCM_WDT_LATCH_35 (0x10006000+0x5EC) */ |
| 2108 | #define PCM_WDT_LATCH_35_LSB (1U << 0) /* 32b */ |
| 2109 | /* PCM_WDT_LATCH_36 (0x10006000+0x5F0) */ |
| 2110 | #define PCM_WDT_LATCH_36_LSB (1U << 0) /* 32b */ |
| 2111 | /* PCM_WDT_LATCH_37 (0x10006000+0x5F4) */ |
| 2112 | #define PCM_WDT_LATCH_37_LSB (1U << 0) /* 32b */ |
| 2113 | /* PCM_WDT_LATCH_38 (0x10006000+0x5F8) */ |
| 2114 | #define PCM_WDT_LATCH_38_LSB (1U << 0) /* 32b */ |
| 2115 | /* PCM_WDT_LATCH_39 (0x10006000+0x5FC) */ |
| 2116 | #define PCM_WDT_LATCH_39_LSB (1U << 0) /* 32b */ |
| 2117 | /* SPM_SW_FLAG_0 (0x10006000+0x600) */ |
| 2118 | #define SPM_SW_FLAG_LSB (1U << 0) /* 32b */ |
| 2119 | /* SPM_SW_DEBUG_0 (0x10006000+0x604) */ |
| 2120 | #define SPM_SW_DEBUG_0_LSB (1U << 0) /* 32b */ |
| 2121 | /* SPM_SW_FLAG_1 (0x10006000+0x608) */ |
| 2122 | #define SPM_SW_FLAG_1_LSB (1U << 0) /* 32b */ |
| 2123 | /* SPM_SW_DEBUG_1 (0x10006000+0x60C) */ |
| 2124 | #define SPM_SW_DEBUG_1_LSB (1U << 0) /* 32b */ |
| 2125 | /* SPM_SW_RSV_0 (0x10006000+0x610) */ |
| 2126 | #define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */ |
| 2127 | /* SPM_SW_RSV_1 (0x10006000+0x614) */ |
| 2128 | #define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */ |
| 2129 | /* SPM_SW_RSV_2 (0x10006000+0x618) */ |
| 2130 | #define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */ |
| 2131 | /* SPM_SW_RSV_3 (0x10006000+0x61C) */ |
| 2132 | #define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */ |
| 2133 | /* SPM_SW_RSV_4 (0x10006000+0x620) */ |
| 2134 | #define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */ |
| 2135 | /* SPM_SW_RSV_5 (0x10006000+0x624) */ |
| 2136 | #define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */ |
| 2137 | /* SPM_SW_RSV_6 (0x10006000+0x628) */ |
| 2138 | #define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */ |
| 2139 | /* SPM_SW_RSV_7 (0x10006000+0x62C) */ |
| 2140 | #define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */ |
| 2141 | /* SPM_SW_RSV_8 (0x10006000+0x630) */ |
| 2142 | #define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */ |
| 2143 | /* SPM_BK_WAKE_EVENT (0x10006000+0x634) */ |
| 2144 | #define SPM_BK_WAKE_EVENT_LSB (1U << 0) /* 32b */ |
| 2145 | /* SPM_BK_VTCXO_DUR (0x10006000+0x638) */ |
| 2146 | #define SPM_BK_VTCXO_DUR_LSB (1U << 0) /* 32b */ |
| 2147 | /* SPM_BK_WAKE_MISC (0x10006000+0x63C) */ |
| 2148 | #define SPM_BK_WAKE_MISC_LSB (1U << 0) /* 32b */ |
| 2149 | /* SPM_BK_PCM_TIMER (0x10006000+0x640) */ |
| 2150 | #define SPM_BK_PCM_TIMER_LSB (1U << 0) /* 32b */ |
| 2151 | /* SPM_RSV_CON_0 (0x10006000+0x650) */ |
| 2152 | #define SPM_RSV_CON_0_LSB (1U << 0) /* 32b */ |
| 2153 | /* SPM_RSV_CON_1 (0x10006000+0x654) */ |
| 2154 | #define SPM_RSV_CON_1_LSB (1U << 0) /* 32b */ |
| 2155 | /* SPM_RSV_STA_0 (0x10006000+0x658) */ |
| 2156 | #define SPM_RSV_STA_0_LSB (1U << 0) /* 32b */ |
| 2157 | /* SPM_RSV_STA_1 (0x10006000+0x65C) */ |
| 2158 | #define SPM_RSV_STA_1_LSB (1U << 0) /* 32b */ |
| 2159 | /* SPM_SPARE_CON (0x10006000+0x660) */ |
| 2160 | #define SPM_SPARE_CON_LSB (1U << 0) /* 32b */ |
| 2161 | /* SPM_SPARE_CON_SET (0x10006000+0x664) */ |
| 2162 | #define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */ |
| 2163 | /* SPM_SPARE_CON_CLR (0x10006000+0x668) */ |
| 2164 | #define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ |
| 2165 | /* SPM_CROSS_WAKE_M00_REQ (0x10006000+0x66C) */ |
| 2166 | #define SPM_CROSS_WAKE_M00_REQ_LSB (1U << 0) /* 4b */ |
| 2167 | #define SPM_CROSS_WAKE_M00_CHK_LSB (1U << 4) /* 4b */ |
| 2168 | /* SPM_CROSS_WAKE_M01_REQ (0x10006000+0x670) */ |
| 2169 | #define SPM_CROSS_WAKE_M01_REQ_LSB (1U << 0) /* 4b */ |
| 2170 | #define SPM_CROSS_WAKE_M01_CHK_LSB (1U << 4) /* 4b */ |
| 2171 | /* SPM_CROSS_WAKE_M02_REQ (0x10006000+0x674) */ |
| 2172 | #define SPM_CROSS_WAKE_M02_REQ_LSB (1U << 0) /* 4b */ |
| 2173 | #define SPM_CROSS_WAKE_M02_CHK_LSB (1U << 4) /* 4b */ |
| 2174 | /* SPM_CROSS_WAKE_M03_REQ (0x10006000+0x678) */ |
| 2175 | #define SPM_CROSS_WAKE_M03_REQ_LSB (1U << 0) /* 4b */ |
| 2176 | #define SPM_CROSS_WAKE_M03_CHK_LSB (1U << 4) /* 4b */ |
| 2177 | /* SCP_VCORE_LEVEL (0x10006000+0x67C) */ |
| 2178 | #define SCP_VCORE_LEVEL_LSB (1U << 0) /* 16b */ |
| 2179 | /* SC_MM_CK_SEL_CON (0x10006000+0x680) */ |
| 2180 | #define SC_MM_CK_SEL_LSB (1U << 0) /* 4b */ |
| 2181 | #define SC_MM_CK_SEL_EN_LSB (1U << 4) /* 1b */ |
| 2182 | /* SPARE_ACK_MASK (0x10006000+0x684) */ |
| 2183 | #define SPARE_ACK_MASK_B_LSB (1U << 0) /* 32b */ |
| 2184 | /* SPM_DV_CON_0 (0x10006000+0x68C) */ |
| 2185 | #define SPM_DV_CON_0_LSB (1U << 0) /* 32b */ |
| 2186 | /* SPM_DV_CON_1 (0x10006000+0x690) */ |
| 2187 | #define SPM_DV_CON_1_LSB (1U << 0) /* 32b */ |
| 2188 | /* SPM_DV_STA (0x10006000+0x694) */ |
| 2189 | #define SPM_DV_STA_LSB (1U << 0) /* 32b */ |
| 2190 | /* CONN_XOWCN_DEBUG_EN (0x10006000+0x698) */ |
| 2191 | #define CONN_XOWCN_DEBUG_EN_LSB (1U << 0) /* 1b */ |
| 2192 | /* SPM_SEMA_M0 (0x10006000+0x69C) */ |
| 2193 | #define SPM_SEMA_M0_LSB (1U << 0) /* 8b */ |
| 2194 | /* SPM_SEMA_M1 (0x10006000+0x6A0) */ |
| 2195 | #define SPM_SEMA_M1_LSB (1U << 0) /* 8b */ |
| 2196 | /* SPM_SEMA_M2 (0x10006000+0x6A4) */ |
| 2197 | #define SPM_SEMA_M2_LSB (1U << 0) /* 8b */ |
| 2198 | /* SPM_SEMA_M3 (0x10006000+0x6A8) */ |
| 2199 | #define SPM_SEMA_M3_LSB (1U << 0) /* 8b */ |
| 2200 | /* SPM_SEMA_M4 (0x10006000+0x6AC) */ |
| 2201 | #define SPM_SEMA_M4_LSB (1U << 0) /* 8b */ |
| 2202 | /* SPM_SEMA_M5 (0x10006000+0x6B0) */ |
| 2203 | #define SPM_SEMA_M5_LSB (1U << 0) /* 8b */ |
| 2204 | /* SPM_SEMA_M6 (0x10006000+0x6B4) */ |
| 2205 | #define SPM_SEMA_M6_LSB (1U << 0) /* 8b */ |
| 2206 | /* SPM_SEMA_M7 (0x10006000+0x6B8) */ |
| 2207 | #define SPM_SEMA_M7_LSB (1U << 0) /* 8b */ |
| 2208 | /* SPM2ADSP_MAILBOX (0x10006000+0x6BC) */ |
| 2209 | #define SPM2ADSP_MAILBOX_LSB (1U << 0) /* 32b */ |
| 2210 | /* ADSP2SPM_MAILBOX (0x10006000+0x6C0) */ |
| 2211 | #define ADSP2SPM_MAILBOX_LSB (1U << 0) /* 32b */ |
| 2212 | /* SPM_ADSP_IRQ (0x10006000+0x6C4) */ |
| 2213 | #define SC_SPM2ADSP_WAKEUP_LSB (1U << 0) /* 1b */ |
| 2214 | #define SPM_ADSP_IRQ_SC_ADSP2SPM_WAKEUP_LSB (1U << 4) /* 1b */ |
| 2215 | /* SPM_MD32_IRQ (0x10006000+0x6C8) */ |
| 2216 | #define SC_SPM2SSPM_WAKEUP_LSB (1U << 0) /* 4b */ |
| 2217 | #define SPM_MD32_IRQ_SC_SSPM2SPM_WAKEUP_LSB (1U << 4) /* 4b */ |
| 2218 | /* SPM2PMCU_MAILBOX_0 (0x10006000+0x6CC) */ |
| 2219 | #define SPM2PMCU_MAILBOX_0_LSB (1U << 0) /* 32b */ |
| 2220 | /* SPM2PMCU_MAILBOX_1 (0x10006000+0x6D0) */ |
| 2221 | #define SPM2PMCU_MAILBOX_1_LSB (1U << 0) /* 32b */ |
| 2222 | /* SPM2PMCU_MAILBOX_2 (0x10006000+0x6D4) */ |
| 2223 | #define SPM2PMCU_MAILBOX_2_LSB (1U << 0) /* 32b */ |
| 2224 | /* SPM2PMCU_MAILBOX_3 (0x10006000+0x6D8) */ |
| 2225 | #define SPM2PMCU_MAILBOX_3_LSB (1U << 0) /* 32b */ |
| 2226 | /* PMCU2SPM_MAILBOX_0 (0x10006000+0x6DC) */ |
| 2227 | #define PMCU2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ |
| 2228 | /* PMCU2SPM_MAILBOX_1 (0x10006000+0x6E0) */ |
| 2229 | #define PMCU2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ |
| 2230 | /* PMCU2SPM_MAILBOX_2 (0x10006000+0x6E4) */ |
| 2231 | #define PMCU2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ |
| 2232 | /* PMCU2SPM_MAILBOX_3 (0x10006000+0x6E8) */ |
| 2233 | #define PMCU2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ |
| 2234 | /* UFS_PSRI_SW (0x10006000+0x6EC) */ |
| 2235 | #define UFS_PSRI_SW_LSB (1U << 0) /* 1b */ |
| 2236 | /* UFS_PSRI_SW_SET (0x10006000+0x6F0) */ |
| 2237 | #define UFS_PSRI_SW_SET_LSB (1U << 0) /* 1b */ |
| 2238 | /* UFS_PSRI_SW_CLR (0x10006000+0x6F4) */ |
| 2239 | #define UFS_PSRI_SW_CLR_LSB (1U << 0) /* 1b */ |
| 2240 | /* SPM_AP_SEMA (0x10006000+0x6F8) */ |
| 2241 | #define SPM_AP_SEMA_LSB (1U << 0) /* 1b */ |
| 2242 | /* SPM_SPM_SEMA (0x10006000+0x6FC) */ |
| 2243 | #define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */ |
| 2244 | /* SPM_DVFS_CON (0x10006000+0x700) */ |
| 2245 | #define SPM_DVFS_CON_LSB (1U << 0) /* 32b */ |
| 2246 | /* SPM_DVFS_CON_STA (0x10006000+0x704) */ |
| 2247 | #define SPM_DVFS_CON_STA_LSB (1U << 0) /* 32b */ |
| 2248 | /* SPM_PMIC_SPMI_CON (0x10006000+0x708) */ |
| 2249 | #define SPM_PMIC_SPMI_CMD_LSB (1U << 0) /* 2b */ |
| 2250 | #define SPM_PMIC_SPMI_SLAVEID_LSB (1U << 2) /* 4b */ |
| 2251 | #define SPM_PMIC_SPMI_PMIFID_LSB (1U << 6) /* 1b */ |
| 2252 | #define SPM_PMIC_SPMI_DBCNT_LSB (1U << 7) /* 1b */ |
| 2253 | /* SPM_DVFS_CMD0 (0x10006000+0x710) */ |
| 2254 | #define SPM_DVFS_CMD0_LSB (1U << 0) /* 32b */ |
| 2255 | /* SPM_DVFS_CMD1 (0x10006000+0x714) */ |
| 2256 | #define SPM_DVFS_CMD1_LSB (1U << 0) /* 32b */ |
| 2257 | /* SPM_DVFS_CMD2 (0x10006000+0x718) */ |
| 2258 | #define SPM_DVFS_CMD2_LSB (1U << 0) /* 32b */ |
| 2259 | /* SPM_DVFS_CMD3 (0x10006000+0x71C) */ |
| 2260 | #define SPM_DVFS_CMD3_LSB (1U << 0) /* 32b */ |
| 2261 | /* SPM_DVFS_CMD4 (0x10006000+0x720) */ |
| 2262 | #define SPM_DVFS_CMD4_LSB (1U << 0) /* 32b */ |
| 2263 | /* SPM_DVFS_CMD5 (0x10006000+0x724) */ |
| 2264 | #define SPM_DVFS_CMD5_LSB (1U << 0) /* 32b */ |
| 2265 | /* SPM_DVFS_CMD6 (0x10006000+0x728) */ |
| 2266 | #define SPM_DVFS_CMD6_LSB (1U << 0) /* 32b */ |
| 2267 | /* SPM_DVFS_CMD7 (0x10006000+0x72C) */ |
| 2268 | #define SPM_DVFS_CMD7_LSB (1U << 0) /* 32b */ |
| 2269 | /* SPM_DVFS_CMD8 (0x10006000+0x730) */ |
| 2270 | #define SPM_DVFS_CMD8_LSB (1U << 0) /* 32b */ |
| 2271 | /* SPM_DVFS_CMD9 (0x10006000+0x734) */ |
| 2272 | #define SPM_DVFS_CMD9_LSB (1U << 0) /* 32b */ |
| 2273 | /* SPM_DVFS_CMD10 (0x10006000+0x738) */ |
| 2274 | #define SPM_DVFS_CMD10_LSB (1U << 0) /* 32b */ |
| 2275 | /* SPM_DVFS_CMD11 (0x10006000+0x73C) */ |
| 2276 | #define SPM_DVFS_CMD11_LSB (1U << 0) /* 32b */ |
| 2277 | /* SPM_DVFS_CMD12 (0x10006000+0x740) */ |
| 2278 | #define SPM_DVFS_CMD12_LSB (1U << 0) /* 32b */ |
| 2279 | /* SPM_DVFS_CMD13 (0x10006000+0x744) */ |
| 2280 | #define SPM_DVFS_CMD13_LSB (1U << 0) /* 32b */ |
| 2281 | /* SPM_DVFS_CMD14 (0x10006000+0x748) */ |
| 2282 | #define SPM_DVFS_CMD14_LSB (1U << 0) /* 32b */ |
| 2283 | /* SPM_DVFS_CMD15 (0x10006000+0x74C) */ |
| 2284 | #define SPM_DVFS_CMD15_LSB (1U << 0) /* 32b */ |
| 2285 | /* SPM_DVFS_CMD16 (0x10006000+0x750) */ |
| 2286 | #define SPM_DVFS_CMD16_LSB (1U << 0) /* 32b */ |
| 2287 | /* SPM_DVFS_CMD17 (0x10006000+0x754) */ |
| 2288 | #define SPM_DVFS_CMD17_LSB (1U << 0) /* 32b */ |
| 2289 | /* SPM_DVFS_CMD18 (0x10006000+0x758) */ |
| 2290 | #define SPM_DVFS_CMD18_LSB (1U << 0) /* 32b */ |
| 2291 | /* SPM_DVFS_CMD19 (0x10006000+0x75C) */ |
| 2292 | #define SPM_DVFS_CMD19_LSB (1U << 0) /* 32b */ |
| 2293 | /* SPM_DVFS_CMD20 (0x10006000+0x760) */ |
| 2294 | #define SPM_DVFS_CMD20_LSB (1U << 0) /* 32b */ |
| 2295 | /* SPM_DVFS_CMD21 (0x10006000+0x764) */ |
| 2296 | #define SPM_DVFS_CMD21_LSB (1U << 0) /* 32b */ |
| 2297 | /* SPM_DVFS_CMD22 (0x10006000+0x768) */ |
| 2298 | #define SPM_DVFS_CMD22_LSB (1U << 0) /* 32b */ |
| 2299 | /* SPM_DVFS_CMD23 (0x10006000+0x76C) */ |
| 2300 | #define SPM_DVFS_CMD23_LSB (1U << 0) /* 32b */ |
| 2301 | /* SYS_TIMER_VALUE_L (0x10006000+0x770) */ |
| 2302 | #define SYS_TIMER_VALUE_L_LSB (1U << 0) /* 32b */ |
| 2303 | /* SYS_TIMER_VALUE_H (0x10006000+0x774) */ |
| 2304 | #define SYS_TIMER_VALUE_H_LSB (1U << 0) /* 32b */ |
| 2305 | /* SYS_TIMER_START_L (0x10006000+0x778) */ |
| 2306 | #define SYS_TIMER_START_L_LSB (1U << 0) /* 32b */ |
| 2307 | /* SYS_TIMER_START_H (0x10006000+0x77C) */ |
| 2308 | #define SYS_TIMER_START_H_LSB (1U << 0) /* 32b */ |
| 2309 | /* SYS_TIMER_LATCH_L_00 (0x10006000+0x780) */ |
| 2310 | #define SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */ |
| 2311 | /* SYS_TIMER_LATCH_H_00 (0x10006000+0x784) */ |
| 2312 | #define SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */ |
| 2313 | /* SYS_TIMER_LATCH_L_01 (0x10006000+0x788) */ |
| 2314 | #define SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */ |
| 2315 | /* SYS_TIMER_LATCH_H_01 (0x10006000+0x78C) */ |
| 2316 | #define SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */ |
| 2317 | /* SYS_TIMER_LATCH_L_02 (0x10006000+0x790) */ |
| 2318 | #define SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */ |
| 2319 | /* SYS_TIMER_LATCH_H_02 (0x10006000+0x794) */ |
| 2320 | #define SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */ |
| 2321 | /* SYS_TIMER_LATCH_L_03 (0x10006000+0x798) */ |
| 2322 | #define SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */ |
| 2323 | /* SYS_TIMER_LATCH_H_03 (0x10006000+0x79C) */ |
| 2324 | #define SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */ |
| 2325 | /* SYS_TIMER_LATCH_L_04 (0x10006000+0x7A0) */ |
| 2326 | #define SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */ |
| 2327 | /* SYS_TIMER_LATCH_H_04 (0x10006000+0x7A4) */ |
| 2328 | #define SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */ |
| 2329 | /* SYS_TIMER_LATCH_L_05 (0x10006000+0x7A8) */ |
| 2330 | #define SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */ |
| 2331 | /* SYS_TIMER_LATCH_H_05 (0x10006000+0x7AC) */ |
| 2332 | #define SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */ |
| 2333 | /* SYS_TIMER_LATCH_L_06 (0x10006000+0x7B0) */ |
| 2334 | #define SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */ |
| 2335 | /* SYS_TIMER_LATCH_H_06 (0x10006000+0x7B4) */ |
| 2336 | #define SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */ |
| 2337 | /* SYS_TIMER_LATCH_L_07 (0x10006000+0x7B8) */ |
| 2338 | #define SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */ |
| 2339 | /* SYS_TIMER_LATCH_H_07 (0x10006000+0x7BC) */ |
| 2340 | #define SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */ |
| 2341 | /* SYS_TIMER_LATCH_L_08 (0x10006000+0x7C0) */ |
| 2342 | #define SYS_TIMER_LATCH_L_08_LSB (1U << 0) /* 32b */ |
| 2343 | /* SYS_TIMER_LATCH_H_08 (0x10006000+0x7C4) */ |
| 2344 | #define SYS_TIMER_LATCH_H_08_LSB (1U << 0) /* 32b */ |
| 2345 | /* SYS_TIMER_LATCH_L_09 (0x10006000+0x7C8) */ |
| 2346 | #define SYS_TIMER_LATCH_L_09_LSB (1U << 0) /* 32b */ |
| 2347 | /* SYS_TIMER_LATCH_H_09 (0x10006000+0x7CC) */ |
| 2348 | #define SYS_TIMER_LATCH_H_09_LSB (1U << 0) /* 32b */ |
| 2349 | /* SYS_TIMER_LATCH_L_10 (0x10006000+0x7D0) */ |
| 2350 | #define SYS_TIMER_LATCH_L_10_LSB (1U << 0) /* 32b */ |
| 2351 | /* SYS_TIMER_LATCH_H_10 (0x10006000+0x7D4) */ |
| 2352 | #define SYS_TIMER_LATCH_H_10_LSB (1U << 0) /* 32b */ |
| 2353 | /* SYS_TIMER_LATCH_L_11 (0x10006000+0x7D8) */ |
| 2354 | #define SYS_TIMER_LATCH_L_11_LSB (1U << 0) /* 32b */ |
| 2355 | /* SYS_TIMER_LATCH_H_11 (0x10006000+0x7DC) */ |
| 2356 | #define SYS_TIMER_LATCH_H_11_LSB (1U << 0) /* 32b */ |
| 2357 | /* SYS_TIMER_LATCH_L_12 (0x10006000+0x7E0) */ |
| 2358 | #define SYS_TIMER_LATCH_L_12_LSB (1U << 0) /* 32b */ |
| 2359 | /* SYS_TIMER_LATCH_H_12 (0x10006000+0x7E4) */ |
| 2360 | #define SYS_TIMER_LATCH_H_12_LSB (1U << 0) /* 32b */ |
| 2361 | /* SYS_TIMER_LATCH_L_13 (0x10006000+0x7E8) */ |
| 2362 | #define SYS_TIMER_LATCH_L_13_LSB (1U << 0) /* 32b */ |
| 2363 | /* SYS_TIMER_LATCH_H_13 (0x10006000+0x7EC) */ |
| 2364 | #define SYS_TIMER_LATCH_H_13_LSB (1U << 0) /* 32b */ |
| 2365 | /* SYS_TIMER_LATCH_L_14 (0x10006000+0x7F0) */ |
| 2366 | #define SYS_TIMER_LATCH_L_14_LSB (1U << 0) /* 32b */ |
| 2367 | /* SYS_TIMER_LATCH_H_14 (0x10006000+0x7F4) */ |
| 2368 | #define SYS_TIMER_LATCH_H_14_LSB (1U << 0) /* 32b */ |
| 2369 | /* SYS_TIMER_LATCH_L_15 (0x10006000+0x7F8) */ |
| 2370 | #define SYS_TIMER_LATCH_L_15_LSB (1U << 0) /* 32b */ |
| 2371 | /* SYS_TIMER_LATCH_H_15 (0x10006000+0x7FC) */ |
| 2372 | #define SYS_TIMER_LATCH_H_15_LSB (1U << 0) /* 32b */ |
| 2373 | /* PCM_WDT_LATCH_0 (0x10006000+0x800) */ |
| 2374 | #define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */ |
| 2375 | /* PCM_WDT_LATCH_1 (0x10006000+0x804) */ |
| 2376 | #define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */ |
| 2377 | /* PCM_WDT_LATCH_2 (0x10006000+0x808) */ |
| 2378 | #define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */ |
| 2379 | /* PCM_WDT_LATCH_3 (0x10006000+0x80C) */ |
| 2380 | #define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */ |
| 2381 | /* PCM_WDT_LATCH_4 (0x10006000+0x810) */ |
| 2382 | #define PCM_WDT_LATCH_4_LSB (1U << 0) /* 32b */ |
| 2383 | /* PCM_WDT_LATCH_5 (0x10006000+0x814) */ |
| 2384 | #define PCM_WDT_LATCH_5_LSB (1U << 0) /* 32b */ |
| 2385 | /* PCM_WDT_LATCH_6 (0x10006000+0x818) */ |
| 2386 | #define PCM_WDT_LATCH_6_LSB (1U << 0) /* 32b */ |
| 2387 | /* PCM_WDT_LATCH_7 (0x10006000+0x81C) */ |
| 2388 | #define PCM_WDT_LATCH_7_LSB (1U << 0) /* 32b */ |
| 2389 | /* PCM_WDT_LATCH_8 (0x10006000+0x820) */ |
| 2390 | #define PCM_WDT_LATCH_8_LSB (1U << 0) /* 32b */ |
| 2391 | /* PCM_WDT_LATCH_9 (0x10006000+0x824) */ |
| 2392 | #define PCM_WDT_LATCH_9_LSB (1U << 0) /* 32b */ |
| 2393 | /* PCM_WDT_LATCH_10 (0x10006000+0x828) */ |
| 2394 | #define PCM_WDT_LATCH_10_LSB (1U << 0) /* 32b */ |
| 2395 | /* PCM_WDT_LATCH_11 (0x10006000+0x82C) */ |
| 2396 | #define PCM_WDT_LATCH_11_LSB (1U << 0) /* 32b */ |
| 2397 | /* PCM_WDT_LATCH_12 (0x10006000+0x830) */ |
| 2398 | #define PCM_WDT_LATCH_12_LSB (1U << 0) /* 32b */ |
| 2399 | /* PCM_WDT_LATCH_13 (0x10006000+0x834) */ |
| 2400 | #define PCM_WDT_LATCH_13_LSB (1U << 0) /* 32b */ |
| 2401 | /* PCM_WDT_LATCH_14 (0x10006000+0x838) */ |
| 2402 | #define PCM_WDT_LATCH_14_LSB (1U << 0) /* 32b */ |
| 2403 | /* PCM_WDT_LATCH_15 (0x10006000+0x83C) */ |
| 2404 | #define PCM_WDT_LATCH_15_LSB (1U << 0) /* 32b */ |
| 2405 | /* PCM_WDT_LATCH_16 (0x10006000+0x840) */ |
| 2406 | #define PCM_WDT_LATCH_16_LSB (1U << 0) /* 32b */ |
| 2407 | /* PCM_WDT_LATCH_17 (0x10006000+0x844) */ |
| 2408 | #define PCM_WDT_LATCH_17_LSB (1U << 0) /* 32b */ |
| 2409 | /* PCM_WDT_LATCH_18 (0x10006000+0x848) */ |
| 2410 | #define PCM_WDT_LATCH_18_LSB (1U << 0) /* 32b */ |
| 2411 | /* PCM_WDT_LATCH_SPARE_0 (0x10006000+0x84C) */ |
| 2412 | #define PCM_WDT_LATCH_SPARE_0_LSB (1U << 0) /* 32b */ |
| 2413 | /* PCM_WDT_LATCH_SPARE_1 (0x10006000+0x850) */ |
| 2414 | #define PCM_WDT_LATCH_SPARE_1_LSB (1U << 0) /* 32b */ |
| 2415 | /* PCM_WDT_LATCH_SPARE_2 (0x10006000+0x854) */ |
| 2416 | #define PCM_WDT_LATCH_SPARE_2_LSB (1U << 0) /* 32b */ |
| 2417 | /* PCM_WDT_LATCH_CONN_0 (0x10006000+0x870) */ |
| 2418 | #define PCM_WDT_LATCH_CONN_0_LSB (1U << 0) /* 32b */ |
| 2419 | /* PCM_WDT_LATCH_CONN_1 (0x10006000+0x874) */ |
| 2420 | #define PCM_WDT_LATCH_CONN_1_LSB (1U << 0) /* 32b */ |
| 2421 | /* PCM_WDT_LATCH_CONN_2 (0x10006000+0x878) */ |
| 2422 | #define PCM_WDT_LATCH_CONN_2_LSB (1U << 0) /* 32b */ |
| 2423 | /* DRAMC_GATING_ERR_LATCH_CH0_0 (0x10006000+0x8A0) */ |
| 2424 | #define DRAMC_GATING_ERR_LATCH_CH0_0_LSB (1U << 0) /* 32b */ |
| 2425 | /* DRAMC_GATING_ERR_LATCH_CH0_1 (0x10006000+0x8A4) */ |
| 2426 | #define DRAMC_GATING_ERR_LATCH_CH0_1_LSB (1U << 0) /* 32b */ |
| 2427 | /* DRAMC_GATING_ERR_LATCH_CH0_2 (0x10006000+0x8A8) */ |
| 2428 | #define DRAMC_GATING_ERR_LATCH_CH0_2_LSB (1U << 0) /* 32b */ |
| 2429 | /* DRAMC_GATING_ERR_LATCH_CH0_3 (0x10006000+0x8AC) */ |
| 2430 | #define DRAMC_GATING_ERR_LATCH_CH0_3_LSB (1U << 0) /* 32b */ |
| 2431 | /* DRAMC_GATING_ERR_LATCH_CH0_4 (0x10006000+0x8B0) */ |
| 2432 | #define DRAMC_GATING_ERR_LATCH_CH0_4_LSB (1U << 0) /* 32b */ |
| 2433 | /* DRAMC_GATING_ERR_LATCH_CH0_5 (0x10006000+0x8B4) */ |
| 2434 | #define DRAMC_GATING_ERR_LATCH_CH0_5_LSB (1U << 0) /* 32b */ |
| 2435 | /* DRAMC_GATING_ERR_LATCH_CH0_6 (0x10006000+0x8B8) */ |
| 2436 | #define DRAMC_GATING_ERR_LATCH_CH0_6_LSB (1U << 0) /* 32b */ |
| 2437 | /* DRAMC_GATING_ERR_LATCH_SPARE_0 (0x10006000+0x8F4) */ |
| 2438 | #define DRAMC_GATING_ERR_LATCH_SPARE_0_LSB (1U << 0) /* 32b */ |
| 2439 | /* SPM_ACK_CHK_CON_0 (0x10006000+0x900) */ |
| 2440 | #define SPM_ACK_CHK_SW_EN_0_LSB (1U << 0) /* 1b */ |
| 2441 | #define SPM_ACK_CHK_CLR_ALL_0_LSB (1U << 1) /* 1b */ |
| 2442 | #define SPM_ACK_CHK_CLR_TIMER_0_LSB (1U << 2) /* 1b */ |
| 2443 | #define SPM_ACK_CHK_CLR_IRQ_0_LSB (1U << 3) /* 1b */ |
| 2444 | #define SPM_ACK_CHK_STA_EN_0_LSB (1U << 4) /* 1b */ |
| 2445 | #define SPM_ACK_CHK_WAKEUP_EN_0_LSB (1U << 5) /* 1b */ |
| 2446 | #define SPM_ACK_CHK_WDT_EN_0_LSB (1U << 6) /* 1b */ |
| 2447 | #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_0_LSB (1U << 7) /* 1b */ |
| 2448 | #define SPM_ACK_CHK_HW_EN_0_LSB (1U << 8) /* 1b */ |
| 2449 | #define SPM_ACK_CHK_HW_MODE_0_LSB (1U << 9) /* 3b */ |
| 2450 | #define SPM_ACK_CHK_FAIL_0_LSB (1U << 15) /* 1b */ |
| 2451 | /* SPM_ACK_CHK_PC_0 (0x10006000+0x904) */ |
| 2452 | #define SPM_ACK_CHK_HW_TRIG_PC_VAL_0_LSB (1U << 0) /* 16b */ |
| 2453 | #define SPM_ACK_CHK_HW_TARG_PC_VAL_0_LSB (1U << 16) /* 16b */ |
| 2454 | /* SPM_ACK_CHK_SEL_0 (0x10006000+0x908) */ |
| 2455 | #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_0_LSB (1U << 0) /* 5b */ |
| 2456 | #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_0_LSB (1U << 5) /* 3b */ |
| 2457 | #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_0_LSB (1U << 16) /* 5b */ |
| 2458 | #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_0_LSB (1U << 21) /* 3b */ |
| 2459 | /* SPM_ACK_CHK_TIMER_0 (0x10006000+0x90C) */ |
| 2460 | #define SPM_ACK_CHK_TIMER_VAL_0_LSB (1U << 0) /* 16b */ |
| 2461 | #define SPM_ACK_CHK_TIMER_0_LSB (1U << 16) /* 16b */ |
| 2462 | /* SPM_ACK_CHK_STA_0 (0x10006000+0x910) */ |
| 2463 | #define SPM_ACK_CHK_STA_0_LSB (1U << 0) /* 32b */ |
| 2464 | /* SPM_ACK_CHK_SWINT_0 (0x10006000+0x914) */ |
| 2465 | #define SPM_ACK_CHK_SWINT_EN_0_LSB (1U << 0) /* 32b */ |
| 2466 | /* SPM_ACK_CHK_CON_1 (0x10006000+0x920) */ |
| 2467 | #define SPM_ACK_CHK_SW_EN_1_LSB (1U << 0) /* 1b */ |
| 2468 | #define SPM_ACK_CHK_CLR_ALL_1_LSB (1U << 1) /* 1b */ |
| 2469 | #define SPM_ACK_CHK_CLR_TIMER_1_LSB (1U << 2) /* 1b */ |
| 2470 | #define SPM_ACK_CHK_CLR_IRQ_1_LSB (1U << 3) /* 1b */ |
| 2471 | #define SPM_ACK_CHK_STA_EN_1_LSB (1U << 4) /* 1b */ |
| 2472 | #define SPM_ACK_CHK_WAKEUP_EN_1_LSB (1U << 5) /* 1b */ |
| 2473 | #define SPM_ACK_CHK_WDT_EN_1_LSB (1U << 6) /* 1b */ |
| 2474 | #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_1_LSB (1U << 7) /* 1b */ |
| 2475 | #define SPM_ACK_CHK_HW_EN_1_LSB (1U << 8) /* 1b */ |
| 2476 | #define SPM_ACK_CHK_HW_MODE_1_LSB (1U << 9) /* 3b */ |
| 2477 | #define SPM_ACK_CHK_FAIL_1_LSB (1U << 15) /* 1b */ |
| 2478 | /* SPM_ACK_CHK_PC_1 (0x10006000+0x924) */ |
| 2479 | #define SPM_ACK_CHK_HW_TRIG_PC_VAL_1_LSB (1U << 0) /* 16b */ |
| 2480 | #define SPM_ACK_CHK_HW_TARG_PC_VAL_1_LSB (1U << 16) /* 16b */ |
| 2481 | /* SPM_ACK_CHK_SEL_1 (0x10006000+0x928) */ |
| 2482 | #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_1_LSB (1U << 0) /* 5b */ |
| 2483 | #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_1_LSB (1U << 5) /* 3b */ |
| 2484 | #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_1_LSB (1U << 16) /* 5b */ |
| 2485 | #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_1_LSB (1U << 21) /* 3b */ |
| 2486 | /* SPM_ACK_CHK_TIMER_1 (0x10006000+0x92C) */ |
| 2487 | #define SPM_ACK_CHK_TIMER_VAL_1_LSB (1U << 0) /* 16b */ |
| 2488 | #define SPM_ACK_CHK_TIMER_1_LSB (1U << 16) /* 16b */ |
| 2489 | /* SPM_ACK_CHK_STA_1 (0x10006000+0x930) */ |
| 2490 | #define SPM_ACK_CHK_STA_1_LSB (1U << 0) /* 32b */ |
| 2491 | /* SPM_ACK_CHK_SWINT_1 (0x10006000+0x934) */ |
| 2492 | #define SPM_ACK_CHK_SWINT_EN_1_LSB (1U << 0) /* 32b */ |
| 2493 | /* SPM_ACK_CHK_CON_2 (0x10006000+0x940) */ |
| 2494 | #define SPM_ACK_CHK_SW_EN_2_LSB (1U << 0) /* 1b */ |
| 2495 | #define SPM_ACK_CHK_CLR_ALL_2_LSB (1U << 1) /* 1b */ |
| 2496 | #define SPM_ACK_CHK_CLR_TIMER_2_LSB (1U << 2) /* 1b */ |
| 2497 | #define SPM_ACK_CHK_CLR_IRQ_2_LSB (1U << 3) /* 1b */ |
| 2498 | #define SPM_ACK_CHK_STA_EN_2_LSB (1U << 4) /* 1b */ |
| 2499 | #define SPM_ACK_CHK_WAKEUP_EN_2_LSB (1U << 5) /* 1b */ |
| 2500 | #define SPM_ACK_CHK_WDT_EN_2_LSB (1U << 6) /* 1b */ |
| 2501 | #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_2_LSB (1U << 7) /* 1b */ |
| 2502 | #define SPM_ACK_CHK_HW_EN_2_LSB (1U << 8) /* 1b */ |
| 2503 | #define SPM_ACK_CHK_HW_MODE_2_LSB (1U << 9) /* 3b */ |
| 2504 | #define SPM_ACK_CHK_FAIL_2_LSB (1U << 15) /* 1b */ |
| 2505 | /* SPM_ACK_CHK_PC_2 (0x10006000+0x944) */ |
| 2506 | #define SPM_ACK_CHK_HW_TRIG_PC_VAL_2_LSB (1U << 0) /* 16b */ |
| 2507 | #define SPM_ACK_CHK_HW_TARG_PC_VAL_2_LSB (1U << 16) /* 16b */ |
| 2508 | /* SPM_ACK_CHK_SEL_2 (0x10006000+0x948) */ |
| 2509 | #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_2_LSB (1U << 0) /* 5b */ |
| 2510 | #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_2_LSB (1U << 5) /* 3b */ |
| 2511 | #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_2_LSB (1U << 16) /* 5b */ |
| 2512 | #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_2_LSB (1U << 21) /* 3b */ |
| 2513 | /* SPM_ACK_CHK_TIMER_2 (0x10006000+0x94C) */ |
| 2514 | #define SPM_ACK_CHK_TIMER_VAL_2_LSB (1U << 0) /* 16b */ |
| 2515 | #define SPM_ACK_CHK_TIMER_2_LSB (1U << 16) /* 16b */ |
| 2516 | /* SPM_ACK_CHK_STA_2 (0x10006000+0x950) */ |
| 2517 | #define SPM_ACK_CHK_STA_2_LSB (1U << 0) /* 32b */ |
| 2518 | /* SPM_ACK_CHK_SWINT_2 (0x10006000+0x954) */ |
| 2519 | #define SPM_ACK_CHK_SWINT_EN_2_LSB (1U << 0) /* 32b */ |
| 2520 | /* SPM_ACK_CHK_CON_3 (0x10006000+0x960) */ |
| 2521 | #define SPM_ACK_CHK_SW_EN_3_LSB (1U << 0) /* 1b */ |
| 2522 | #define SPM_ACK_CHK_CLR_ALL_3_LSB (1U << 1) /* 1b */ |
| 2523 | #define SPM_ACK_CHK_CLR_TIMER_3_LSB (1U << 2) /* 1b */ |
| 2524 | #define SPM_ACK_CHK_CLR_IRQ_3_LSB (1U << 3) /* 1b */ |
| 2525 | #define SPM_ACK_CHK_STA_EN_3_LSB (1U << 4) /* 1b */ |
| 2526 | #define SPM_ACK_CHK_WAKEUP_EN_3_LSB (1U << 5) /* 1b */ |
| 2527 | #define SPM_ACK_CHK_WDT_EN_3_LSB (1U << 6) /* 1b */ |
| 2528 | #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_3_LSB (1U << 7) /* 1b */ |
| 2529 | #define SPM_ACK_CHK_HW_EN_3_LSB (1U << 8) /* 1b */ |
| 2530 | #define SPM_ACK_CHK_HW_MODE_3_LSB (1U << 9) /* 3b */ |
| 2531 | #define SPM_ACK_CHK_FAIL_3_LSB (1U << 15) /* 1b */ |
| 2532 | /* SPM_ACK_CHK_PC_3 (0x10006000+0x964) */ |
| 2533 | #define SPM_ACK_CHK_HW_TRIG_PC_VAL_3_LSB (1U << 0) /* 16b */ |
| 2534 | #define SPM_ACK_CHK_HW_TARG_PC_VAL_3_LSB (1U << 16) /* 16b */ |
| 2535 | /* SPM_ACK_CHK_SEL_3 (0x10006000+0x968) */ |
| 2536 | #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_3_LSB (1U << 0) /* 5b */ |
| 2537 | #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_3_LSB (1U << 5) /* 3b */ |
| 2538 | #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_3_LSB (1U << 16) /* 5b */ |
| 2539 | #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_3_LSB (1U << 21) /* 3b */ |
| 2540 | /* SPM_ACK_CHK_TIMER_3 (0x10006000+0x96C) */ |
| 2541 | #define SPM_ACK_CHK_TIMER_VAL_3_LSB (1U << 0) /* 16b */ |
| 2542 | #define SPM_ACK_CHK_TIMER_3_LSB (1U << 16) /* 16b */ |
| 2543 | /* SPM_ACK_CHK_STA_3 (0x10006000+0x970) */ |
| 2544 | #define SPM_ACK_CHK_STA_3_LSB (1U << 0) /* 32b */ |
| 2545 | /* SPM_ACK_CHK_SWINT_3 (0x10006000+0x974) */ |
| 2546 | #define SPM_ACK_CHK_SWINT_EN_3_LSB (1U << 0) /* 32b */ |
| 2547 | /* SPM_COUNTER_0 (0x10006000+0x978) */ |
| 2548 | #define SPM_COUNTER_VAL_0_LSB (1U << 0) /* 14b */ |
| 2549 | #define SPM_COUNTER_OUT_0_LSB (1U << 14) /* 14b */ |
| 2550 | #define SPM_COUNTER_EN_0_LSB (1U << 28) /* 1b */ |
| 2551 | #define SPM_COUNTER_CLR_0_LSB (1U << 29) /* 1b */ |
| 2552 | #define SPM_COUNTER_TIMEOUT_0_LSB (1U << 30) /* 1b */ |
| 2553 | #define SPM_COUNTER_WAKEUP_EN_0_LSB (1U << 31) /* 1b */ |
| 2554 | /* SPM_COUNTER_1 (0x10006000+0x97C) */ |
| 2555 | #define SPM_COUNTER_VAL_1_LSB (1U << 0) /* 14b */ |
| 2556 | #define SPM_COUNTER_OUT_1_LSB (1U << 14) /* 14b */ |
| 2557 | #define SPM_COUNTER_EN_1_LSB (1U << 28) /* 1b */ |
| 2558 | #define SPM_COUNTER_CLR_1_LSB (1U << 29) /* 1b */ |
| 2559 | #define SPM_COUNTER_TIMEOUT_1_LSB (1U << 30) /* 1b */ |
| 2560 | #define SPM_COUNTER_WAKEUP_EN_1_LSB (1U << 31) /* 1b */ |
| 2561 | /* SPM_COUNTER_2 (0x10006000+0x980) */ |
| 2562 | #define SPM_COUNTER_VAL_2_LSB (1U << 0) /* 14b */ |
| 2563 | #define SPM_COUNTER_OUT_2_LSB (1U << 14) /* 14b */ |
| 2564 | #define SPM_COUNTER_EN_2_LSB (1U << 28) /* 1b */ |
| 2565 | #define SPM_COUNTER_CLR_2_LSB (1U << 29) /* 1b */ |
| 2566 | #define SPM_COUNTER_TIMEOUT_2_LSB (1U << 30) /* 1b */ |
| 2567 | #define SPM_COUNTER_WAKEUP_EN_2_LSB (1U << 31) /* 1b */ |
| 2568 | /* SYS_TIMER_CON (0x10006000+0x98C) */ |
| 2569 | #define SYS_TIMER_START_EN_LSB (1U << 0) /* 1b */ |
| 2570 | #define SYS_TIMER_LATCH_EN_LSB (1U << 1) /* 1b */ |
| 2571 | #define SYS_TIMER_ID_LSB (1U << 8) /* 8b */ |
| 2572 | #define SYS_TIMER_VALID_LSB (1U << 31) /* 1b */ |
| 2573 | /* RC_FSM_STA_0 (0x10006000+0xE00) */ |
| 2574 | #define RC_FSM_STA_0_LSB (1U << 0) /* 32b */ |
| 2575 | /* RC_CMD_STA_0 (0x10006000+0xE04) */ |
| 2576 | #define RC_CMD_STA_0_LSB (1U << 0) /* 32b */ |
| 2577 | /* RC_CMD_STA_1 (0x10006000+0xE08) */ |
| 2578 | #define RC_CMD_STA_1_LSB (1U << 0) /* 32b */ |
| 2579 | /* RC_SPI_STA_0 (0x10006000+0xE0C) */ |
| 2580 | #define RC_SPI_STA_0_LSB (1U << 0) /* 32b */ |
| 2581 | /* RC_PI_PO_STA_0 (0x10006000+0xE10) */ |
| 2582 | #define RC_PI_PO_STA_0_LSB (1U << 0) /* 32b */ |
| 2583 | /* RC_M00_REQ_STA_0 (0x10006000+0xE14) */ |
| 2584 | #define RC_M00_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| 2585 | /* RC_M01_REQ_STA_0 (0x10006000+0xE1C) */ |
| 2586 | #define RC_M01_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| 2587 | /* RC_M02_REQ_STA_0 (0x10006000+0xE20) */ |
| 2588 | #define RC_M02_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| 2589 | /* RC_M03_REQ_STA_0 (0x10006000+0xE24) */ |
| 2590 | #define RC_M03_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| 2591 | /* RC_M04_REQ_STA_0 (0x10006000+0xE28) */ |
| 2592 | #define RC_M04_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| 2593 | /* RC_M05_REQ_STA_0 (0x10006000+0xE2C) */ |
| 2594 | #define RC_M05_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| 2595 | /* RC_M06_REQ_STA_0 (0x10006000+0xE30) */ |
| 2596 | #define RC_M06_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| 2597 | /* RC_M07_REQ_STA_0 (0x10006000+0xE34) */ |
| 2598 | #define RC_M07_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| 2599 | /* RC_M08_REQ_STA_0 (0x10006000+0xE38) */ |
| 2600 | #define RC_M08_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| 2601 | /* RC_M09_REQ_STA_0 (0x10006000+0xE3C) */ |
| 2602 | #define RC_M09_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| 2603 | /* RC_M10_REQ_STA_0 (0x10006000+0xE40) */ |
| 2604 | #define RC_M10_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| 2605 | /* RC_M11_REQ_STA_0 (0x10006000+0xE44) */ |
| 2606 | #define RC_M11_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| 2607 | /* RC_M12_REQ_STA_0 (0x10006000+0xE48) */ |
| 2608 | #define RC_M12_REQ_STA_0_LSB (1U << 0) /* 32b */ |
| 2609 | /* RC_DEBUG_STA_0 (0x10006000+0xE4C) */ |
| 2610 | #define RC_DEBUG_STA_0_LSB (1U << 0) /* 32b */ |
| 2611 | /* RC_DEBUG_TRACE_0_LSB (0x10006000+0xE50) */ |
| 2612 | #define RO_PMRC_TRACE_00_LSB_LSB (1U << 0) /* 32b */ |
| 2613 | /* RC_DEBUG_TRACE_0_MSB (0x10006000+0xE54) */ |
| 2614 | #define RO_PMRC_TRACE_00_MSB_LSB (1U << 0) /* 32b */ |
| 2615 | /* RC_DEBUG_TRACE_1_LSB (0x10006000+0xE5C) */ |
| 2616 | #define RO_PMRC_TRACE_01_LSB_LSB (1U << 0) /* 32b */ |
| 2617 | /* RC_DEBUG_TRACE_1_MSB (0x10006000+0xE60) */ |
| 2618 | #define RO_PMRC_TRACE_01_MSB_LSB (1U << 0) /* 32b */ |
| 2619 | /* RC_DEBUG_TRACE_2_LSB (0x10006000+0xE64) */ |
| 2620 | #define RO_PMRC_TRACE_02_LSB_LSB (1U << 0) /* 32b */ |
| 2621 | /* RC_DEBUG_TRACE_2_MSB (0x10006000+0xE6C) */ |
| 2622 | #define RO_PMRC_TRACE_02_MSB_LSB (1U << 0) /* 32b */ |
| 2623 | /* RC_DEBUG_TRACE_3_LSB (0x10006000+0xE70) */ |
| 2624 | #define RO_PMRC_TRACE_03_LSB_LSB (1U << 0) /* 32b */ |
| 2625 | /* RC_DEBUG_TRACE_3_MSB (0x10006000+0xE74) */ |
| 2626 | #define RO_PMRC_TRACE_03_MSB_LSB (1U << 0) /* 32b */ |
| 2627 | /* RC_DEBUG_TRACE_4_LSB (0x10006000+0xE78) */ |
| 2628 | #define RO_PMRC_TRACE_04_LSB_LSB (1U << 0) /* 32b */ |
| 2629 | /* RC_DEBUG_TRACE_4_MSB (0x10006000+0xE7C) */ |
| 2630 | #define RO_PMRC_TRACE_04_MSB_LSB (1U << 0) /* 32b */ |
| 2631 | /* RC_DEBUG_TRACE_5_LSB (0x10006000+0xE80) */ |
| 2632 | #define RO_PMRC_TRACE_05_LSB_LSB (1U << 0) /* 32b */ |
| 2633 | /* RC_DEBUG_TRACE_5_MSB (0x10006000+0xE84) */ |
| 2634 | #define RO_PMRC_TRACE_05_MSB_LSB (1U << 0) /* 32b */ |
| 2635 | /* RC_DEBUG_TRACE_6_LSB (0x10006000+0xE88) */ |
| 2636 | #define RO_PMRC_TRACE_06_LSB_LSB (1U << 0) /* 32b */ |
| 2637 | /* RC_DEBUG_TRACE_6_MSB (0x10006000+0xE8C) */ |
| 2638 | #define RO_PMRC_TRACE_06_MSB_LSB (1U << 0) /* 32b */ |
| 2639 | /* RC_DEBUG_TRACE_7_LSB (0x10006000+0xE90) */ |
| 2640 | #define RO_PMRC_TRACE_07_LSB_LSB (1U << 0) /* 32b */ |
| 2641 | /* RC_DEBUG_TRACE_7_MSB (0x10006000+0xE94) */ |
| 2642 | #define RO_PMRC_TRACE_07_MSB_LSB (1U << 0) /* 32b */ |
| 2643 | /* RC_SYS_TIMER_LATCH_0_LSB (0x10006000+0xE98) */ |
| 2644 | #define RC_SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */ |
| 2645 | /* RC_SYS_TIMER_LATCH_0_MSB (0x10006000+0xE9C) */ |
| 2646 | #define RC_SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */ |
| 2647 | /* RC_SYS_TIMER_LATCH_1_LSB (0x10006000+0xEA0) */ |
| 2648 | #define RC_SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */ |
| 2649 | /* RC_SYS_TIMER_LATCH_1_MSB (0x10006000+0xEA4) */ |
| 2650 | #define RC_SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */ |
| 2651 | /* RC_SYS_TIMER_LATCH_2_LSB (0x10006000+0xEA8) */ |
| 2652 | #define RC_SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */ |
| 2653 | /* RC_SYS_TIMER_LATCH_2_MSB (0x10006000+0xEAC) */ |
| 2654 | #define RC_SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */ |
| 2655 | /* RC_SYS_TIMER_LATCH_3_LSB (0x10006000+0xEB0) */ |
| 2656 | #define RC_SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */ |
| 2657 | /* RC_SYS_TIMER_LATCH_3_MSB (0x10006000+0xEB4) */ |
| 2658 | #define RC_SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */ |
| 2659 | /* RC_SYS_TIMER_LATCH_4_LSB (0x10006000+0xEB8) */ |
| 2660 | #define RC_SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */ |
| 2661 | /* RC_SYS_TIMER_LATCH_4_MSB (0x10006000+0xEBC) */ |
| 2662 | #define RC_SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */ |
| 2663 | /* RC_SYS_TIMER_LATCH_5_LSB (0x10006000+0xEC0) */ |
| 2664 | #define RC_SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */ |
| 2665 | /* RC_SYS_TIMER_LATCH_5_MSB (0x10006000+0xEC4) */ |
| 2666 | #define RC_SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */ |
| 2667 | /* RC_SYS_TIMER_LATCH_6_LSB (0x10006000+0xEC8) */ |
| 2668 | #define RC_SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */ |
| 2669 | /* RC_SYS_TIMER_LATCH_6_MSB (0x10006000+0xECC) */ |
| 2670 | #define RC_SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */ |
| 2671 | /* RC_SYS_TIMER_LATCH_7_LSB (0x10006000+0xED0) */ |
| 2672 | #define RC_SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */ |
| 2673 | /* RC_SYS_TIMER_LATCH_7_MSB (0x10006000+0xED4) */ |
| 2674 | #define RC_SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */ |
| 2675 | /* PCM_WDT_LATCH_19 (0x10006000+0xED8) */ |
| 2676 | #define PCM_WDT_LATCH_19_LSB (1U << 0) /* 32b */ |
| 2677 | /* PCM_WDT_LATCH_20 (0x10006000+0xEDC) */ |
| 2678 | #define PCM_WDT_LATCH_20_LSB (1U << 0) /* 32b */ |
| 2679 | /* PCM_WDT_LATCH_21 (0x10006000+0xEE0) */ |
| 2680 | #define PCM_WDT_LATCH_21_LSB (1U << 0) /* 32b */ |
| 2681 | /* PCM_WDT_LATCH_22 (0x10006000+0xEE4) */ |
| 2682 | #define PCM_WDT_LATCH_22_LSB (1U << 0) /* 32b */ |
| 2683 | /* PCM_WDT_LATCH_23 (0x10006000+0xEE8) */ |
| 2684 | #define PCM_WDT_LATCH_23_LSB (1U << 0) /* 32b */ |
| 2685 | /* PCM_WDT_LATCH_24 (0x10006000+0xEEC) */ |
| 2686 | #define PCM_WDT_LATCH_24_LSB (1U << 0) /* 32b */ |
| 2687 | /* PMSR_LAST_DAT (0x10006000+0xF00) */ |
| 2688 | #define PMSR_LAST_DAT_LSB (1U << 0) /* 32b */ |
| 2689 | /* PMSR_LAST_CNT (0x10006000+0xF04) */ |
| 2690 | #define PMSR_LAST_CMD_LSB (1U << 0) /* 30b */ |
| 2691 | #define PMSR_LAST_REQ_LSB (1U << 30) /* 1b */ |
| 2692 | /* PMSR_LAST_ACK (0x10006000+0xF08) */ |
| 2693 | #define PMSR_LAST_ACK_LSB (1U << 0) /* 1b */ |
| 2694 | /* SPM_PMSR_SEL_CON0 (0x10006000+0xF10) */ |
| 2695 | #define REG_PMSR_SIG_SEL_0_LSB (1U << 0) /* 8b */ |
| 2696 | #define REG_PMSR_SIG_SEL_1_LSB (1U << 8) /* 8b */ |
| 2697 | #define REG_PMSR_SIG_SEL_2_LSB (1U << 16) /* 8b */ |
| 2698 | #define REG_PMSR_SIG_SEL_3_LSB (1U << 24) /* 8b */ |
| 2699 | /* SPM_PMSR_SEL_CON1 (0x10006000+0xF14) */ |
| 2700 | #define REG_PMSR_SIG_SEL_4_LSB (1U << 0) /* 8b */ |
| 2701 | #define REG_PMSR_SIG_SEL_5_LSB (1U << 8) /* 8b */ |
| 2702 | #define REG_PMSR_SIG_SEL_6_LSB (1U << 16) /* 8b */ |
| 2703 | #define REG_PMSR_SIG_SEL_7_LSB (1U << 24) /* 8b */ |
| 2704 | /* SPM_PMSR_SEL_CON2 (0x10006000+0xF18) */ |
| 2705 | #define REG_PMSR_SIG_SEL_8_LSB (1U << 0) /* 8b */ |
| 2706 | #define REG_PMSR_SIG_SEL_9_LSB (1U << 8) /* 8b */ |
| 2707 | #define REG_PMSR_SIG_SEL_10_LSB (1U << 16) /* 8b */ |
| 2708 | #define REG_PMSR_SIG_SEL_11_LSB (1U << 24) /* 8b */ |
| 2709 | /* SPM_PMSR_SEL_CON3 (0x10006000+0xF1C) */ |
| 2710 | #define REG_PMSR_SIG_SEL_12_LSB (1U << 0) /* 8b */ |
| 2711 | #define REG_PMSR_SIG_SEL_13_LSB (1U << 8) /* 8b */ |
| 2712 | #define REG_PMSR_SIG_SEL_14_LSB (1U << 16) /* 8b */ |
| 2713 | #define REG_PMSR_SIG_SEL_15_LSB (1U << 24) /* 8b */ |
| 2714 | /* SPM_PMSR_SEL_CON4 (0x10006000+0xF20) */ |
| 2715 | #define REG_PMSR_SIG_SEL_16_LSB (1U << 0) /* 8b */ |
| 2716 | #define REG_PMSR_SIG_SEL_17_LSB (1U << 8) /* 8b */ |
| 2717 | #define REG_PMSR_SIG_SEL_18_LSB (1U << 16) /* 8b */ |
| 2718 | #define REG_PMSR_SIG_SEL_19_LSB (1U << 24) /* 8b */ |
| 2719 | /* SPM_PMSR_SEL_CON5 (0x10006000+0xF24) */ |
| 2720 | #define REG_PMSR_SIG_SEL_20_LSB (1U << 0) /* 8b */ |
| 2721 | #define REG_PMSR_SIG_SEL_21_LSB (1U << 8) /* 8b */ |
| 2722 | #define REG_PMSR_SIG_SEL_22_LSB (1U << 16) /* 8b */ |
| 2723 | #define REG_PMSR_SIG_SEL_23_LSB (1U << 24) /* 8b */ |
| 2724 | /* SPM_PMSR_SEL_CON6 (0x10006000+0xF28) */ |
| 2725 | #define REG_PMSR_SIG_SEL_24_LSB (1U << 0) /* 8b */ |
| 2726 | #define REG_PMSR_SIG_SEL_25_LSB (1U << 8) /* 8b */ |
| 2727 | #define REG_PMSR_SIG_SEL_26_LSB (1U << 16) /* 8b */ |
| 2728 | #define REG_PMSR_SIG_SEL_27_LSB (1U << 24) /* 8b */ |
| 2729 | /* SPM_PMSR_SEL_CON7 (0x10006000+0xF2C) */ |
| 2730 | #define REG_PMSR_SIG_SEL_28_LSB (1U << 0) /* 8b */ |
| 2731 | #define REG_PMSR_SIG_SEL_29_LSB (1U << 8) /* 8b */ |
| 2732 | #define REG_PMSR_SIG_SEL_30_LSB (1U << 16) /* 8b */ |
| 2733 | #define REG_PMSR_SIG_SEL_31_LSB (1U << 24) /* 8b */ |
| 2734 | /* SPM_PMSR_SEL_CON8 (0x10006000+0xF30) */ |
| 2735 | #define REG_PMSR_SIG_SEL_32_LSB (1U << 0) /* 8b */ |
| 2736 | #define REG_PMSR_SIG_SEL_33_LSB (1U << 8) /* 8b */ |
| 2737 | #define REG_PMSR_SIG_SEL_34_LSB (1U << 16) /* 8b */ |
| 2738 | #define REG_PMSR_SIG_SEL_35_LSB (1U << 24) /* 8b */ |
| 2739 | /* SPM_PMSR_SEL_CON9 (0x10006000+0xF34) */ |
| 2740 | #define REG_PMSR_SIG_SEL_36_LSB (1U << 0) /* 8b */ |
| 2741 | #define REG_PMSR_SIG_SEL_37_LSB (1U << 8) /* 8b */ |
| 2742 | #define REG_PMSR_SIG_SEL_38_LSB (1U << 16) /* 8b */ |
| 2743 | #define REG_PMSR_SIG_SEL_39_LSB (1U << 24) /* 8b */ |
| 2744 | /* SPM_PMSR_SEL_CON10 (0x10006000+0xF3C) */ |
| 2745 | #define REG_PMSR_SIG_SEL_40_LSB (1U << 0) /* 8b */ |
| 2746 | #define REG_PMSR_SIG_SEL_41_LSB (1U << 8) /* 8b */ |
| 2747 | #define REG_PMSR_SIG_SEL_42_LSB (1U << 16) /* 8b */ |
| 2748 | #define REG_PMSR_SIG_SEL_43_LSB (1U << 24) /* 8b */ |
| 2749 | /* SPM_PMSR_SEL_CON11 (0x10006000+0xF40) */ |
| 2750 | #define REG_PMSR_SIG_SEL_44_LSB (1U << 0) /* 8b */ |
| 2751 | #define REG_PMSR_SIG_SEL_45_LSB (1U << 8) /* 8b */ |
| 2752 | #define REG_PMSR_SIG_SEL_46_LSB (1U << 16) /* 8b */ |
| 2753 | #define REG_PMSR_SIG_SEL_47_LSB (1U << 24) /* 8b */ |
| 2754 | /* SPM_PMSR_TIEMR_STA0 (0x10006000+0xFB8) */ |
| 2755 | #define PMSR_TIMER_SET0_LSB (1U << 0) /* 32b */ |
| 2756 | /* SPM_PMSR_TIEMR_STA1 (0x10006000+0xFBC) */ |
| 2757 | #define PMSR_TIMER_SET1_LSB (1U << 0) /* 32b */ |
| 2758 | /* SPM_PMSR_TIEMR_STA2 (0x10006000+0xFC0) */ |
| 2759 | #define PMSR_TIMER_SET2_LSB (1U << 0) /* 32b */ |
| 2760 | /* SPM_PMSR_GENERAL_CON0 (0x10006000+0xFC4) */ |
| 2761 | #define PMSR_ENABLE_SET0_LSB (1U << 0) /* 1b */ |
| 2762 | #define PMSR_ENABLE_SET1_LSB (1U << 1) /* 1b */ |
| 2763 | #define PMSR_ENABLE_SET2_LSB (1U << 2) /* 1b */ |
| 2764 | #define PMSR_IRQ_CLR_SET0_LSB (1U << 3) /* 1b */ |
| 2765 | #define PMSR_IRQ_CLR_SET1_LSB (1U << 4) /* 1b */ |
| 2766 | #define PMSR_IRQ_CLR_SET2_LSB (1U << 5) /* 1b */ |
| 2767 | #define PMSR_SPEED_MODE_EN_SET0_LSB (1U << 6) /* 1b */ |
| 2768 | #define PMSR_SPEED_MODE_EN_SET1_LSB (1U << 7) /* 1b */ |
| 2769 | #define PMSR_SPEED_MODE_EN_SET2_LSB (1U << 8) /* 1b */ |
| 2770 | #define PMSR_EVENT_CLR_SET0_LSB (1U << 9) /* 1b */ |
| 2771 | #define PMSR_EVENT_CLR_SET1_LSB (1U << 10) /* 1b */ |
| 2772 | #define PMSR_EVENT_CLR_SET2_LSB (1U << 11) /* 1b */ |
| 2773 | #define REG_PMSR_IRQ_MASK_SET0_LSB (1U << 12) /* 1b */ |
| 2774 | #define REG_PMSR_IRQ_MASK_SET1_LSB (1U << 13) /* 1b */ |
| 2775 | #define REG_PMSR_IRQ_MASK_SET2_LSB (1U << 14) /* 1b */ |
| 2776 | #define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET0_LSB (1U << 15) /* 1b */ |
| 2777 | #define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET1_LSB (1U << 16) /* 1b */ |
| 2778 | #define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET2_LSB (1U << 17) /* 1b */ |
| 2779 | #define PMSR_GEN_SW_RST_EN_LSB (1U << 18) /* 1b */ |
| 2780 | #define PMSR_MODULE_ENABLE_LSB (1U << 19) /* 1b */ |
| 2781 | #define PMSR_MODE_LSB (1U << 20) /* 2b */ |
| 2782 | #define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET0_LSB (1U << 29) /* 1b */ |
| 2783 | #define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET1_LSB (1U << 30) /* 1b */ |
| 2784 | #define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET2_LSB (1U << 31) /* 1b */ |
| 2785 | /* SPM_PMSR_GENERAL_CON1 (0x10006000+0xFC8) */ |
| 2786 | #define PMSR_COUNTER_THRES_LSB (1U << 0) /* 32b */ |
| 2787 | /* SPM_PMSR_GENERAL_CON2 (0x10006000+0xFCC) */ |
| 2788 | #define PMSR_DEBUG_IN_0_MASK_B_LSB (1U << 0) /* 32b */ |
| 2789 | /* SPM_PMSR_GENERAL_CON3 (0x10006000+0xFD0) */ |
| 2790 | #define PMSR_DEBUG_IN_1_MASK_B_LSB (1U << 0) /* 32b */ |
| 2791 | /* SPM_PMSR_GENERAL_CON4 (0x10006000+0xFD4) */ |
| 2792 | #define PMSR_DEBUG_IN_2_MASK_B_LSB (1U << 0) /* 32b */ |
| 2793 | /* SPM_PMSR_GENERAL_CON5 (0x10006000+0xFD8) */ |
| 2794 | #define PMSR_DEBUG_IN_3_MASK_B_LSB (1U << 0) /* 32b */ |
| 2795 | /* SPM_PMSR_SW_RESET (0x10006000+0xFDC) */ |
| 2796 | #define PMSR_SW_RST_EN_SET0_LSB (1U << 0) /* 1b */ |
| 2797 | #define PMSR_SW_RST_EN_SET1_LSB (1U << 1) /* 1b */ |
| 2798 | #define PMSR_SW_RST_EN_SET2_LSB (1U << 2) /* 1b */ |
| 2799 | /* SPM_PMSR_MON_CON0 (0x10006000+0xFE0) */ |
| 2800 | #define REG_PMSR_MON_TYPE_0_LSB (1U << 0) /* 2b */ |
| 2801 | #define REG_PMSR_MON_TYPE_1_LSB (1U << 2) /* 2b */ |
| 2802 | #define REG_PMSR_MON_TYPE_2_LSB (1U << 4) /* 2b */ |
| 2803 | #define REG_PMSR_MON_TYPE_3_LSB (1U << 6) /* 2b */ |
| 2804 | #define REG_PMSR_MON_TYPE_4_LSB (1U << 8) /* 2b */ |
| 2805 | #define REG_PMSR_MON_TYPE_5_LSB (1U << 10) /* 2b */ |
| 2806 | #define REG_PMSR_MON_TYPE_6_LSB (1U << 12) /* 2b */ |
| 2807 | #define REG_PMSR_MON_TYPE_7_LSB (1U << 14) /* 2b */ |
| 2808 | #define REG_PMSR_MON_TYPE_8_LSB (1U << 16) /* 2b */ |
| 2809 | #define REG_PMSR_MON_TYPE_9_LSB (1U << 18) /* 2b */ |
| 2810 | #define REG_PMSR_MON_TYPE_10_LSB (1U << 20) /* 2b */ |
| 2811 | #define REG_PMSR_MON_TYPE_11_LSB (1U << 22) /* 2b */ |
| 2812 | #define REG_PMSR_MON_TYPE_12_LSB (1U << 24) /* 2b */ |
| 2813 | #define REG_PMSR_MON_TYPE_13_LSB (1U << 26) /* 2b */ |
| 2814 | #define REG_PMSR_MON_TYPE_14_LSB (1U << 28) /* 2b */ |
| 2815 | #define REG_PMSR_MON_TYPE_15_LSB (1U << 30) /* 2b */ |
| 2816 | /* SPM_PMSR_MON_CON1 (0x10006000+0xFE4) */ |
| 2817 | #define REG_PMSR_MON_TYPE_16_LSB (1U << 0) /* 2b */ |
| 2818 | #define REG_PMSR_MON_TYPE_17_LSB (1U << 2) /* 2b */ |
| 2819 | #define REG_PMSR_MON_TYPE_18_LSB (1U << 4) /* 2b */ |
| 2820 | #define REG_PMSR_MON_TYPE_19_LSB (1U << 6) /* 2b */ |
| 2821 | #define REG_PMSR_MON_TYPE_20_LSB (1U << 8) /* 2b */ |
| 2822 | #define REG_PMSR_MON_TYPE_21_LSB (1U << 10) /* 2b */ |
| 2823 | #define REG_PMSR_MON_TYPE_22_LSB (1U << 12) /* 2b */ |
| 2824 | #define REG_PMSR_MON_TYPE_23_LSB (1U << 14) /* 2b */ |
| 2825 | #define REG_PMSR_MON_TYPE_24_LSB (1U << 16) /* 2b */ |
| 2826 | #define REG_PMSR_MON_TYPE_25_LSB (1U << 18) /* 2b */ |
| 2827 | #define REG_PMSR_MON_TYPE_26_LSB (1U << 20) /* 2b */ |
| 2828 | #define REG_PMSR_MON_TYPE_27_LSB (1U << 22) /* 2b */ |
| 2829 | #define REG_PMSR_MON_TYPE_28_LSB (1U << 24) /* 2b */ |
| 2830 | #define REG_PMSR_MON_TYPE_29_LSB (1U << 26) /* 2b */ |
| 2831 | #define REG_PMSR_MON_TYPE_30_LSB (1U << 28) /* 2b */ |
| 2832 | #define REG_PMSR_MON_TYPE_31_LSB (1U << 30) /* 2b */ |
| 2833 | /* SPM_PMSR_MON_CON2 (0x10006000+0xFE8) */ |
| 2834 | #define REG_PMSR_MON_TYPE_32_LSB (1U << 0) /* 2b */ |
| 2835 | #define REG_PMSR_MON_TYPE_33_LSB (1U << 2) /* 2b */ |
| 2836 | #define REG_PMSR_MON_TYPE_34_LSB (1U << 4) /* 2b */ |
| 2837 | #define REG_PMSR_MON_TYPE_35_LSB (1U << 6) /* 2b */ |
| 2838 | #define REG_PMSR_MON_TYPE_36_LSB (1U << 8) /* 2b */ |
| 2839 | #define REG_PMSR_MON_TYPE_37_LSB (1U << 10) /* 2b */ |
| 2840 | #define REG_PMSR_MON_TYPE_38_LSB (1U << 12) /* 2b */ |
| 2841 | #define REG_PMSR_MON_TYPE_39_LSB (1U << 14) /* 2b */ |
| 2842 | #define REG_PMSR_MON_TYPE_40_LSB (1U << 16) /* 2b */ |
| 2843 | #define REG_PMSR_MON_TYPE_41_LSB (1U << 18) /* 2b */ |
| 2844 | #define REG_PMSR_MON_TYPE_42_LSB (1U << 20) /* 2b */ |
| 2845 | #define REG_PMSR_MON_TYPE_43_LSB (1U << 22) /* 2b */ |
| 2846 | #define REG_PMSR_MON_TYPE_44_LSB (1U << 24) /* 2b */ |
| 2847 | #define REG_PMSR_MON_TYPE_45_LSB (1U << 26) /* 2b */ |
| 2848 | #define REG_PMSR_MON_TYPE_46_LSB (1U << 28) /* 2b */ |
| 2849 | #define REG_PMSR_MON_TYPE_47_LSB (1U << 30) /* 2b */ |
| 2850 | /* SPM_PMSR_LEN_CON0 (0x10006000+0xFEC) */ |
| 2851 | #define REG_PMSR_WINDOW_LEN_SET0_LSB (1U << 0) /* 32b */ |
| 2852 | /* SPM_PMSR_LEN_CON1 (0x10006000+0xFF0) */ |
| 2853 | #define REG_PMSR_WINDOW_LEN_SET1_LSB (1U << 0) /* 32b */ |
| 2854 | /* SPM_PMSR_LEN_CON2 (0x10006000+0xFF4) */ |
| 2855 | #define REG_PMSR_WINDOW_LEN_SET2_LSB (1U << 0) /* 32b */ |
| 2856 | |
| 2857 | #define SPM_PROJECT_CODE 0xb16 |
| 2858 | #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) |
| 2859 | #endif |