blob: 5e42bd7840d1da5f8e61b392cda980528475e200 [file] [log] [blame]
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05301/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef VERSAL_DEF_H
8#define VERSAL_DEF_H
9
10#include <common_def.h>
11
12/* List all consoles */
13#define VERSAL_CONSOLE_ID_pl011 1
14#define VERSAL_CONSOLE_ID_pl011_0 1
15#define VERSAL_CONSOLE_ID_pl011_1 2
16#define VERSAL_CONSOLE_ID_dcc 3
17
18#define VERSAL_CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE)
19
20/* List all supported platforms */
21#define VERSAL_PLATFORM_ID_versal_virt 1
22
23#define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM)
24
25/* Firmware Image Package */
26#define VERSAL_PRIMARY_CPU 0
27
28/*******************************************************************************
29 * memory map related constants
30 ******************************************************************************/
31#define DEVICE0_BASE 0xFF000000
32#define DEVICE0_SIZE 0x00E00000
33#define DEVICE1_BASE 0xF9000000
34#define DEVICE1_SIZE 0x00800000
35
36/* CRL */
37#define VERSAL_CRL 0xFF5E0000
38#define VERSAL_CRL_IOU_SWITCH_CTRL (VERSAL_CRL + 0x114)
39#define VERSAL_CRL_TIMESTAMP_REF_CTRL (VERSAL_CRL + 0x14C)
40#define VERSAL_CRL_RST_TIMESTAMP_OFFSET (VERSAL_CRL + 0x348)
41
42#define VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1 << 25)
43#define VERSAL_IOU_SWITCH_CTRL_CLKACT_BIT (1 << 25)
44#define VERSAL_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8
45
46/* IOU SCNTRS */
47#define VERSAL_IOU_SCNTRS 0xFF140000
48#define VERSAL_IOU_SCNTRS_COUNTER_CONTROL_REG (VERSAL_IOU_SCNTRS + 0x0)
49#define VERSAL_IOU_SCNTRS_BASE_FREQ (VERSAL_IOU_SCNTRS + 0x20)
50
51#define VERSAL_IOU_SCNTRS_CONTROL_EN 1
52
53/*******************************************************************************
54 * IRQ constants
55 ******************************************************************************/
56#define VERSAL_IRQ_SEC_PHY_TIMER 29
57
58/*******************************************************************************
59 * UART related constants
60 ******************************************************************************/
61#define VERSAL_UART0_BASE 0xFF000000
62#define VERSAL_UART1_BASE 0xFF010000
63
64#if VERSAL_CONSOLE_IS(pl011)
65# define VERSAL_UART_BASE VERSAL_UART0_BASE
66#elif VERSAL_CONSOLE_IS(pl011_1)
67# define VERSAL_UART_BASE VERSAL_UART1_BASE
68#else
69# error "invalid VERSAL_CONSOLE"
70#endif
71
72#define PLAT_VERSAL_CRASH_UART_BASE VERSAL_UART_BASE
73#define PLAT_VERSAL_CRASH_UART_CLK_IN_HZ VERSAL_UART_CLOCK
74#define VERSAL_CONSOLE_BAUDRATE VERSAL_UART_BAUDRATE
75
76/*******************************************************************************
77 * Platform related constants
78 ******************************************************************************/
79#if VERSAL_PLATFORM_IS(versal_virt)
80# define PLATFORM_NAME "Versal Virt"
81# define VERSAL_UART_CLOCK 25000000
82# define VERSAL_UART_BAUDRATE 115200
83# define VERSAL_CPU_CLOCK 62500000
84#endif
85
86/* Access control register defines */
87#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
88#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
89
90/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
91#define CRF_BASE 0xFD1A0000
92#define CRF_SIZE 0x00600000
93
94/* CRF registers and bitfields */
95#define CRF_RST_APU (CRF_BASE + 0X00000300)
96
97#define CRF_RST_APU_ACPU_RESET (1 << 0)
98#define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10)
99
100/* APU registers and bitfields */
101#define FPD_APU_BASE 0xFD5C0000
102#define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20)
103#define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40)
104#define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44)
105#define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90)
106
107#define FPD_APU_CONFIG_0_VINITHI_SHIFT 8
108
109#endif /* VERSAL_DEF_H */