| Hari Nagalla | 3c0ef77 | 2022-08-22 14:04:52 -0500 | [diff] [blame] | 1 | # |
| 2 | # Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. |
| 3 | # |
| 4 | # SPDX-License-Identifier: BSD-3-Clause |
| 5 | # |
| 6 | |
| 7 | BL32_BASE ?= 0x9e800000 |
| 8 | $(eval $(call add_define,BL32_BASE)) |
| 9 | |
| 10 | PRELOADED_BL33_BASE ?= 0x80080000 |
| 11 | $(eval $(call add_define,PRELOADED_BL33_BASE)) |
| 12 | |
| 13 | K3_HW_CONFIG_BASE ?= 0x82000000 |
| 14 | $(eval $(call add_define,K3_HW_CONFIG_BASE)) |
| 15 | |
| 16 | # Define sec_proxy usage as the full prioritized communication scheme |
| 17 | K3_SEC_PROXY_LITE := 0 |
| 18 | $(eval $(call add_define,K3_SEC_PROXY_LITE)) |
| 19 | |
| Andrew Davis | e7d7d11 | 2023-01-10 13:14:37 -0600 | [diff] [blame] | 20 | # Use a 4 cycle data RAM latency for J784s4 |
| 21 | K3_DATA_RAM_4_LATENCY := 1 |
| 22 | $(eval $(call add_define,K3_DATA_RAM_4_LATENCY)) |
| 23 | |
| Hari Nagalla | 3c0ef77 | 2022-08-22 14:04:52 -0500 | [diff] [blame] | 24 | # System coherency is managed in hardware |
| 25 | USE_COHERENT_MEM := 1 |
| 26 | |
| 27 | PLAT_INCLUDES += \ |
| 28 | -Iplat/ti/k3/board/j784s4/include \ |