blob: 5ccbc8c3a7cfdb20ecead9b4a9870990e1413e41 [file] [log] [blame]
Hadi Asyrafi616da772019-06-27 11:34:03 +08001/*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2019, Intel Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef AGX_PRIVATE_H
9#define AGX_PRIVATE_H
10
11#define AGX_MMC_REG_BASE 0xff808000
12
13#define EMMC_DESC_SIZE (1<<20)
14#define EMMC_INIT_PARAMS(base) \
15 { .bus_width = MMC_BUS_WIDTH_4, \
16 .clk_rate = 50000000, \
17 .desc_base = (base), \
18 .desc_size = EMMC_DESC_SIZE, \
19 .flags = 0, \
20 .reg_base = AGX_MMC_REG_BASE, \
21 \
22 }
23
24typedef enum {
25 BOOT_SOURCE_FPGA = 0,
26 BOOT_SOURCE_SDMMC,
27 BOOT_SOURCE_NAND,
28 BOOT_SOURCE_RSVD,
29 BOOT_SOURCE_QSPI,
30} boot_source_type;
31
32void enable_nonsecure_access(void);
33void socfpga_io_setup(int boot_source);
34
35#endif