Paul Beesley | f3653a6 | 2019-05-22 11:22:44 +0100 | [diff] [blame] | 1 | Arm Versatile Express |
| 2 | ===================== |
Usama Arif | b8cd97f | 2019-02-05 15:44:17 +0000 | [diff] [blame] | 3 | |
John Tsichritzis | 4730c11 | 2019-07-05 14:14:40 +0100 | [diff] [blame] | 4 | Versatile Express (VE) family development platform provides an ultra fast |
| 5 | environment for prototyping Armv7 System-on-Chip designs. VE Fixed Virtual |
| 6 | Platforms (FVP) are simulations of Versatile Express boards. The platform in |
| 7 | Trusted Firmware-A has been verified with Arm Cortex-A5 and Cortex-A7 VE FVP's. |
| 8 | This platform is tested on and only expected to work with single core models. |
Usama Arif | b8cd97f | 2019-02-05 15:44:17 +0000 | [diff] [blame] | 9 | |
| 10 | Boot Sequence |
Paul Beesley | f3653a6 | 2019-05-22 11:22:44 +0100 | [diff] [blame] | 11 | ------------- |
Usama Arif | b8cd97f | 2019-02-05 15:44:17 +0000 | [diff] [blame] | 12 | |
| 13 | BL1 --> BL2 --> BL32(sp_min) --> BL33(u-boot) --> Linux kernel |
| 14 | |
| 15 | How to build |
Paul Beesley | f3653a6 | 2019-05-22 11:22:44 +0100 | [diff] [blame] | 16 | ------------ |
Usama Arif | b8cd97f | 2019-02-05 15:44:17 +0000 | [diff] [blame] | 17 | |
| 18 | Code Locations |
Paul Beesley | f3653a6 | 2019-05-22 11:22:44 +0100 | [diff] [blame] | 19 | ~~~~~~~~~~~~~~ |
Usama Arif | b8cd97f | 2019-02-05 15:44:17 +0000 | [diff] [blame] | 20 | - `U-boot <https://git.linaro.org/landing-teams/working/arm/u-boot.git>`__ |
| 21 | |
John Tsichritzis | 4730c11 | 2019-07-05 14:14:40 +0100 | [diff] [blame] | 22 | - `Trusted Firmware-A <https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git>`__ |
Usama Arif | b8cd97f | 2019-02-05 15:44:17 +0000 | [diff] [blame] | 23 | |
| 24 | Build Procedure |
Paul Beesley | f3653a6 | 2019-05-22 11:22:44 +0100 | [diff] [blame] | 25 | ~~~~~~~~~~~~~~~ |
Usama Arif | b8cd97f | 2019-02-05 15:44:17 +0000 | [diff] [blame] | 26 | |
| 27 | - Obtain arm toolchain. The software stack has been verified with linaro 6.2 |
| 28 | `arm-linux-gnueabihf <https://releases.linaro.org/components/toolchain/binaries/6.2-2016.11/arm-linux-gnueabihf/>`__. |
| 29 | Set the CROSS_COMPILE environment variable to point to the toolchain folder. |
| 30 | |
| 31 | - Fetch and build u-boot. |
| 32 | Make the .config file using the command: |
| 33 | |
| 34 | .. code:: shell |
| 35 | |
| 36 | make ARCH=arm vexpress_aemv8a_aarch32_config |
| 37 | |
| 38 | Make the u-boot binary for Cortex-A5 using the command: |
| 39 | |
| 40 | .. code:: shell |
| 41 | |
| 42 | make ARCH=arm SUPPORT_ARCH_TIMER=no |
| 43 | |
| 44 | Make the u-boot binary for Cortex-A7 using the command: |
| 45 | |
| 46 | .. code:: shell |
| 47 | |
| 48 | make ARCH=arm |
| 49 | |
| 50 | |
| 51 | - Build TF-A: |
| 52 | |
| 53 | The make command for Cortex-A5 is: |
| 54 | |
| 55 | .. code:: shell |
| 56 | |
| 57 | make PLAT=fvp_ve ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A5=yes \ |
| 58 | AARCH32_SP=sp_min FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A5x1.dts \ |
| 59 | ARM_XLAT_TABLES_LIB_V1=1 BL33=<path_to_u-boot.bin> all fip |
| 60 | |
| 61 | The make command for Cortex-A7 is: |
| 62 | |
| 63 | .. code:: shell |
| 64 | |
| 65 | make PLAT=fvp_ve ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes \ |
| 66 | AARCH32_SP=sp_min FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A7x1.dts \ |
| 67 | BL33=<path_to_u-boot.bin> all fip |
| 68 | |
| 69 | Run Procedure |
Paul Beesley | f3653a6 | 2019-05-22 11:22:44 +0100 | [diff] [blame] | 70 | ~~~~~~~~~~~~~ |
Usama Arif | b8cd97f | 2019-02-05 15:44:17 +0000 | [diff] [blame] | 71 | |
| 72 | The following model parameters should be used to boot Linux using the build of |
John Tsichritzis | 4730c11 | 2019-07-05 14:14:40 +0100 | [diff] [blame] | 73 | Trusted Firmware-A made using the above make commands: |
Usama Arif | b8cd97f | 2019-02-05 15:44:17 +0000 | [diff] [blame] | 74 | |
| 75 | .. code:: shell |
| 76 | |
| 77 | ./<path_to_model> <path_to_bl1.elf> \ |
| 78 | -C motherboard.flashloader1.fname=<path_to_fip.bin> \ |
| 79 | --data cluster.cpu0=<path_to_zImage>@0x80080000 \ |
| 80 | --data cluster.cpu0=<path_to_ramdisk>@0x84000000 |