Pankaj Gupta | f24e1a3 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 1 | /* |
Jiafei Pan | b27ac80 | 2021-07-20 17:14:32 +0800 | [diff] [blame] | 2 | * Copyright 2018-2021 NXP |
Pankaj Gupta | f24e1a3 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #ifndef _SOC_H |
| 9 | #define _SOC_H |
| 10 | |
| 11 | /* Chassis specific defines - common across SoC's of a particular platform */ |
| 12 | #include <dcfg_lsch3.h> |
| 13 | #include <soc_default_base_addr.h> |
| 14 | #include <soc_default_helper_macros.h> |
| 15 | |
| 16 | |
| 17 | #define NUM_DRAM_REGIONS 3 |
| 18 | #define NXP_DRAM0_ADDR 0x80000000 |
| 19 | #define NXP_DRAM0_MAX_SIZE 0x80000000 /* 2 GB */ |
| 20 | |
| 21 | #define NXP_DRAM1_ADDR 0x2080000000 |
| 22 | #define NXP_DRAM1_MAX_SIZE 0x1F80000000 /* 126 G */ |
| 23 | |
| 24 | #define NXP_DRAM2_ADDR 0x6000000000 |
| 25 | #define NXP_DRAM2_MAX_SIZE 0x2000000000 /* 128G */ |
| 26 | |
| 27 | /*DRAM0 Size defined in platform_def.h */ |
| 28 | #define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE |
| 29 | |
| 30 | #define DDR_PLL_FIX |
| 31 | #define NXP_DDR_PHY1_ADDR 0x01400000 |
| 32 | #define NXP_DDR_PHY2_ADDR 0x01600000 |
| 33 | |
| 34 | #if defined(IMAGE_BL31) |
| 35 | #define LS_SYS_TIMCTL_BASE 0x2890000 |
| 36 | |
| 37 | #ifdef LS_SYS_TIMCTL_BASE |
| 38 | #define PLAT_LS_NSTIMER_FRAME_ID 0 |
| 39 | #define LS_CONFIG_CNTACR 1 |
| 40 | #endif |
| 41 | #endif |
| 42 | |
| 43 | /* Start: Macros used by soc.c: get_boot_dev */ |
| 44 | #define PORSR1_RCW_MASK 0x07800000 |
| 45 | #define PORSR1_RCW_SHIFT 23 |
| 46 | |
| 47 | #define SDHC1_VAL 0x8 |
| 48 | #define SDHC2_VAL 0x9 |
| 49 | #define I2C1_VAL 0xa |
| 50 | #define FLEXSPI_NAND2K_VAL 0xc |
| 51 | #define FLEXSPI_NAND4K_VAL 0xd |
| 52 | #define FLEXSPI_NOR 0xf |
| 53 | /* End: Macros used by soc.c: get_boot_dev */ |
| 54 | |
Jiafei Pan | b27ac80 | 2021-07-20 17:14:32 +0800 | [diff] [blame] | 55 | /* SVR Definition (not include major and minor rev) */ |
| 56 | #define SVR_LX2160A 0x873601 |
Jiafei Pan | 616a94a | 2022-06-10 17:26:34 +0800 | [diff] [blame^] | 57 | #define SVR_LX2160E 0x873610 |
| 58 | #define SVR_LX2160C 0x873600 |
| 59 | #define SVR_LX2160N 0x873611 |
Jiafei Pan | b27ac80 | 2021-07-20 17:14:32 +0800 | [diff] [blame] | 60 | #define SVR_LX2120A 0x873621 |
Jiafei Pan | 616a94a | 2022-06-10 17:26:34 +0800 | [diff] [blame^] | 61 | #define SVR_LX2120E 0x873630 |
| 62 | #define SVR_LX2120C 0x873620 |
| 63 | #define SVR_LX2120N 0x873631 |
Jiafei Pan | b27ac80 | 2021-07-20 17:14:32 +0800 | [diff] [blame] | 64 | #define SVR_LX2080A 0x873603 |
Jiafei Pan | 616a94a | 2022-06-10 17:26:34 +0800 | [diff] [blame^] | 65 | #define SVR_LX2080E 0x873612 |
| 66 | #define SVR_LX2080C 0x873602 |
| 67 | #define SVR_LX2080N 0x873613 |
| 68 | |
| 69 | /* SVR Definition of SoC LX2162A. */ |
| 70 | #define SVR_LX2162A 0x873609 |
| 71 | #define SVR_LX2162E 0x873618 |
| 72 | #define SVR_LX2162C 0x873608 |
| 73 | #define SVR_LX2162N 0x873619 |
| 74 | #define SVR_LX2122A 0x873629 |
| 75 | #define SVR_LX2122E 0x873638 |
| 76 | #define SVR_LX2122C 0x873628 |
| 77 | #define SVR_LX2122N 0x873639 |
| 78 | #define SVR_LX2082A 0x87360b |
| 79 | #define SVR_LX2082E 0x87361a |
| 80 | #define SVR_LX2082C 0x87360a |
| 81 | #define SVR_LX2082N 0x87361b |
Pankaj Gupta | f24e1a3 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 82 | |
| 83 | /* Number of cores in platform */ |
| 84 | /* Used by common code for array initialization */ |
| 85 | #define NUMBER_OF_CLUSTERS 8 |
| 86 | #define CORES_PER_CLUSTER 2 |
| 87 | #define PLATFORM_CORE_COUNT NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER |
| 88 | |
| 89 | /* |
| 90 | * Required LS standard platform porting definitions |
| 91 | * for CCN-508 |
| 92 | */ |
| 93 | #define PLAT_CLUSTER_TO_CCN_ID_MAP 11, 15, 27, 31, 12, 28, 16, 0 |
| 94 | #define PLAT_6CLUSTER_TO_CCN_ID_MAP 11, 15, 27, 31, 12, 28 |
| 95 | |
| 96 | |
| 97 | /* Defines required for using XLAT tables from ARM common code */ |
| 98 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 40) |
| 99 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 40) |
| 100 | |
| 101 | /* Clock Divisors */ |
| 102 | #define NXP_PLATFORM_CLK_DIVIDER 2 |
| 103 | #define NXP_UART_CLK_DIVIDER 4 |
| 104 | |
| 105 | /* Start: Macros used by lx2160a.S */ |
| 106 | #define MPIDR_AFFINITY0_MASK 0x00FF |
| 107 | #define MPIDR_AFFINITY1_MASK 0xFF00 |
| 108 | #define CPUECTLR_DISABLE_TWALK_PREFETCH 0x4000000000 |
| 109 | #define CPUECTLR_INS_PREFETCH_MASK 0x1800000000 |
| 110 | #define CPUECTLR_DAT_PREFETCH_MASK 0x0300000000 |
| 111 | #define CPUECTLR_RET_8CLK 0x2 |
| 112 | #define OSDLR_EL1_DLK_LOCK 0x1 |
| 113 | #define CNTP_CTL_EL0_EN 0x1 |
| 114 | #define CNTP_CTL_EL0_IMASK 0x2 |
| 115 | /* set to 0 if the clusters are not symmetrical */ |
| 116 | #define SYMMETRICAL_CLUSTERS 1 |
| 117 | /* End: Macros used by lx2160a.S */ |
| 118 | |
| 119 | /* Start: Macros used by lib/psci files */ |
| 120 | #define SYSTEM_PWR_DOMAINS 1 |
| 121 | #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ |
| 122 | NUMBER_OF_CLUSTERS + \ |
| 123 | SYSTEM_PWR_DOMAINS) |
| 124 | |
| 125 | /* Power state coordination occurs at the system level */ |
| 126 | #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 |
| 127 | |
| 128 | /* define retention state */ |
| 129 | #define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1) |
| 130 | |
| 131 | /* define power-down state */ |
| 132 | #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1) |
| 133 | /* End: Macros used by lib/psci files */ |
| 134 | |
| 135 | /* Some data must be aligned on the biggest cache line size in the platform. |
| 136 | * This is known only to the platform as it might have a combination of |
| 137 | * integrated and external caches. |
| 138 | * |
| 139 | * CACHE_WRITEBACK_GRANULE is defined in soc.def |
| 140 | * |
| 141 | * One cache line needed for bakery locks on ARM platforms |
| 142 | */ |
| 143 | #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) |
| 144 | |
| 145 | #ifndef WDOG_RESET_FLAG |
| 146 | #define WDOG_RESET_FLAG DEFAULT_SET_VALUE |
| 147 | #endif |
| 148 | |
| 149 | #ifndef WARM_BOOT_SUCCESS |
| 150 | #define WARM_BOOT_SUCCESS DEFAULT_SET_VALUE |
| 151 | #endif |
| 152 | |
| 153 | #ifndef __ASSEMBLER__ |
| 154 | |
| 155 | void set_base_freq_CNTFID0(void); |
| 156 | void soc_init_start(void); |
| 157 | void soc_init_finish(void); |
| 158 | void soc_init_percpu(void); |
| 159 | void _soc_set_start_addr(unsigned long addr); |
| 160 | void _set_platform_security(void); |
| 161 | |
| 162 | #endif |
| 163 | |
| 164 | #endif /* _SOC_H */ |