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Jimmy Brisson7cc90c42020-09-30 15:34:51 -05001/*
Bipin Ravieb4d12b2022-03-12 01:58:02 -06002 * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
Varun Wadekar9030a6c2022-03-09 22:04:00 +00003 * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
Jimmy Brisson7cc90c42020-09-30 15:34:51 -05004 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef CORTEX_A78_AE_H
9#define CORTEX_A78_AE_H
10
11#include <cortex_a78.h>
12
Bipin Ravieb4d12b2022-03-12 01:58:02 -060013#define CORTEX_A78_AE_MIDR U(0x410FD420)
14
15/* Cortex-A78AE loop count for CVE-2022-23960 mitigation */
16#define CORTEX_A78_AE_BHB_LOOP_COUNT U(32)
Jimmy Brisson7cc90c42020-09-30 15:34:51 -050017
Varun Wadekar0914fc42021-07-27 02:32:29 -070018/*******************************************************************************
19 * CPU Extended Control register specific definitions.
20 ******************************************************************************/
21#define CORTEX_A78_AE_CPUECTLR_EL1 CORTEX_A78_CPUECTLR_EL1
22#define CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 CORTEX_A78_CPUECTLR_EL1_BIT_8
23
Varun Wadekar9030a6c2022-03-09 22:04:00 +000024/*******************************************************************************
25 * CPU Auxiliary Control register 2 specific definitions.
26 ******************************************************************************/
27#define CORTEX_A78_AE_ACTLR2_EL1 CORTEX_A78_ACTLR2_EL1
28#define CORTEX_A78_AE_ACTLR2_EL1_BIT_0 CORTEX_A78_ACTLR2_EL1_BIT_0
Varun Wadekarac6bf2e2022-03-09 22:20:32 +000029#define CORTEX_A78_AE_ACTLR2_EL1_BIT_40 CORTEX_A78_ACTLR2_EL1_BIT_40
Varun Wadekar9030a6c2022-03-09 22:04:00 +000030
Jimmy Brisson7cc90c42020-09-30 15:34:51 -050031#endif /* CORTEX_A78_AE_H */