Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 1 | /* |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 2 | * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 5 | */ |
| 6 | #include <arch.h> |
| 7 | #include <asm_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | #include <common/bl_common.h> |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 9 | #include <cortex_a73.h> |
| 10 | #include <cpu_macros.S> |
| 11 | #include <plat_macros.S> |
| 12 | |
| 13 | /* --------------------------------------------- |
| 14 | * Disable L1 data cache |
| 15 | * --------------------------------------------- |
| 16 | */ |
| 17 | func cortex_a73_disable_dcache |
Sona Mathew | 3b01893 | 2023-06-19 19:08:18 -0500 | [diff] [blame] | 18 | sysreg_bit_clear sctlr_el3, SCTLR_C_BIT |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 19 | isb |
| 20 | ret |
| 21 | endfunc cortex_a73_disable_dcache |
| 22 | |
| 23 | /* --------------------------------------------- |
| 24 | * Disable intra-cluster coherency |
| 25 | * --------------------------------------------- |
| 26 | */ |
| 27 | func cortex_a73_disable_smp |
Sona Mathew | 3b01893 | 2023-06-19 19:08:18 -0500 | [diff] [blame] | 28 | sysreg_bit_clear CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 29 | isb |
| 30 | dsb sy |
| 31 | ret |
| 32 | endfunc cortex_a73_disable_smp |
| 33 | |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 34 | func check_smccc_arch_workaround_3 |
| 35 | mov x0, #ERRATA_APPLIES |
| 36 | ret |
| 37 | endfunc check_smccc_arch_workaround_3 |
| 38 | |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 39 | workaround_reset_start cortex_a73, ERRATUM(852427), ERRATA_A73_852427 |
Sona Mathew | 3b01893 | 2023-06-19 19:08:18 -0500 | [diff] [blame] | 40 | sysreg_bit_set CORTEX_A73_DIAGNOSTIC_REGISTER, BIT(12) |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 41 | workaround_reset_end cortex_a73, ERRATUM(852427) |
Louis Mayencourt | d69722c | 2019-02-27 14:24:16 +0000 | [diff] [blame] | 42 | |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 43 | check_erratum_ls cortex_a73, ERRATUM(852427), CPU_REV(0, 0) |
Louis Mayencourt | d69722c | 2019-02-27 14:24:16 +0000 | [diff] [blame] | 44 | |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 45 | workaround_reset_start cortex_a73, ERRATUM(855423), ERRATA_A73_855423 |
Sona Mathew | 3b01893 | 2023-06-19 19:08:18 -0500 | [diff] [blame] | 46 | sysreg_bit_set CORTEX_A73_IMP_DEF_REG2, BIT(7) |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 47 | workaround_reset_end cortex_a73, ERRATUM(855423) |
Louis Mayencourt | 4405de6 | 2019-02-21 16:38:16 +0000 | [diff] [blame] | 48 | |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 49 | check_erratum_ls cortex_a73, ERRATUM(855423), CPU_REV(0, 1) |
Louis Mayencourt | 4405de6 | 2019-02-21 16:38:16 +0000 | [diff] [blame] | 50 | |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 51 | workaround_reset_start cortex_a73, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 |
| 52 | #if IMAGE_BL31 |
Sona Mathew | 3b01893 | 2023-06-19 19:08:18 -0500 | [diff] [blame] | 53 | override_vector_table wa_cve_2017_5715_bpiall_vbar |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 54 | #endif /* IMAGE_BL31 */ |
| 55 | workaround_reset_end cortex_a73, CVE(2017, 5715) |
| 56 | |
| 57 | check_erratum_custom_start cortex_a73, CVE(2017, 5715) |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 58 | cpu_check_csv2 x0, 1f |
| 59 | #if WORKAROUND_CVE_2017_5715 |
| 60 | mov x0, #ERRATA_APPLIES |
| 61 | #else |
| 62 | mov x0, #ERRATA_MISSING |
| 63 | #endif |
| 64 | ret |
| 65 | 1: |
| 66 | mov x0, #ERRATA_NOT_APPLIES |
| 67 | ret |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 68 | check_erratum_custom_end cortex_a73, CVE(2017, 5715) |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 69 | |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 70 | workaround_reset_start cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 |
Sona Mathew | 3b01893 | 2023-06-19 19:08:18 -0500 | [diff] [blame] | 71 | sysreg_bit_set CORTEX_A73_IMP_DEF_REG1, CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 72 | workaround_reset_end cortex_a73, CVE(2018, 3639) |
| 73 | |
| 74 | check_erratum_chosen cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 |
| 75 | |
| 76 | workaround_reset_start cortex_a73, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 77 | #if IMAGE_BL31 |
| 78 | /* Skip installing vector table again for CVE_2022_23960 */ |
Sona Mathew | 3b01893 | 2023-06-19 19:08:18 -0500 | [diff] [blame] | 79 | override_vector_table wa_cve_2017_5715_bpiall_vbar |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 80 | cmp x0, x1 |
| 81 | b.eq 1f |
| 82 | msr vbar_el3, x0 |
| 83 | 1: |
| 84 | #endif /* IMAGE_BL31 */ |
| 85 | workaround_reset_end cortex_a73, CVE(2022, 23960) |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 86 | |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 87 | check_erratum_custom_start cortex_a73, CVE(2022, 23960) |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 88 | #if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 89 | cpu_check_csv2 x0, 1f |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 90 | mov x0, #ERRATA_APPLIES |
| 91 | ret |
| 92 | 1: |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 93 | #if WORKAROUND_CVE_2022_23960 |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 94 | mov x0, #ERRATA_APPLIES |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 95 | #else |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 96 | mov x0, #ERRATA_MISSING |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 97 | #endif /* WORKAROUND_CVE_2022_23960 */ |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 98 | ret |
| 99 | #endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ |
| 100 | mov x0, #ERRATA_MISSING |
| 101 | ret |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 102 | check_erratum_custom_end cortex_a73, CVE(2022, 23960) |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 103 | |
Louis Mayencourt | 4405de6 | 2019-02-21 16:38:16 +0000 | [diff] [blame] | 104 | /* ------------------------------------------------- |
| 105 | * The CPU Ops reset function for Cortex-A73. |
| 106 | * ------------------------------------------------- |
| 107 | */ |
| 108 | |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 109 | cpu_reset_func_start cortex_a73 |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 110 | /* --------------------------------------------- |
| 111 | * Enable the SMP bit. |
| 112 | * Clobbers : x0 |
| 113 | * --------------------------------------------- |
| 114 | */ |
Sona Mathew | 3b01893 | 2023-06-19 19:08:18 -0500 | [diff] [blame] | 115 | sysreg_bit_set CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 116 | cpu_reset_func_end cortex_a73 |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 117 | |
| 118 | func cortex_a73_core_pwr_dwn |
| 119 | mov x18, x30 |
| 120 | |
| 121 | /* --------------------------------------------- |
| 122 | * Turn off caches. |
| 123 | * --------------------------------------------- |
| 124 | */ |
| 125 | bl cortex_a73_disable_dcache |
| 126 | |
| 127 | /* --------------------------------------------- |
| 128 | * Flush L1 caches. |
| 129 | * --------------------------------------------- |
| 130 | */ |
| 131 | mov x0, #DCCISW |
| 132 | bl dcsw_op_level1 |
| 133 | |
| 134 | /* --------------------------------------------- |
| 135 | * Come out of intra cluster coherency |
| 136 | * --------------------------------------------- |
| 137 | */ |
| 138 | mov x30, x18 |
| 139 | b cortex_a73_disable_smp |
| 140 | endfunc cortex_a73_core_pwr_dwn |
| 141 | |
| 142 | func cortex_a73_cluster_pwr_dwn |
| 143 | mov x18, x30 |
| 144 | |
| 145 | /* --------------------------------------------- |
| 146 | * Turn off caches. |
| 147 | * --------------------------------------------- |
| 148 | */ |
| 149 | bl cortex_a73_disable_dcache |
| 150 | |
| 151 | /* --------------------------------------------- |
| 152 | * Flush L1 caches. |
| 153 | * --------------------------------------------- |
| 154 | */ |
| 155 | mov x0, #DCCISW |
| 156 | bl dcsw_op_level1 |
| 157 | |
| 158 | /* --------------------------------------------- |
| 159 | * Disable the optional ACP. |
| 160 | * --------------------------------------------- |
| 161 | */ |
| 162 | bl plat_disable_acp |
| 163 | |
| 164 | /* --------------------------------------------- |
| 165 | * Flush L2 caches. |
| 166 | * --------------------------------------------- |
| 167 | */ |
| 168 | mov x0, #DCCISW |
| 169 | bl dcsw_op_level2 |
| 170 | |
| 171 | /* --------------------------------------------- |
| 172 | * Come out of intra cluster coherency |
| 173 | * --------------------------------------------- |
| 174 | */ |
| 175 | mov x30, x18 |
| 176 | b cortex_a73_disable_smp |
| 177 | endfunc cortex_a73_cluster_pwr_dwn |
| 178 | |
Bipin Ravi | caa2e05 | 2022-02-23 23:45:50 -0600 | [diff] [blame] | 179 | |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 180 | errata_report_shim cortex_a73 |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 181 | |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 182 | /* --------------------------------------------- |
| 183 | * This function provides cortex_a73 specific |
| 184 | * register information for crash reporting. |
| 185 | * It needs to return with x6 pointing to |
| 186 | * a list of register names in ascii and |
| 187 | * x8 - x15 having values of registers to be |
| 188 | * reported. |
| 189 | * --------------------------------------------- |
| 190 | */ |
| 191 | .section .rodata.cortex_a73_regs, "aS" |
| 192 | cortex_a73_regs: /* The ascii list of register names to be reported */ |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 193 | .asciz "cpuectlr_el1", "l2merrsr_el1", "" |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 194 | |
| 195 | func cortex_a73_cpu_reg_dump |
| 196 | adr x6, cortex_a73_regs |
| 197 | mrs x8, CORTEX_A73_CPUECTLR_EL1 |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 198 | mrs x9, CORTEX_A73_L2MERRSR_EL1 |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 199 | ret |
| 200 | endfunc cortex_a73_cpu_reg_dump |
| 201 | |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 202 | declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \ |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 203 | cortex_a73_reset_func, \ |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame] | 204 | check_erratum_cortex_a73_5715, \ |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 205 | CPU_NO_EXTRA2_FUNC, \ |
Bipin Ravi | caa2e05 | 2022-02-23 23:45:50 -0600 | [diff] [blame] | 206 | check_smccc_arch_workaround_3, \ |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 207 | cortex_a73_core_pwr_dwn, \ |
| 208 | cortex_a73_cluster_pwr_dwn |