blob: 38a375edff57b6d7a31ae34d25c5f2f3c92e2c36 [file] [log] [blame]
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +01001/*
Zelalem Aweke173c6a22021-07-08 17:23:04 -05002 * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +01007#include <assert.h>
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +01008#include <errno.h>
Javier Almansa Sobrino2a8af482021-11-25 09:29:27 +00009#include <inttypes.h>
Antonio Nino Diaz5c97bd12018-08-02 09:57:29 +010010#include <stdbool.h>
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010011#include <stdint.h>
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010012#include <stdio.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013
14#include <platform_def.h>
15
16#include <arch_helpers.h>
17#include <common/debug.h>
18#include <lib/utils_def.h>
19#include <lib/xlat_tables/xlat_tables_defs.h>
20#include <lib/xlat_tables/xlat_tables_v2.h>
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010021
22#include "xlat_tables_private.h"
23
24#if LOG_LEVEL < LOG_LEVEL_VERBOSE
25
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010026void xlat_mmap_print(__unused const mmap_region_t *mmap)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010027{
28 /* Empty */
29}
30
31void xlat_tables_print(__unused xlat_ctx_t *ctx)
32{
33 /* Empty */
34}
35
36#else /* if LOG_LEVEL >= LOG_LEVEL_VERBOSE */
37
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010038void xlat_mmap_print(const mmap_region_t *mmap)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010039{
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010040 printf("mmap:\n");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010041 const mmap_region_t *mm = mmap;
42
43 while (mm->size != 0U) {
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010044 printf(" VA:0x%lx PA:0x%llx size:0x%zx attr:0x%x granularity:0x%zx\n",
45 mm->base_va, mm->base_pa, mm->size, mm->attr,
46 mm->granularity);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010047 ++mm;
48 };
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010049 printf("\n");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010050}
51
52/* Print the attributes of the specified block descriptor. */
53static void xlat_desc_print(const xlat_ctx_t *ctx, uint64_t desc)
54{
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010055 uint64_t mem_type_index = ATTR_INDEX_GET(desc);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010056 int xlat_regime = ctx->xlat_regime;
57
58 if (mem_type_index == ATTR_IWBWA_OWBWA_NTR_INDEX) {
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010059 printf("MEM");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010060 } else if (mem_type_index == ATTR_NON_CACHEABLE_INDEX) {
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010061 printf("NC");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010062 } else {
63 assert(mem_type_index == ATTR_DEVICE_INDEX);
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010064 printf("DEV");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010065 }
66
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +010067 if ((xlat_regime == EL3_REGIME) || (xlat_regime == EL2_REGIME)) {
68 /* For EL3 and EL2 only check the AP[2] and XN bits. */
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010069 printf(((desc & LOWER_ATTRS(AP_RO)) != 0ULL) ? "-RO" : "-RW");
70 printf(((desc & UPPER_ATTRS(XN)) != 0ULL) ? "-XN" : "-EXEC");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010071 } else {
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010072 assert(xlat_regime == EL1_EL0_REGIME);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010073 /*
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010074 * For EL0 and EL1:
75 * - In AArch64 PXN and UXN can be set independently but in
76 * AArch32 there is no UXN (XN affects both privilege levels).
77 * For consistency, we set them simultaneously in both cases.
78 * - RO and RW permissions must be the same in EL1 and EL0. If
79 * EL0 can access that memory region, so can EL1, with the
80 * same permissions.
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010081 */
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010082#if ENABLE_ASSERTIONS
83 uint64_t xn_mask = xlat_arch_regime_get_xn_desc(EL1_EL0_REGIME);
84 uint64_t xn_perm = desc & xn_mask;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010085
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010086 assert((xn_perm == xn_mask) || (xn_perm == 0ULL));
87#endif
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010088 printf(((desc & LOWER_ATTRS(AP_RO)) != 0ULL) ? "-RO" : "-RW");
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010089 /* Only check one of PXN and UXN, the other one is the same. */
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010090 printf(((desc & UPPER_ATTRS(PXN)) != 0ULL) ? "-XN" : "-EXEC");
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010091 /*
92 * Privileged regions can only be accessed from EL1, user
93 * regions can be accessed from EL1 and EL0.
94 */
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010095 printf(((desc & LOWER_ATTRS(AP_ACCESS_UNPRIVILEGED)) != 0ULL)
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010096 ? "-USER" : "-PRIV");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010097 }
98
Zelalem Aweke173c6a22021-07-08 17:23:04 -050099#if ENABLE_RME
100 switch (desc & LOWER_ATTRS(EL3_S1_NSE | NS)) {
101 case 0ULL:
102 printf("-S");
103 break;
104 case LOWER_ATTRS(NS):
105 printf("-NS");
106 break;
107 case LOWER_ATTRS(EL3_S1_NSE):
108 printf("-RT");
109 break;
110 default: /* LOWER_ATTRS(EL3_S1_NSE | NS) */
111 printf("-RL");
112 }
113#else
Antonio Nino Diaz00086e32018-08-16 16:46:06 +0100114 printf(((LOWER_ATTRS(NS) & desc) != 0ULL) ? "-NS" : "-S");
Zelalem Aweke173c6a22021-07-08 17:23:04 -0500115#endif
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100116
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700117#ifdef __aarch64__
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100118 /* Check Guarded Page bit */
119 if ((desc & GP) != 0ULL) {
120 printf("-GP");
121 }
122#endif
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100123}
124
125static const char * const level_spacers[] = {
126 "[LV0] ",
127 " [LV1] ",
128 " [LV2] ",
129 " [LV3] "
130};
131
132static const char *invalid_descriptors_ommited =
133 "%s(%d invalid descriptors omitted)\n";
134
135/*
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000136 * Recursive function that reads the translation tables passed as an argument
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100137 * and prints their status.
138 */
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100139static void xlat_tables_print_internal(xlat_ctx_t *ctx, uintptr_t table_base_va,
140 const uint64_t *table_base, unsigned int table_entries,
141 unsigned int level)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100142{
143 assert(level <= XLAT_TABLE_LEVEL_MAX);
144
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000145 uint64_t desc;
David Pu36e27b82019-02-25 10:52:41 -0800146 uintptr_t table_idx_va = table_base_va;
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000147 unsigned int table_idx = 0U;
148 size_t level_size = XLAT_BLOCK_SIZE(level);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100149
150 /*
151 * Keep track of how many invalid descriptors are counted in a row.
152 * Whenever multiple invalid descriptors are found, only the first one
153 * is printed, and a line is added to inform about how many descriptors
154 * have been omitted.
155 */
156 int invalid_row_count = 0;
157
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000158 while (table_idx < table_entries) {
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100159
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000160 desc = table_base[table_idx];
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100161
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000162 if ((desc & DESC_MASK) == INVALID_DESC) {
163
164 if (invalid_row_count == 0) {
165 printf("%sVA:0x%lx size:0x%zx\n",
166 level_spacers[level],
167 table_idx_va, level_size);
David Pu36e27b82019-02-25 10:52:41 -0800168 }
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000169 invalid_row_count++;
170
David Pu36e27b82019-02-25 10:52:41 -0800171 } else {
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100172
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000173 if (invalid_row_count > 1) {
174 printf(invalid_descriptors_ommited,
175 level_spacers[level],
176 invalid_row_count - 1);
177 }
178 invalid_row_count = 0;
179
180 /*
181 * Check if this is a table or a block. Tables are only
182 * allowed in levels other than 3, but DESC_PAGE has the
183 * same value as DESC_TABLE, so we need to check.
184 */
185 if (((desc & DESC_MASK) == TABLE_DESC) &&
186 (level < XLAT_TABLE_LEVEL_MAX)) {
David Pu36e27b82019-02-25 10:52:41 -0800187 /*
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000188 * Do not print any PA for a table descriptor,
189 * as it doesn't directly map physical memory
190 * but instead points to the next translation
191 * table in the translation table walk.
David Pu36e27b82019-02-25 10:52:41 -0800192 */
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000193 printf("%sVA:0x%lx size:0x%zx\n",
194 level_spacers[level],
195 table_idx_va, level_size);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100196
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000197 uintptr_t addr_inner = desc & TABLE_ADDR_MASK;
David Pu36e27b82019-02-25 10:52:41 -0800198
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000199 xlat_tables_print_internal(ctx, table_idx_va,
200 (uint64_t *)addr_inner,
201 XLAT_TABLE_ENTRIES, level + 1U);
202 } else {
Javier Almansa Sobrino2a8af482021-11-25 09:29:27 +0000203 printf("%sVA:0x%lx PA:0x%" PRIx64 " size:0x%zx ",
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000204 level_spacers[level], table_idx_va,
205 (uint64_t)(desc & TABLE_ADDR_MASK),
206 level_size);
207 xlat_desc_print(ctx, desc);
208 printf("\n");
David Pu36e27b82019-02-25 10:52:41 -0800209 }
210 }
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000211
212 table_idx++;
213 table_idx_va += level_size;
214 }
215
216 if (invalid_row_count > 1) {
217 printf(invalid_descriptors_ommited,
218 level_spacers[level], invalid_row_count - 1);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100219 }
220}
221
222void xlat_tables_print(xlat_ctx_t *ctx)
223{
224 const char *xlat_regime_str;
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100225 int used_page_tables;
226
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100227 if (ctx->xlat_regime == EL1_EL0_REGIME) {
228 xlat_regime_str = "1&0";
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100229 } else if (ctx->xlat_regime == EL2_REGIME) {
230 xlat_regime_str = "2";
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100231 } else {
232 assert(ctx->xlat_regime == EL3_REGIME);
233 xlat_regime_str = "3";
234 }
235 VERBOSE("Translation tables state:\n");
236 VERBOSE(" Xlat regime: EL%s\n", xlat_regime_str);
237 VERBOSE(" Max allowed PA: 0x%llx\n", ctx->pa_max_address);
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100238 VERBOSE(" Max allowed VA: 0x%lx\n", ctx->va_max_address);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100239 VERBOSE(" Max mapped PA: 0x%llx\n", ctx->max_pa);
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100240 VERBOSE(" Max mapped VA: 0x%lx\n", ctx->max_va);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100241
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100242 VERBOSE(" Initial lookup level: %u\n", ctx->base_level);
243 VERBOSE(" Entries @initial lookup level: %u\n",
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100244 ctx->base_table_entries);
245
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100246#if PLAT_XLAT_TABLES_DYNAMIC
247 used_page_tables = 0;
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100248 for (int i = 0; i < ctx->tables_num; ++i) {
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100249 if (ctx->tables_mapped_regions[i] != 0)
250 ++used_page_tables;
251 }
252#else
253 used_page_tables = ctx->next_table;
254#endif
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100255 VERBOSE(" Used %d sub-tables out of %d (spare: %d)\n",
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100256 used_page_tables, ctx->tables_num,
257 ctx->tables_num - used_page_tables);
258
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100259 xlat_tables_print_internal(ctx, 0U, ctx->base_table,
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100260 ctx->base_table_entries, ctx->base_level);
261}
262
263#endif /* LOG_LEVEL >= LOG_LEVEL_VERBOSE */
264
265/*
266 * Do a translation table walk to find the block or page descriptor that maps
267 * virtual_addr.
268 *
269 * On success, return the address of the descriptor within the translation
270 * table. Its lookup level is stored in '*out_level'.
271 * On error, return NULL.
272 *
273 * xlat_table_base
274 * Base address for the initial lookup level.
275 * xlat_table_base_entries
276 * Number of entries in the translation table for the initial lookup level.
277 * virt_addr_space_size
278 * Size in bytes of the virtual address space.
279 */
280static uint64_t *find_xlat_table_entry(uintptr_t virtual_addr,
281 void *xlat_table_base,
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100282 unsigned int xlat_table_base_entries,
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100283 unsigned long long virt_addr_space_size,
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100284 unsigned int *out_level)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100285{
286 unsigned int start_level;
287 uint64_t *table;
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100288 unsigned int entries;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100289
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100290 start_level = GET_XLAT_TABLE_LEVEL_BASE(virt_addr_space_size);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100291
292 table = xlat_table_base;
293 entries = xlat_table_base_entries;
294
295 for (unsigned int level = start_level;
296 level <= XLAT_TABLE_LEVEL_MAX;
297 ++level) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100298 uint64_t idx, desc, desc_type;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100299
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100300 idx = XLAT_TABLE_IDX(virtual_addr, level);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100301 if (idx >= entries) {
Antonio Nino Diazbd0aff62018-07-02 09:26:51 +0100302 WARN("Missing xlat table entry at address 0x%lx\n",
303 virtual_addr);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100304 return NULL;
305 }
306
307 desc = table[idx];
308 desc_type = desc & DESC_MASK;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100309
310 if (desc_type == INVALID_DESC) {
311 VERBOSE("Invalid entry (memory not mapped)\n");
312 return NULL;
313 }
314
315 if (level == XLAT_TABLE_LEVEL_MAX) {
316 /*
Antonio Nino Diazbd0aff62018-07-02 09:26:51 +0100317 * Only page descriptors allowed at the final lookup
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100318 * level.
319 */
320 assert(desc_type == PAGE_DESC);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100321 *out_level = level;
322 return &table[idx];
323 }
324
325 if (desc_type == BLOCK_DESC) {
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100326 *out_level = level;
327 return &table[idx];
328 }
329
330 assert(desc_type == TABLE_DESC);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100331 table = (uint64_t *)(uintptr_t)(desc & TABLE_ADDR_MASK);
332 entries = XLAT_TABLE_ENTRIES;
333 }
334
335 /*
336 * This shouldn't be reached, the translation table walk should end at
337 * most at level XLAT_TABLE_LEVEL_MAX and return from inside the loop.
338 */
Antonio Nino Diaz5c97bd12018-08-02 09:57:29 +0100339 assert(false);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100340
341 return NULL;
342}
343
344
Antonio Nino Diaz6c4c9ee2018-08-05 15:34:10 +0100345static int xlat_get_mem_attributes_internal(const xlat_ctx_t *ctx,
346 uintptr_t base_va, uint32_t *attributes, uint64_t **table_entry,
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100347 unsigned long long *addr_pa, unsigned int *table_level)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100348{
349 uint64_t *entry;
350 uint64_t desc;
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100351 unsigned int level;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100352 unsigned long long virt_addr_space_size;
353
354 /*
355 * Sanity-check arguments.
356 */
357 assert(ctx != NULL);
Antonio Nino Diaz5c97bd12018-08-02 09:57:29 +0100358 assert(ctx->initialized);
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100359 assert((ctx->xlat_regime == EL1_EL0_REGIME) ||
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100360 (ctx->xlat_regime == EL2_REGIME) ||
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100361 (ctx->xlat_regime == EL3_REGIME));
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100362
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100363 virt_addr_space_size = (unsigned long long)ctx->va_max_address + 1ULL;
364 assert(virt_addr_space_size > 0U);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100365
366 entry = find_xlat_table_entry(base_va,
367 ctx->base_table,
368 ctx->base_table_entries,
369 virt_addr_space_size,
370 &level);
371 if (entry == NULL) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100372 WARN("Address 0x%lx is not mapped.\n", base_va);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100373 return -EINVAL;
374 }
375
376 if (addr_pa != NULL) {
377 *addr_pa = *entry & TABLE_ADDR_MASK;
378 }
379
380 if (table_entry != NULL) {
381 *table_entry = entry;
382 }
383
384 if (table_level != NULL) {
385 *table_level = level;
386 }
387
388 desc = *entry;
389
390#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
391 VERBOSE("Attributes: ");
392 xlat_desc_print(ctx, desc);
Antonio Nino Diaz00086e32018-08-16 16:46:06 +0100393 printf("\n");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100394#endif /* LOG_LEVEL >= LOG_LEVEL_VERBOSE */
395
396 assert(attributes != NULL);
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100397 *attributes = 0U;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100398
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100399 uint64_t attr_index = (desc >> ATTR_INDEX_SHIFT) & ATTR_INDEX_MASK;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100400
401 if (attr_index == ATTR_IWBWA_OWBWA_NTR_INDEX) {
402 *attributes |= MT_MEMORY;
403 } else if (attr_index == ATTR_NON_CACHEABLE_INDEX) {
404 *attributes |= MT_NON_CACHEABLE;
405 } else {
406 assert(attr_index == ATTR_DEVICE_INDEX);
407 *attributes |= MT_DEVICE;
408 }
409
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100410 uint64_t ap2_bit = (desc >> AP2_SHIFT) & 1U;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100411
412 if (ap2_bit == AP2_RW)
413 *attributes |= MT_RW;
414
415 if (ctx->xlat_regime == EL1_EL0_REGIME) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100416 uint64_t ap1_bit = (desc >> AP1_SHIFT) & 1U;
417
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100418 if (ap1_bit == AP1_ACCESS_UNPRIVILEGED)
419 *attributes |= MT_USER;
420 }
421
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100422 uint64_t ns_bit = (desc >> NS_SHIFT) & 1U;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100423
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100424 if (ns_bit == 1U)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100425 *attributes |= MT_NS;
426
427 uint64_t xn_mask = xlat_arch_regime_get_xn_desc(ctx->xlat_regime);
428
429 if ((desc & xn_mask) == xn_mask) {
430 *attributes |= MT_EXECUTE_NEVER;
431 } else {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100432 assert((desc & xn_mask) == 0U);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100433 }
434
435 return 0;
436}
437
438
Antonio Nino Diaz6c4c9ee2018-08-05 15:34:10 +0100439int xlat_get_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va,
440 uint32_t *attr)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100441{
Antonio Nino Diaz6c4c9ee2018-08-05 15:34:10 +0100442 return xlat_get_mem_attributes_internal(ctx, base_va, attr,
443 NULL, NULL, NULL);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100444}
445
446
Antonio Nino Diaz6c4c9ee2018-08-05 15:34:10 +0100447int xlat_change_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va,
448 size_t size, uint32_t attr)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100449{
450 /* Note: This implementation isn't optimized. */
451
452 assert(ctx != NULL);
Antonio Nino Diaz5c97bd12018-08-02 09:57:29 +0100453 assert(ctx->initialized);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100454
455 unsigned long long virt_addr_space_size =
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100456 (unsigned long long)ctx->va_max_address + 1U;
457 assert(virt_addr_space_size > 0U);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100458
459 if (!IS_PAGE_ALIGNED(base_va)) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100460 WARN("%s: Address 0x%lx is not aligned on a page boundary.\n",
461 __func__, base_va);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100462 return -EINVAL;
463 }
464
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100465 if (size == 0U) {
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100466 WARN("%s: Size is 0.\n", __func__);
467 return -EINVAL;
468 }
469
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100470 if ((size % PAGE_SIZE) != 0U) {
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100471 WARN("%s: Size 0x%zx is not a multiple of a page size.\n",
472 __func__, size);
473 return -EINVAL;
474 }
475
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100476 if (((attr & MT_EXECUTE_NEVER) == 0U) && ((attr & MT_RW) != 0U)) {
Antonio Nino Diazbd0aff62018-07-02 09:26:51 +0100477 WARN("%s: Mapping memory as read-write and executable not allowed.\n",
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100478 __func__);
479 return -EINVAL;
480 }
481
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100482 size_t pages_count = size / PAGE_SIZE;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100483
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100484 VERBOSE("Changing memory attributes of %zu pages starting from address 0x%lx...\n",
485 pages_count, base_va);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100486
487 uintptr_t base_va_original = base_va;
488
489 /*
490 * Sanity checks.
491 */
Jimmy Brissoned202072020-08-04 16:18:52 -0500492 for (unsigned int i = 0U; i < pages_count; ++i) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100493 const uint64_t *entry;
494 uint64_t desc, attr_index;
495 unsigned int level;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100496
497 entry = find_xlat_table_entry(base_va,
498 ctx->base_table,
499 ctx->base_table_entries,
500 virt_addr_space_size,
501 &level);
502 if (entry == NULL) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100503 WARN("Address 0x%lx is not mapped.\n", base_va);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100504 return -EINVAL;
505 }
506
507 desc = *entry;
508
509 /*
510 * Check that all the required pages are mapped at page
511 * granularity.
512 */
513 if (((desc & DESC_MASK) != PAGE_DESC) ||
514 (level != XLAT_TABLE_LEVEL_MAX)) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100515 WARN("Address 0x%lx is not mapped at the right granularity.\n",
516 base_va);
Jimmy Brissoned202072020-08-04 16:18:52 -0500517 WARN("Granularity is 0x%lx, should be 0x%lx.\n",
518 XLAT_BLOCK_SIZE(level), PAGE_SIZE);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100519 return -EINVAL;
520 }
521
522 /*
523 * If the region type is device, it shouldn't be executable.
524 */
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100525 attr_index = (desc >> ATTR_INDEX_SHIFT) & ATTR_INDEX_MASK;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100526 if (attr_index == ATTR_DEVICE_INDEX) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100527 if ((attr & MT_EXECUTE_NEVER) == 0U) {
528 WARN("Setting device memory as executable at address 0x%lx.",
529 base_va);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100530 return -EINVAL;
531 }
532 }
533
534 base_va += PAGE_SIZE;
535 }
536
537 /* Restore original value. */
538 base_va = base_va_original;
539
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100540 for (unsigned int i = 0U; i < pages_count; ++i) {
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100541
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100542 uint32_t old_attr = 0U, new_attr;
543 uint64_t *entry = NULL;
544 unsigned int level = 0U;
545 unsigned long long addr_pa = 0ULL;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100546
Antonio Nino Diaz6c4c9ee2018-08-05 15:34:10 +0100547 (void) xlat_get_mem_attributes_internal(ctx, base_va, &old_attr,
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100548 &entry, &addr_pa, &level);
549
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100550 /*
551 * From attr, only MT_RO/MT_RW, MT_EXECUTE/MT_EXECUTE_NEVER and
552 * MT_USER/MT_PRIVILEGED are taken into account. Any other
553 * information is ignored.
554 */
555
556 /* Clean the old attributes so that they can be rebuilt. */
Antonio Nino Diazbd0aff62018-07-02 09:26:51 +0100557 new_attr = old_attr & ~(MT_RW | MT_EXECUTE_NEVER | MT_USER);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100558
559 /*
560 * Update attributes, but filter out the ones this function
561 * isn't allowed to change.
562 */
Antonio Nino Diazbd0aff62018-07-02 09:26:51 +0100563 new_attr |= attr & (MT_RW | MT_EXECUTE_NEVER | MT_USER);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100564
565 /*
566 * The break-before-make sequence requires writing an invalid
567 * descriptor and making sure that the system sees the change
568 * before writing the new descriptor.
569 */
570 *entry = INVALID_DESC;
Artsem Artsemenkabce728f2019-10-17 13:51:27 +0100571#if !HW_ASSISTED_COHERENCY
Antonio Nino Diaz37a5efa2018-08-07 12:47:12 +0100572 dccvac((uintptr_t)entry);
573#endif
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100574 /* Invalidate any cached copy of this mapping in the TLBs. */
Antonio Nino Diazad5dc7f2018-07-11 09:46:45 +0100575 xlat_arch_tlbi_va(base_va, ctx->xlat_regime);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100576
577 /* Ensure completion of the invalidation. */
578 xlat_arch_tlbi_va_sync();
579
580 /* Write new descriptor */
581 *entry = xlat_desc(ctx, new_attr, addr_pa, level);
Artsem Artsemenkabce728f2019-10-17 13:51:27 +0100582#if !HW_ASSISTED_COHERENCY
Antonio Nino Diaz37a5efa2018-08-07 12:47:12 +0100583 dccvac((uintptr_t)entry);
584#endif
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100585 base_va += PAGE_SIZE;
586 }
587
588 /* Ensure that the last descriptor writen is seen by the system. */
589 dsbish();
590
591 return 0;
592}