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Sughosh Ganu18f513d2018-05-16 17:22:35 +05301/*
Paul Beesleye9754e62019-10-15 12:51:55 +00002 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Sughosh Ganu18f513d2018-05-16 17:22:35 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Sughosh Ganu18f513d2018-05-16 17:22:35 +05307#include <assert.h>
Sughosh Ganu18f513d2018-05-16 17:22:35 +05308#include <string.h>
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <bl31/interrupt_mgmt.h>
11#include <lib/el3_runtime/context_mgmt.h>
12#include <lib/extensions/ras.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000013#include <plat/arm/common/arm_spm_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <plat/common/platform.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <services/sdei.h>
Paul Beesleye9754e62019-10-15 12:51:55 +000016#include <services/spm_mm_svc.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000018#include <sgi_ras.h>
19
Sughosh Ganu18f513d2018-05-16 17:22:35 +053020static int sgi_ras_intr_handler(const struct err_record_info *err_rec,
21 int probe_data,
22 const struct err_handler_data *const data);
23struct efi_guid {
24 uint32_t data1;
25 uint16_t data2;
26 uint16_t data3;
27 uint8_t data4[8];
28};
29
30typedef struct mm_communicate_header {
31 struct efi_guid header_guid;
32 size_t message_len;
33 uint8_t data[8];
34} mm_communicate_header_t;
35
Sughosh Ganu70661cf2018-05-16 17:26:40 +053036struct sgi_ras_ev_map sgi575_ras_map[] = {
37
38 /* DMC620 error overflow interrupt*/
39 {SP_DMC_ERROR_OVERFLOW_EVENT_AARCH64, SGI_SDEI_DS_EVENT_1, 33},
40
41 /* DMC620 error ECC error interrupt*/
42 {SP_DMC_ERROR_ECC_EVENT_AARCH64, SGI_SDEI_DS_EVENT_0, 35},
43};
44
45#define SGI575_RAS_MAP_SIZE ARRAY_SIZE(sgi575_ras_map)
46
47struct err_record_info sgi_err_records[] = {
48 {
49 .handler = &sgi_ras_intr_handler,
50 },
51};
52
53struct ras_interrupt sgi_ras_interrupts[] = {
54 {
55 .intr_number = 33,
56 .err_record = &sgi_err_records[0],
57 },
58 {
59 .intr_number = 35,
60 .err_record = &sgi_err_records[0],
61 }
62};
63
64REGISTER_ERR_RECORD_INFO(sgi_err_records);
65REGISTER_RAS_INTERRUPTS(sgi_ras_interrupts);
66
67static struct sgi_ras_ev_map *plat_sgi_get_ras_ev_map(void)
68{
69 return sgi575_ras_map;
70}
71
72static int plat_sgi_get_ras_ev_map_size(void)
73{
74 return SGI575_RAS_MAP_SIZE;
75}
76
Sughosh Ganu18f513d2018-05-16 17:22:35 +053077/*
78 * Find event mapping for a given interrupt number: On success, returns pointer
79 * to the event mapping. On error, returns NULL.
80 */
81static struct sgi_ras_ev_map *find_ras_event_map_by_intr(uint32_t intr_num)
82{
83 struct sgi_ras_ev_map *map = plat_sgi_get_ras_ev_map();
84 int i;
85 int size = plat_sgi_get_ras_ev_map_size();
86
87 for (i = 0; i < size; i++) {
88 if (map->intr == intr_num)
89 return map;
90
91 map++;
92 }
93
94 return NULL;
95}
96
97static void sgi_ras_intr_configure(int intr)
98{
99 plat_ic_set_interrupt_type(intr, INTR_TYPE_EL3);
100 plat_ic_set_interrupt_priority(intr, PLAT_RAS_PRI);
101 plat_ic_clear_interrupt_pending(intr);
102 plat_ic_set_spi_routing(intr, INTR_ROUTING_MODE_ANY,
103 (u_register_t)read_mpidr_el1());
104 plat_ic_enable_interrupt(intr);
105}
106
107static int sgi_ras_intr_handler(const struct err_record_info *err_rec,
108 int probe_data,
109 const struct err_handler_data *const data)
110{
111 struct sgi_ras_ev_map *ras_map;
112 mm_communicate_header_t *header;
113 uint32_t intr;
114
115 cm_el1_sysregs_context_save(NON_SECURE);
116 intr = data->interrupt;
117
118 /*
119 * Find if this is a RAS interrupt. There must be an event against
120 * this interrupt
121 */
122 ras_map = find_ras_event_map_by_intr(intr);
123 assert(ras_map);
124
125 /*
126 * Populate the MM_COMMUNICATE payload to share the
127 * event info with StandaloneMM code. This allows us to use
128 * MM_COMMUNICATE as a common entry mechanism into S-EL0. The
129 * header data will be parsed in StandaloneMM to process the
130 * corresponding event.
131 *
132 * TBD - Currently, the buffer allocated by SPM for communication
133 * between EL3 and S-EL0 is being used(PLAT_SPM_BUF_BASE). But this
134 * should happen via a dynamic mem allocation, which should be
135 * managed by SPM -- the individual platforms then call the mem
136 * alloc api to get memory for the payload.
137 */
138 header = (void *) PLAT_SPM_BUF_BASE;
139 memset(header, 0, sizeof(*header));
140 memcpy(&header->data, &ras_map->ras_ev_num,
141 sizeof(ras_map->ras_ev_num));
142 header->message_len = 4;
143
Paul Beesleye9754e62019-10-15 12:51:55 +0000144 spm_mm_sp_call(MM_COMMUNICATE_AARCH64, (uint64_t)header, 0,
145 plat_my_core_pos());
Sughosh Ganu18f513d2018-05-16 17:22:35 +0530146
147 /*
Paul Beesleye9754e62019-10-15 12:51:55 +0000148 * Do an EOI of the RAS interrupt. This allows the
Sughosh Ganu18f513d2018-05-16 17:22:35 +0530149 * sdei event to be dispatched at the SDEI event's
150 * priority.
151 */
152 plat_ic_end_of_interrupt(intr);
153
154 /* Dispatch the event to the SDEI client */
155 sdei_dispatch_event(ras_map->sdei_ev_num);
156
157 return 0;
158}
159
160int sgi_ras_intr_handler_setup(void)
161{
162 int i;
163 struct sgi_ras_ev_map *map = plat_sgi_get_ras_ev_map();
164 int size = plat_sgi_get_ras_ev_map_size();
165
166 for (i = 0; i < size; i++) {
167 sgi_ras_intr_configure(map->intr);
168 map++;
169 }
170
171 INFO("SGI: RAS Interrupt Handler successfully registered\n");
172
173 return 0;
174}