blob: 0de094a4c94a1bad7ee6b09d27fa9f7425c42197 [file] [log] [blame]
Varun Wadekar28463b92015-07-14 17:11:20 +05301/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __DENVER_H__
32#define __DENVER_H__
33
Varun Wadekar3c337a62015-09-03 17:15:06 +053034/* MIDR values for Denver */
35#define DENVER_MIDR_PN0 0x4E0F0000
36#define DENVER_MIDR_PN1 0x4E0F0010
37#define DENVER_MIDR_PN2 0x4E0F0020
38#define DENVER_MIDR_PN3 0x4E0F0030
39#define DENVER_MIDR_PN4 0x4E0F0040
40
41/* Implementer code in the MIDR register */
42#define DENVER_IMPL 0x4E
Varun Wadekar28463b92015-07-14 17:11:20 +053043
44/* CPU state ids - implementation defined */
45#define DENVER_CPU_STATE_POWER_DOWN 0x3
46
47#endif /* __DENVER_H__ */