Konstantin Porotchkin | e7be6e2 | 2018-10-08 16:53:09 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2018 Marvell International Ltd. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * https://spdx.org/licenses |
| 6 | */ |
| 7 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | #include <lib/mmio.h> |
| 9 | |
Konstantin Porotchkin | e7be6e2 | 2018-10-08 16:53:09 +0300 | [diff] [blame] | 10 | #include <armada_common.h> |
| 11 | #include <dram_win.h> |
| 12 | #include <io_addr_dec.h> |
Konstantin Porotchkin | e7be6e2 | 2018-10-08 16:53:09 +0300 | [diff] [blame] | 13 | #include <marvell_plat_priv.h> |
| 14 | #include <plat_marvell.h> |
| 15 | |
| 16 | /* This routine does MPP initialization */ |
| 17 | static void marvell_bl31_mpp_init(void) |
| 18 | { |
| 19 | mmio_clrbits_32(MVEBU_NB_GPIO_SEL_REG, 1 << MVEBU_GPIO_TW1_GPIO_EN_OFF); |
| 20 | |
| 21 | /* Set hidden GPIO setting for SPI. |
| 22 | * In north_bridge_pin_out_en_high register 13804, |
| 23 | * bit 28 is the one which enables CS, CLK pins to be |
| 24 | * output, need to set it to 1. |
| 25 | * The initial value of this bit is 1, but in UART boot mode |
| 26 | * initialization, this bit is disabled and the SPI CS and CLK pins |
| 27 | * are used for downloading image purpose; so after downloading, |
| 28 | * we should set this bit to 1 again to enable SPI CS and CLK pins. |
| 29 | * And anyway, this bit value should be 1 in all modes, |
| 30 | * so here we does not judge boot mode and set this bit to 1 always. |
| 31 | */ |
| 32 | mmio_setbits_32(MVEBU_NB_GPIO_OUTPUT_EN_HIGH_REG, |
| 33 | 1 << MVEBU_GPIO_NB_SPI_PIN_MODE_OFF); |
| 34 | } |
| 35 | |
| 36 | /* This function overruns the same function in marvell_bl31_setup.c */ |
| 37 | void bl31_plat_arch_setup(void) |
| 38 | { |
| 39 | struct dec_win_config *io_dec_map; |
| 40 | uint32_t dec_win_num; |
| 41 | struct dram_win_map dram_wins_map; |
| 42 | |
| 43 | marvell_bl31_plat_arch_setup(); |
| 44 | |
| 45 | /* MPP init */ |
| 46 | marvell_bl31_mpp_init(); |
| 47 | |
| 48 | /* initialize the timer for delay functionality */ |
| 49 | plat_delay_timer_init(); |
| 50 | |
| 51 | /* CPU address decoder windows initialization. */ |
| 52 | cpu_wins_init(); |
| 53 | |
| 54 | /* fetch CPU-DRAM window mapping information by reading |
| 55 | * CPU-DRAM decode windows (only the enabled ones) |
| 56 | */ |
| 57 | dram_win_map_build(&dram_wins_map); |
| 58 | |
| 59 | /* Get IO address decoder windows */ |
| 60 | if (marvell_get_io_dec_win_conf(&io_dec_map, &dec_win_num)) { |
| 61 | printf("No IO address decoder windows configurations found!\n"); |
| 62 | return; |
| 63 | } |
| 64 | |
| 65 | /* IO address decoder init */ |
| 66 | if (init_io_addr_dec(&dram_wins_map, io_dec_map, dec_win_num)) { |
| 67 | printf("IO address decoder windows initialization failed!\n"); |
| 68 | return; |
| 69 | } |
| 70 | } |