blob: 2f41e2e723ef9eb109ada169624906a246e3ebf6 [file] [log] [blame]
Aditya Angadicdd7f632020-04-06 17:11:23 +05301# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
2#
3# SPDX-License-Identifier: BSD-3-Clause
4#
5
6# Enable GICv4 extension with multichip driver
7GIC_ENABLE_V4_EXTN := 1
8GICV3_IMPL_GIC600_MULTICHIP := 1
9
10include plat/arm/css/sgi/sgi-common.mk
11
12RDDANIELXLR_BASE = plat/arm/board/rddanielxlr
13
14PLAT_INCLUDES += -I${RDDANIELXLR_BASE}/include/
15
Jimmy Brisson958a0b12020-09-30 15:28:03 -050016SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_v1.S
Aditya Angadicdd7f632020-04-06 17:11:23 +053017
Aditya Angadi502d0ac2020-11-18 08:27:15 +053018PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c
19
Aditya Angadicdd7f632020-04-06 17:11:23 +053020BL1_SOURCES += ${SGI_CPU_SOURCES} \
21 ${RDDANIELXLR_BASE}/rddanielxlr_err.c
22
23BL2_SOURCES += ${RDDANIELXLR_BASE}/rddanielxlr_plat.c \
24 ${RDDANIELXLR_BASE}/rddanielxlr_security.c \
25 ${RDDANIELXLR_BASE}/rddanielxlr_err.c \
26 lib/utils/mem_region.c \
27 plat/arm/common/arm_nor_psci_mem_protect.c
28
29BL31_SOURCES += ${SGI_CPU_SOURCES} \
30 ${RDDANIELXLR_BASE}/rddanielxlr_plat.c \
31 ${RDDANIELXLR_BASE}/rddanielxlr_topology.c \
32 drivers/cfi/v2m/v2m_flash.c \
33 drivers/arm/gic/v3/gic600_multichip.c \
34 lib/utils/mem_region.c \
35 plat/arm/common/arm_nor_psci_mem_protect.c
36
Vijayenthiran Subramaniam01ce6fe2020-07-14 15:51:37 +053037ifeq (${TRUSTED_BOARD_BOOT}, 1)
38BL1_SOURCES += ${RDDANIELXLR_BASE}/rddanielxlr_trusted_boot.c
39BL2_SOURCES += ${RDDANIELXLR_BASE}/rddanielxlr_trusted_boot.c
40endif
41
Aditya Angadicdd7f632020-04-06 17:11:23 +053042# Enable dynamic addition of MMAP regions in BL31
43BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
44
45# Add the FDT_SOURCES and options for Dynamic Config
Manish V Badarkhe64616a52020-05-31 08:53:40 +010046FDT_SOURCES += ${RDDANIELXLR_BASE}/fdts/${PLAT}_fw_config.dts \
47 ${RDDANIELXLR_BASE}/fdts/${PLAT}_tb_fw_config.dts
48FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
49TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
Aditya Angadicdd7f632020-04-06 17:11:23 +053050
Manish V Badarkhe64616a52020-05-31 08:53:40 +010051# Add the FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +010052$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
Aditya Angadicdd7f632020-04-06 17:11:23 +053053# Add the TB_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +010054$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
Aditya Angadicdd7f632020-04-06 17:11:23 +053055
56$(eval $(call CREATE_SEQ,SEQ,4))
57ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),$(SEQ)))
58 $(error "Chip count for RD-Daniel Config-XLR should be either $(SEQ) \
59 currently it is set to ${CSS_SGI_CHIP_COUNT}.")
60endif
61
62FDT_SOURCES += ${RDDANIELXLR_BASE}/fdts/${PLAT}_nt_fw_config.dts
63NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
64
65# Add the NT_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +010066$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
Aditya Angadicdd7f632020-04-06 17:11:23 +053067
68override CTX_INCLUDE_AARCH32_REGS := 0