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Soby Mathew7c6df5b2018-01-15 14:43:42 +00001/*
Achin Guptada6ef0e2019-10-11 14:54:48 +01002 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
Soby Mathew7c6df5b2018-01-15 14:43:42 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <string.h>
Louis Mayencourt73d42d72019-12-09 11:29:38 +00009#include <libfdt.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
11#include <platform_def.h>
12
13#include <common/debug.h>
14#include <common/desc_image_load.h>
15#include <common/tbbr/tbbr_img_def.h>
John Tsichritzisc34341a2018-07-30 13:41:52 +010016#if TRUSTED_BOARD_BOOT
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <drivers/auth/mbedtls/mbedtls_config.h>
Alexei Fedorov25d7c882020-03-20 18:38:55 +000018#if MEASURED_BOOT
19#include <drivers/auth/crypto_mod.h>
20#include <mbedtls/md.h>
21#endif
John Tsichritzisc34341a2018-07-30 13:41:52 +010022#endif
Louis Mayencourt6d2b5732019-12-17 13:17:25 +000023#include <lib/fconf/fconf.h>
24#include <lib/fconf/fconf_dyn_cfg_getter.h>
Louis Mayencourt5b9055f2019-10-01 10:45:14 +010025#include <lib/fconf/fconf_tbbr_getter.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000026#include <plat/arm/common/arm_dyn_cfg_helpers.h>
27#include <plat/arm/common/plat_arm.h>
Soby Mathew7c6df5b2018-01-15 14:43:42 +000028
John Tsichritzisc34341a2018-07-30 13:41:52 +010029#if TRUSTED_BOARD_BOOT
30
31static void *mbedtls_heap_addr;
32static size_t mbedtls_heap_size;
33
34/*
35 * This function is the implementation of the shared Mbed TLS heap between
36 * BL1 and BL2 for Arm platforms. The shared heap address is passed from BL1
37 * to BL2 with a pointer. This pointer resides inside the TB_FW_CONFIG file
38 * which is a DTB.
39 *
40 * This function is placed inside an #if directive for the below reasons:
41 * - To allocate space for the Mbed TLS heap --only if-- Trusted Board Boot
42 * is enabled.
43 * - This implementation requires the DTB to be present so that BL1 has a
Antonio Nino Diaz05f49572018-09-25 11:37:23 +010044 * mechanism to pass the pointer to BL2.
John Tsichritzisc34341a2018-07-30 13:41:52 +010045 */
46int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
47{
48 assert(heap_addr != NULL);
49 assert(heap_size != NULL);
50
51#if defined(IMAGE_BL1) || BL2_AT_EL3
52
53 /* If in BL1 or BL2_AT_EL3 define a heap */
54 static unsigned char heap[TF_MBEDTLS_HEAP_SIZE];
55
56 *heap_addr = heap;
57 *heap_size = sizeof(heap);
58 mbedtls_heap_addr = heap;
59 mbedtls_heap_size = sizeof(heap);
60
61#elif defined(IMAGE_BL2)
62
John Tsichritzisc34341a2018-07-30 13:41:52 +010063 /* If in BL2, retrieve the already allocated heap's info from DTB */
Louis Mayencourt5b9055f2019-10-01 10:45:14 +010064 *heap_addr = FCONF_GET_PROPERTY(tbbr, dyn_config, mbedtls_heap_addr);
65 *heap_size = FCONF_GET_PROPERTY(tbbr, dyn_config, mbedtls_heap_size);
66
John Tsichritzisc34341a2018-07-30 13:41:52 +010067#endif
68
69 return 0;
70}
71
72/*
73 * Puts the shared Mbed TLS heap information to the DTB.
74 * Executed only from BL1.
75 */
76void arm_bl1_set_mbedtls_heap(void)
77{
78 int err;
Louis Mayencourt6d2b5732019-12-17 13:17:25 +000079 uintptr_t tb_fw_cfg_dtb;
John Tsichritzisc34341a2018-07-30 13:41:52 +010080
81 /*
82 * If tb_fw_cfg_dtb==NULL then DTB is not present for the current
83 * platform. As such, we don't attempt to write to the DTB at all.
84 *
85 * If mbedtls_heap_addr==NULL, then it means we are using the default
86 * heap implementation. As such, BL2 will have its own heap for sure
87 * and hence there is no need to pass any information to the DTB.
88 *
89 * In the latter case, if we still wanted to write in the DTB the heap
90 * information, we would need to call plat_get_mbedtls_heap to retrieve
91 * the default heap's address and size.
92 */
Louis Mayencourt6d2b5732019-12-17 13:17:25 +000093
Alexei Fedorov25d7c882020-03-20 18:38:55 +000094 /* fconf FW_CONFIG and TB_FW_CONFIG are currently the same DTB */
Louis Mayencourt6d2b5732019-12-17 13:17:25 +000095 tb_fw_cfg_dtb = FCONF_GET_PROPERTY(fconf, dtb, base_addr);
96
97 if ((tb_fw_cfg_dtb != 0UL) && (mbedtls_heap_addr != NULL)) {
98 /* As libfdt use void *, we can't avoid this cast */
99 void *dtb = (void *)tb_fw_cfg_dtb;
100
101 err = arm_set_dtb_mbedtls_heap_info(dtb,
John Tsichritzisc34341a2018-07-30 13:41:52 +0100102 mbedtls_heap_addr, mbedtls_heap_size);
103 if (err < 0) {
John Tsichritzis36507682018-09-07 10:42:37 +0100104 ERROR("BL1: unable to write shared Mbed TLS heap information to DTB\n");
John Tsichritzisc34341a2018-07-30 13:41:52 +0100105 panic();
106 }
Alexei Fedorov25d7c882020-03-20 18:38:55 +0000107#if !MEASURED_BOOT
John Tsichritzis03459c22018-09-07 10:52:12 +0100108 /*
109 * Ensure that the info written to the DTB is visible to other
110 * images. It's critical because BL2 won't be able to proceed
111 * without the heap info.
Alexei Fedorov25d7c882020-03-20 18:38:55 +0000112 *
113 * In MEASURED_BOOT case flushing is done in
114 * arm_bl1_set_bl2_hash() function which is called after heap
115 * information is written in the DTB.
John Tsichritzis03459c22018-09-07 10:52:12 +0100116 */
Louis Mayencourt6d2b5732019-12-17 13:17:25 +0000117 flush_dcache_range(tb_fw_cfg_dtb, fdt_totalsize(dtb));
Alexei Fedorov25d7c882020-03-20 18:38:55 +0000118#endif /* !MEASURED_BOOT */
John Tsichritzisc34341a2018-07-30 13:41:52 +0100119 }
120}
121
Alexei Fedorov25d7c882020-03-20 18:38:55 +0000122#if MEASURED_BOOT
123/*
124 * Puts the BL2 hash data to TB_FW_CONFIG DTB.
125 * Executed only from BL1.
126 */
127void arm_bl1_set_bl2_hash(image_desc_t *image_desc)
128{
129 unsigned char hash_data[MBEDTLS_MD_MAX_SIZE];
130 image_info_t image_info = image_desc->image_info;
131 uintptr_t tb_fw_cfg_dtb;
132 int err;
133
134 /* fconf FW_CONFIG and TB_FW_CONFIG are currently the same DTB */
135 tb_fw_cfg_dtb = FCONF_GET_PROPERTY(fconf, dtb, base_addr);
136
137 /*
138 * If tb_fw_cfg_dtb==NULL then DTB is not present for the current
139 * platform. As such, we cannot write to the DTB at all and pass
140 * measured data.
141 */
142 if (tb_fw_cfg_dtb == 0UL) {
143 panic();
144 }
145
146 /* Calculate hash */
147 err = crypto_mod_calc_hash(MBEDTLS_MD_ID,
148 (void *)image_info.image_base,
149 image_info.image_size, hash_data);
150 if (err != 0) {
151 ERROR("BL1: unable to calculate BL2 hash\n");
152 panic();
153 }
154
155 err = arm_set_bl2_hash_info((void *)tb_fw_cfg_dtb, hash_data);
156 if (err < 0) {
157 ERROR("BL1: unable to write BL2 hash data to DTB\n");
158 panic();
159 }
160
161 /*
162 * Ensure that the info written to the DTB is visible to other
163 * images. It's critical because BL2 won't be able to proceed
164 * without the heap info and its hash data.
165 */
166 flush_dcache_range(tb_fw_cfg_dtb, fdt_totalsize((void *)tb_fw_cfg_dtb));
167}
168#endif /* MEASURED_BOOT */
John Tsichritzisc34341a2018-07-30 13:41:52 +0100169#endif /* TRUSTED_BOARD_BOOT */
170
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000171/*
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000172 * BL2 utility function to initialize dynamic configuration specified by
Soby Mathewb6814842018-04-04 09:40:32 +0100173 * TB_FW_CONFIG. Populate the bl_mem_params_node_t of other FW_CONFIGs if
174 * specified in TB_FW_CONFIG.
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000175 */
176void arm_bl2_dyn_cfg_init(void)
177{
Soby Mathewb6814842018-04-04 09:40:32 +0100178 unsigned int i;
179 bl_mem_params_node_t *cfg_mem_params = NULL;
Louis Mayencourt6d2b5732019-12-17 13:17:25 +0000180 uintptr_t image_base;
181 size_t image_size;
Soby Mathewb6814842018-04-04 09:40:32 +0100182 const unsigned int config_ids[] = {
183 HW_CONFIG_ID,
184 SOC_FW_CONFIG_ID,
185 NT_FW_CONFIG_ID,
Achin Guptada6ef0e2019-10-11 14:54:48 +0100186#if defined(SPD_tspd) || defined(SPD_spmd)
187 /* tos_fw_config is only present for TSPD/SPMD */
Soby Mathewb6814842018-04-04 09:40:32 +0100188 TOS_FW_CONFIG_ID
189#endif
190 };
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000191
Louis Mayencourt6d2b5732019-12-17 13:17:25 +0000192 const struct dyn_cfg_dtb_info_t *dtb_info;
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000193
Soby Mathewb6814842018-04-04 09:40:32 +0100194 /* Iterate through all the fw config IDs */
195 for (i = 0; i < ARRAY_SIZE(config_ids); i++) {
196 /* Get the config load address and size from TB_FW_CONFIG */
197 cfg_mem_params = get_bl_mem_params_node(config_ids[i]);
198 if (cfg_mem_params == NULL) {
199 VERBOSE("Couldn't find HW_CONFIG in bl_mem_params_node\n");
200 continue;
201 }
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000202
Louis Mayencourt6d2b5732019-12-17 13:17:25 +0000203 dtb_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, config_ids[i]);
204 if (dtb_info == NULL) {
Soby Mathewb6814842018-04-04 09:40:32 +0100205 VERBOSE("Couldn't find config_id %d load info in TB_FW_CONFIG\n",
206 config_ids[i]);
207 continue;
208 }
209
Louis Mayencourt6d2b5732019-12-17 13:17:25 +0000210 image_base = dtb_info->config_addr;
211 image_size = dtb_info->config_max_size;
212
Soby Mathewb6814842018-04-04 09:40:32 +0100213 /*
214 * Do some runtime checks on the load addresses of soc_fw_config,
215 * tos_fw_config, nt_fw_config. This is not a comprehensive check
216 * of all invalid addresses but to prevent trivial porting errors.
217 */
218 if (config_ids[i] != HW_CONFIG_ID) {
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000219
Antonio Nino Diazb5acb3f2018-10-30 16:32:48 +0000220 if (check_uptr_overflow(image_base, image_size))
Soby Mathewb6814842018-04-04 09:40:32 +0100221 continue;
222
Usama Arife97998f2018-11-30 15:43:56 +0000223#ifdef BL31_BASE
Soby Mathewaf14b462018-06-01 16:53:38 +0100224 /* Ensure the configs don't overlap with BL31 */
Alexei Fedorov91e20c82019-12-19 11:59:31 +0000225 if ((image_base >= BL31_BASE) &&
226 (image_base <= BL31_LIMIT))
Soby Mathewb6814842018-04-04 09:40:32 +0100227 continue;
Usama Arife97998f2018-11-30 15:43:56 +0000228#endif
Soby Mathewb6814842018-04-04 09:40:32 +0100229 /* Ensure the configs are loaded in a valid address */
230 if (image_base < ARM_BL_RAM_BASE)
231 continue;
232#ifdef BL32_BASE
233 /*
234 * If BL32 is present, ensure that the configs don't
235 * overlap with it.
236 */
Alexei Fedorov91e20c82019-12-19 11:59:31 +0000237 if ((image_base >= BL32_BASE) &&
238 (image_base <= BL32_LIMIT))
Soby Mathewb6814842018-04-04 09:40:32 +0100239 continue;
240#endif
241 }
242
243
Louis Mayencourt6d2b5732019-12-17 13:17:25 +0000244 cfg_mem_params->image_info.image_base = image_base;
245 cfg_mem_params->image_info.image_max_size = (uint32_t)image_size;
Soby Mathewb6814842018-04-04 09:40:32 +0100246
Alexei Fedorov91e20c82019-12-19 11:59:31 +0000247 /*
248 * Remove the IMAGE_ATTRIB_SKIP_LOADING attribute from
249 * HW_CONFIG or FW_CONFIG nodes
250 */
Soby Mathewb6814842018-04-04 09:40:32 +0100251 cfg_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING;
252 }
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000253}