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Jens Wiklander52c798e2015-12-07 14:37:10 +01001/*
Douglas Raillarda8954fc2017-01-26 15:54:44 +00002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Jens Wiklander52c798e2015-12-07 14:37:10 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Jens Wiklander52c798e2015-12-07 14:37:10 +01005 */
6#include <arch_helpers.h>
Fu Weic2f78442017-05-27 21:21:42 +08007#include <assert.h>
Jens Wiklander52c798e2015-12-07 14:37:10 +01008#include <bl_common.h>
9#include <console.h>
10#include <debug.h>
Fu Weic2f78442017-05-27 21:21:42 +080011#include <desc_image_load.h>
Jens Wiklander0acbaaa2017-08-24 13:16:26 +020012#include <optee_utils.h>
Jens Wiklander52c798e2015-12-07 14:37:10 +010013#include <libfdt.h>
Etienne Carriere911de8c2018-02-02 13:23:22 +010014#include <platform.h>
Jens Wiklander52c798e2015-12-07 14:37:10 +010015#include <platform_def.h>
Jens Wiklander52c798e2015-12-07 14:37:10 +010016#include <string.h>
Douglas Raillarda8954fc2017-01-26 15:54:44 +000017#include <utils.h>
Isla Mitchelle3631462017-07-14 10:46:32 +010018#include "qemu_private.h"
Jens Wiklander52c798e2015-12-07 14:37:10 +010019
20/*
21 * The next 2 constants identify the extents of the code & RO data region.
22 * These addresses are used by the MMU setup code and therefore they must be
23 * page-aligned. It is the responsibility of the linker script to ensure that
24 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
25 */
26#define BL2_RO_BASE (unsigned long)(&__RO_START__)
27#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
28
Fu Weic2f78442017-05-27 21:21:42 +080029/* Data structure which holds the extents of the trusted SRAM for BL2 */
30static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
31
32#if !LOAD_IMAGE_V2
Jens Wiklander52c798e2015-12-07 14:37:10 +010033/*******************************************************************************
34 * This structure represents the superset of information that is passed to
35 * BL3-1, e.g. while passing control to it from BL2, bl31_params
36 * and other platform specific params
37 ******************************************************************************/
38typedef struct bl2_to_bl31_params_mem {
39 bl31_params_t bl31_params;
40 image_info_t bl31_image_info;
41 image_info_t bl32_image_info;
42 image_info_t bl33_image_info;
43 entry_point_info_t bl33_ep_info;
44 entry_point_info_t bl32_ep_info;
45 entry_point_info_t bl31_ep_info;
46} bl2_to_bl31_params_mem_t;
47
48
49static bl2_to_bl31_params_mem_t bl31_params_mem;
50
Jens Wiklander52c798e2015-12-07 14:37:10 +010051
52meminfo_t *bl2_plat_sec_mem_layout(void)
53{
54 return &bl2_tzram_layout;
55}
56
57/*******************************************************************************
58 * This function assigns a pointer to the memory that the platform has kept
59 * aside to pass platform specific and trusted firmware related information
60 * to BL31. This memory is allocated by allocating memory to
61 * bl2_to_bl31_params_mem_t structure which is a superset of all the
62 * structure whose information is passed to BL31
63 * NOTE: This function should be called only once and should be done
64 * before generating params to BL31
65 ******************************************************************************/
66bl31_params_t *bl2_plat_get_bl31_params(void)
67{
68 bl31_params_t *bl2_to_bl31_params;
69
70 /*
71 * Initialise the memory for all the arguments that needs to
72 * be passed to BL3-1
73 */
Douglas Raillarda8954fc2017-01-26 15:54:44 +000074 zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t));
Jens Wiklander52c798e2015-12-07 14:37:10 +010075
76 /* Assign memory for TF related information */
77 bl2_to_bl31_params = &bl31_params_mem.bl31_params;
78 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
79
80 /* Fill BL3-1 related information */
81 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
82 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
83 VERSION_1, 0);
84
85 /* Fill BL3-2 related information */
86 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
87 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
88 VERSION_1, 0);
89 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
90 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
91 VERSION_1, 0);
92
93 /* Fill BL3-3 related information */
94 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
95 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
96 PARAM_EP, VERSION_1, 0);
97
98 /* BL3-3 expects to receive the primary CPU MPID (through x0) */
99 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
100
101 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
102 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
103 VERSION_1, 0);
104
105 return bl2_to_bl31_params;
106}
107
108/* Flush the TF params and the TF plat params */
109void bl2_plat_flush_bl31_params(void)
110{
111 flush_dcache_range((unsigned long)&bl31_params_mem,
112 sizeof(bl2_to_bl31_params_mem_t));
113}
114
115/*******************************************************************************
116 * This function returns a pointer to the shared memory that the platform
117 * has kept to point to entry point information of BL31 to BL2
118 ******************************************************************************/
119struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
120{
121#if DEBUG
122 bl31_params_mem.bl31_ep_info.args.arg1 = QEMU_BL31_PLAT_PARAM_VAL;
123#endif
124
125 return &bl31_params_mem.bl31_ep_info;
126}
Fu Weic2f78442017-05-27 21:21:42 +0800127#endif /* !LOAD_IMAGE_V2 */
Jens Wiklander52c798e2015-12-07 14:37:10 +0100128
129
130
131void bl2_early_platform_setup(meminfo_t *mem_layout)
132{
133 /* Initialize the console to provide early debug support */
134 console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ,
135 PLAT_QEMU_CONSOLE_BAUDRATE);
136
137 /* Setup the BL2 memory layout */
138 bl2_tzram_layout = *mem_layout;
139
140 plat_qemu_io_setup();
141}
142
143static void security_setup(void)
144{
145 /*
146 * This is where a TrustZone address space controller and other
147 * security related peripherals, would be configured.
148 */
149}
150
151static void update_dt(void)
152{
153 int ret;
154 void *fdt = (void *)(uintptr_t)PLAT_QEMU_DT_BASE;
155
156 ret = fdt_open_into(fdt, fdt, PLAT_QEMU_DT_MAX_SIZE);
157 if (ret < 0) {
158 ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret);
159 return;
160 }
161
162 if (dt_add_psci_node(fdt)) {
163 ERROR("Failed to add PSCI Device Tree node\n");
164 return;
165 }
166
167 if (dt_add_psci_cpu_enable_methods(fdt)) {
168 ERROR("Failed to add PSCI cpu enable methods in Device Tree\n");
169 return;
170 }
171
172 ret = fdt_pack(fdt);
173 if (ret < 0)
174 ERROR("Failed to pack Device Tree at %p: error %d\n", fdt, ret);
175}
176
177void bl2_platform_setup(void)
178{
179 security_setup();
180 update_dt();
181
182 /* TODO Initialize timer */
183}
184
Etienne Carriere911de8c2018-02-02 13:23:22 +0100185#ifdef AARCH32
186#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_secure(__VA_ARGS__)
187#else
188#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_el1(__VA_ARGS__)
189#endif
190
Jens Wiklander52c798e2015-12-07 14:37:10 +0100191void bl2_plat_arch_setup(void)
192{
Etienne Carriere911de8c2018-02-02 13:23:22 +0100193 QEMU_CONFIGURE_BL2_MMU(bl2_tzram_layout.total_base,
Jens Wiklander52c798e2015-12-07 14:37:10 +0100194 bl2_tzram_layout.total_size,
195 BL2_RO_BASE, BL2_RO_LIMIT,
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900196 BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
Jens Wiklander52c798e2015-12-07 14:37:10 +0100197}
198
199/*******************************************************************************
200 * Gets SPSR for BL32 entry
201 ******************************************************************************/
202static uint32_t qemu_get_spsr_for_bl32_entry(void)
203{
Etienne Carriere911de8c2018-02-02 13:23:22 +0100204#ifdef AARCH64
Jens Wiklander52c798e2015-12-07 14:37:10 +0100205 /*
206 * The Secure Payload Dispatcher service is responsible for
207 * setting the SPSR prior to entry into the BL3-2 image.
208 */
209 return 0;
Etienne Carriere911de8c2018-02-02 13:23:22 +0100210#else
211 return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE,
212 DISABLE_ALL_EXCEPTIONS);
213#endif
Jens Wiklander52c798e2015-12-07 14:37:10 +0100214}
215
216/*******************************************************************************
217 * Gets SPSR for BL33 entry
218 ******************************************************************************/
219static uint32_t qemu_get_spsr_for_bl33_entry(void)
220{
Jens Wiklander52c798e2015-12-07 14:37:10 +0100221 uint32_t spsr;
Etienne Carriere911de8c2018-02-02 13:23:22 +0100222#ifdef AARCH64
223 unsigned int mode;
Jens Wiklander52c798e2015-12-07 14:37:10 +0100224
225 /* Figure out what mode we enter the non-secure world in */
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000226 mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
Jens Wiklander52c798e2015-12-07 14:37:10 +0100227
228 /*
229 * TODO: Consider the possibility of specifying the SPSR in
230 * the FIP ToC and allowing the platform to have a say as
231 * well.
232 */
233 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
Etienne Carriere911de8c2018-02-02 13:23:22 +0100234#else
235 spsr = SPSR_MODE32(MODE32_svc,
236 plat_get_ns_image_entrypoint() & 0x1,
237 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
238#endif
Jens Wiklander52c798e2015-12-07 14:37:10 +0100239 return spsr;
240}
241
Fu Weic2f78442017-05-27 21:21:42 +0800242#if LOAD_IMAGE_V2
243static int qemu_bl2_handle_post_image_load(unsigned int image_id)
244{
245 int err = 0;
246 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
Etienne Carriere911de8c2018-02-02 13:23:22 +0100247#if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE)
Jens Wiklander0acbaaa2017-08-24 13:16:26 +0200248 bl_mem_params_node_t *pager_mem_params = NULL;
249 bl_mem_params_node_t *paged_mem_params = NULL;
250#endif
Fu Weic2f78442017-05-27 21:21:42 +0800251
252 assert(bl_mem_params);
253
254 switch (image_id) {
Fu Weic2f78442017-05-27 21:21:42 +0800255 case BL32_IMAGE_ID:
Etienne Carriere911de8c2018-02-02 13:23:22 +0100256#if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE)
Jens Wiklander0acbaaa2017-08-24 13:16:26 +0200257 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
258 assert(pager_mem_params);
259
260 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
261 assert(paged_mem_params);
262
263 err = parse_optee_header(&bl_mem_params->ep_info,
264 &pager_mem_params->image_info,
265 &paged_mem_params->image_info);
266 if (err != 0) {
267 WARN("OPTEE header parse error.\n");
268 }
269
Etienne Carriere911de8c2018-02-02 13:23:22 +0100270#if defined(SPD_opteed)
Jens Wiklander0acbaaa2017-08-24 13:16:26 +0200271 /*
272 * OP-TEE expect to receive DTB address in x2.
273 * This will be copied into x2 by dispatcher.
274 */
275 bl_mem_params->ep_info.args.arg3 = PLAT_QEMU_DT_BASE;
Etienne Carriere911de8c2018-02-02 13:23:22 +0100276#else /* case AARCH32_SP_OPTEE */
277 bl_mem_params->ep_info.args.arg0 =
278 bl_mem_params->ep_info.args.arg1;
279 bl_mem_params->ep_info.args.arg1 = 0;
280 bl_mem_params->ep_info.args.arg2 = PLAT_QEMU_DT_BASE;
281 bl_mem_params->ep_info.args.arg3 = 0;
282#endif
Jens Wiklander0acbaaa2017-08-24 13:16:26 +0200283#endif
Fu Weic2f78442017-05-27 21:21:42 +0800284 bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl32_entry();
285 break;
Etienne Carriere911de8c2018-02-02 13:23:22 +0100286
Fu Weic2f78442017-05-27 21:21:42 +0800287 case BL33_IMAGE_ID:
Etienne Carriere911de8c2018-02-02 13:23:22 +0100288#ifdef AARCH32_SP_OPTEE
289 /* AArch32 only core: OP-TEE expects NSec EP in register LR */
290 pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
291 assert(pager_mem_params);
292 pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
293#endif
294
Fu Weic2f78442017-05-27 21:21:42 +0800295 /* BL33 expects to receive the primary CPU MPID (through r0) */
296 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
297 bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry();
298 break;
299 }
300
301 return err;
302}
303
304/*******************************************************************************
305 * This function can be used by the platforms to update/use image
306 * information for given `image_id`.
307 ******************************************************************************/
308int bl2_plat_handle_post_image_load(unsigned int image_id)
309{
310 return qemu_bl2_handle_post_image_load(image_id);
311}
312
313#else /* LOAD_IMAGE_V2 */
314
Jens Wiklander52c798e2015-12-07 14:37:10 +0100315/*******************************************************************************
316 * Before calling this function BL3-1 is loaded in memory and its entrypoint
317 * is set by load_image. This is a placeholder for the platform to change
318 * the entrypoint of BL3-1 and set SPSR and security state.
319 * On ARM standard platforms we only set the security state of the entrypoint
320 ******************************************************************************/
321void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
322 entry_point_info_t *bl31_ep_info)
323{
324 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
325 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
326 DISABLE_ALL_EXCEPTIONS);
327}
328
329/*******************************************************************************
330 * Before calling this function BL3-2 is loaded in memory and its entrypoint
331 * is set by load_image. This is a placeholder for the platform to change
332 * the entrypoint of BL3-2 and set SPSR and security state.
333 * On ARM standard platforms we only set the security state of the entrypoint
334 ******************************************************************************/
335void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
336 entry_point_info_t *bl32_ep_info)
337{
338 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
339 bl32_ep_info->spsr = qemu_get_spsr_for_bl32_entry();
340}
341
342/*******************************************************************************
343 * Before calling this function BL3-3 is loaded in memory and its entrypoint
344 * is set by load_image. This is a placeholder for the platform to change
345 * the entrypoint of BL3-3 and set SPSR and security state.
346 * On ARM standard platforms we only set the security state of the entrypoint
347 ******************************************************************************/
348void bl2_plat_set_bl33_ep_info(image_info_t *image,
349 entry_point_info_t *bl33_ep_info)
350{
351
352 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
353 bl33_ep_info->spsr = qemu_get_spsr_for_bl33_entry();
354}
355
356/*******************************************************************************
357 * Populate the extents of memory available for loading BL32
358 ******************************************************************************/
359void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
360{
361 /*
362 * Populate the extents of memory available for loading BL32.
363 */
364 bl32_meminfo->total_base = BL32_BASE;
365 bl32_meminfo->free_base = BL32_BASE;
366 bl32_meminfo->total_size = (BL32_MEM_BASE + BL32_MEM_SIZE) - BL32_BASE;
367 bl32_meminfo->free_size = (BL32_MEM_BASE + BL32_MEM_SIZE) - BL32_BASE;
368}
369
370/*******************************************************************************
371 * Populate the extents of memory available for loading BL33
372 ******************************************************************************/
373void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
374{
375 bl33_meminfo->total_base = NS_DRAM0_BASE;
376 bl33_meminfo->total_size = NS_DRAM0_SIZE;
377 bl33_meminfo->free_base = NS_DRAM0_BASE;
378 bl33_meminfo->free_size = NS_DRAM0_SIZE;
379}
Fu Weic2f78442017-05-27 21:21:42 +0800380#endif /* !LOAD_IMAGE_V2 */
Jens Wiklander52c798e2015-12-07 14:37:10 +0100381
Etienne Carriere911de8c2018-02-02 13:23:22 +0100382uintptr_t plat_get_ns_image_entrypoint(void)
Jens Wiklander52c798e2015-12-07 14:37:10 +0100383{
384 return NS_IMAGE_OFFSET;
385}